DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-36 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 29 December 2022, 29 May 2024, 16 May 2025, 01 September 2025 and 28 October 2025. The information therein was considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-36 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-26 of U.S. Patent No. 12,464,799 (‘799). Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application are recited in the claims of ‘799 with only nominal differences that would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 1-36 would be allowable if the double patenting rejection set forth in this Office action is overcome.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, a semiconductor device comprising: a semiconductor substrate with an upper surface and a channel; source and drain electrodes over the upper surface of the semiconductor substrate, wherein the source and drain electrodes are electrically coupled to the channel, and the channel extends between the source and drain electrodes; a passivation layer over the upper surface of the semiconductor substrate and between the source and drain electrodes, wherein the passivation layer includes a lower passivation sub-layer over the upper surface of the semiconductor substrate, and an upper passivation sub-layer over the lower passivation sub-layer; a gate electrode over the upper surface of the semiconductor substrate between the source and drain electrodes, wherein the gate electrode includes a lower portion that extends through the passivation layer; and a conductive field plate adjacent to the gate electrode, wherein the conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and wherein the conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer; and as recited in independent claim 18, a semiconductor device comprising: a semiconductor substrate with an upper surface and a channel; source and drain electrodes over the upper surface of the semiconductor substrate, wherein the source and drain electrodes are electrically coupled to the channel, and the channel extends between the source and drain electrodes; a passivation layer over the upper surface of the semiconductor substrate and between the source and drain electrodes, wherein the passivation layer includes a lower passivation sub-layer over the upper surface of the semiconductor substrate, an intermediate passivation sub-layer over the lower passivation sub-layer, and an upper passivation sub-layer over the intermediate passivation sub-layer; a gate electrode over the upper surface of the semiconductor substrate between the source and drain electrodes, wherein the gate electrode includes a lower portion that extends through the upper passivation sub-layer and through the intermediate passivation sub-layer; and a conductive field plate adjacent to the gate electrode, wherein the conductive field plate includes a recessed region that extends through the upper passivation sub-layer but does not extend through the lower passivation sub-layer, wherein the conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer, and wherein the lower portion of the gate electrode extends deeper into the passivation layer than the conductive field plate; and independent claim 24, a method of forming a semiconductor device, the method comprising: forming source and drain electrodes over an upper surface of a semiconductor substrate that includes a channel, wherein the source and drain electrodes are electrically coupled to the channel, and the channel extends between the source and drain electrodes; depositing a passivation layer over the upper surface of the semiconductor substrate by depositing a lower passivation sub-layer on the upper surface of the semiconductor substrate, and depositing an upper passivation sub-layer over the lower passivation sub-layer, wherein the lower passivation sub-layer is formed from a first dielectric material, and the upper passivation sub-layer is formed from a second dielectric material that is different from the first dielectric material; forming a first opening at least partially through the passivation layer between the source and drain electrodes; depositing a gate electrode over the semiconductor substrate between the source and drain electrodes, wherein the gate electrode includes a lower portion that extends into the first opening in the passivation layer; forming a second opening through the upper passivation sub-layer adjacent to the gate electrode, wherein the second opening does not extend through the lower passivation sub-layer, and the second opening is shallower than the first opening; and forming a conductive field plate over the semiconductor substrate and adjacent to the gate electrode, wherein the conductive field plate includes a recessed region that extends through the second opening in the upper passivation sub-layer but does not extend through the lower passivation sub-layer, and the conductive field plate and the upper surface of the semiconductor substrate are separated by a portion of the lower passivation sub-layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hu et al. US 2024/0395872 and Grote et al. US 2025/0142924 teach similar subject matter as the instant invention.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 1/6/2026