DETAILED ACTION
The instant application having Application No. 18/148,161 filed on 12/29/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2022/0342736) in view of Shen et al. (US 12,444,447).
As per Claim 1, Liu discloses a semiconductor device, comprising: a memory cell array including a plurality of memory cells and a plurality of bit lines (Abstract and Figure 1 and Paragraph 0023, a data processing circuit includes a phase change memory (PCM) comprising memory cells connected to bit lines); and a computing circuit configured to perform a multiplication and accumulation (MAC) operation using a plurality of input data and a plurality of weights respectively provided from the plurality of bit lines (Figures 1-4B and Paragraphs 0007-0008, 0022-0024, 0032-0034 and 0040, the computing unit 130 performs signed MAC operations using sub-sequences of bits of input data and weight data stored in and read from the memory 110, which may be a phase change in-memory architecture); wherein the memory cell array stores the plurality of weights and sign information of the plurality of weights (Figures 3-4B and Paragraphs 0007-0008, 0022, 0034 and 0040, the computing unit 130 performs signed MAC operations on bits read from the memory 110, which includes both sign bits and data bits of the operand values).
Liu does not explicitly disclose that the memory cell array includes a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, wherein one or more memory cells connected to each of the plurality of bit lines store a corresponding one of the plurality of weights, and the one or more memory cells store sign information of the corresponding weight.
However, Shen discloses a phase change memory cell array which performs in-memory MAC operations using signed weights. wherein the memory cell array includes a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, wherein one or more memory cells connected to each of the plurality of bit lines store a corresponding one of the plurality of weights, and the one or more memory cells store sign information of the corresponding weight (Title and Abstract and Figure 1 and Column 4, lines 16-30, 50-54, 62-67 and Column 5, lines 59-67 and Column 6, lines 20-22, 47-48 and 58-60, a phase change memory array for in-memory computing comprises an array of memory cells coupled between a plurality of word lines and a plurality of bit lines, each memory cell storing a bit of a weight value, wherein rows of memory cells, i.e. along word lines, store MSB to LSB of a multi-bit weights and the MSB stores the sign bit of the corresponding weight, such that a MSB column (i.e. bit line) of memory cells is a sign bit column and the remaining columns store data bits of 2n-2 to 20 bit precision).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to apply the phase change memory (PCM) and in-memory MAC processing taught by Shen as the PCM in-memory processor required by Liu because Shen stores signed weight values as required by Liu and provides reduces memory bits as compared with prior art techniques, in addition to improved accuracy and reduced noise (Shen, Column 3, lines 24-49 and Column 6, lines 55-63), and because Liu explicitly combines an in-memory computing architecture including a phase change memory such as Shen’s with a MAC compute circuit (Liu, Paragraphs 0023 and 0028), as well as providing reduced computation error for in-memory MAC processors such as the PCM in-memory processor of Shen (Liu, Paragraphs 0028).
Allowable Subject Matter
Claims 2-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Dreesen et al. (US 2022/0101914) – discloses a compute-memory circuit for performing multiply-and-accumulate operations in memory, wherein respective bits of a signed multi-bit weight value are stored in compute data storage cells and a corresponding sign bit is stored in a sign data storage cell.
Pasotti et al. (US 11,942,144) – discloses an in-memory computation system comprising an array of memory cells positioned at the intersection of word lines and bit lines, wherein a group of four memory cells may encode either a positive or negative single-bit weight value, i.e. +1, 0, or -1.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
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