DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/28/2023 and 08/11/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 20-24 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. Claim 20 recites “MASAR” in line 1; “SAR” in line 9; “MAC” in line 10; and “CDAC” in line 11. These acronyms should be spelled out in the first recitation to define how these acronyms are to be interpreted. Claims 21-22 inherit the same deficiency as claim 20 by reason of dependence.
B. Claim 21 recites “ADC” in line 8. This acronym should be spelled out to define how this acronym is to be interpreted.
C. Claim 23 recites “MASAR” in line 2; “SAR” in line 9; “MAC” in line 10; and “CDAC” in line 11. This acronym should be spelled out to define how this acronym is to be interpreted. Claim 24 inherit the same deficiency as claim 23 by reason of dependence.
D. In claim 23 line 9, “digital logic” should read “the digital logic” instead because digital logic is already introduced in line 2. Claim 24 inherit the same deficiency as claim 23 by reason of dependence.
E. In claim 23 lines 6-7, “the respective MASAR cells” should read “the plurality of MASAR cells” instead for consistency of claim terminologies. Claim 24 inherit the same deficiency as claim 23 by reason of dependence.
F. Claim 24 recites “MUX” in line 1; “and “MAC” in line 2. These acronyms should be spelled out in the first recitation to define how these acronyms are to be interpreted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 10-19 and 22-24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the value” in lines 3, 4 and 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the first recitation in line 3 is interpreted as a value instead. Claim 22 recites a similar limitation and is rejected for the same reason.
Claim 10 recites “wherein the digital output utilizes N + 1 bits for signed integer arithmetic and N bits for two's complement arithmetic”. A two's complement format is a common way for representing signed integer in a computer. Therefore, it is unclear how the digital output utilizes different number of bits for signed integer arithmetic and two's complement arithmetic because two's complement arithmetic is a signed integer arithmetic. Further clarification is required.
Claim 11 recites “
N
B
G
” in line 1; and “
2
N
r
” in line 2.
B
G
and
N
r
are not defined in the claim. Therefore, it is unclear how these two variables are related. For purposes of examination, this is interpreted as a N and
2
N
respectively. Claims 12-19 inherit the same deficiency as claim 11 by reason of dependence. Claims 13-14 recite instances of
N
B
G
and are rejected for the same reason.
Claim 17 recites “the range” in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as a range instead. Claim 19 recites a similar limitation in line 4 and is rejected for the same reason.
Claim 18 recites “the full range” in line 3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as a full range instead.
Claim 23 recites “the respective MASAR cell” in line 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as a respective MASAR cell instead. Claim 24 inherit the same deficiency as claim 23 by reason of dependence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 9 and 23 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Agrawal et al. (US 20220075596 A1), hereinafter Agrawal.
Regarding claim 1, Agrawal teaches a multiply-accumulate successive approximation (MASAR) column, comprising (Agrawal Fig. 10 MASAR column – 1000):
a plurality of MASAR cells, each including a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result, and a unit capacitor configured to store the result as analog charge (Agrawal Fig. 10 and paragraph [0070] “charge-sharing pop counter 1000 for the inner product summation circuit 254”; paragraph [0073] “Simultaneously, the product of each pair of inputs Ai, Wi is computed by digital AND gates … each capacitor 1020 stores the charge”; plurality of MASAR cells – AND gate-capacitor pairs; multiplier – AND gate 1012; input activation – Ai; operand – Wi; result – product; unit capacitor – capacitor 1020); and
digital logic configured to perform analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of the multiplication by configuring the unit capacitors as a capacitive digital to analog converter (CDAC) in a successive approximation register (SAR) analog to digital converter (ADC) (Agrawal Fig. 10 and paragraph [0072] “the same bank of capacitors 1020 is utilized for both input summation and SAR conversion”; paragraphs [0074-0076] “the switch pairs 1008 are configured to pass the output of the SAR controller 1028 (the sum switch of each switch pair 1008 is opened and the SAR switch of each switch pair 1008 is closed) such that the data output of the SAR controller 1028 controls the configuration of the transmission gates 1016. The capacitor bank is configured as an array of five binary weighted capacitances in this phase”; digital logic – SAR ADC; digital output – binary weighted code; paragraph [0079] “FIG. … 10 can be referred to as merged-CDAC”).
Regarding claim 2, Agrawal teaches all the limitations of claim 1 as stated above. Further, Agrawal teaches wherein the operands specify weights or biases of a neural network (Agrawal Figs. 2A-2B and paragraphs [0034, 0038]).
Regarding claim 5, Agrawal teaches all the limitations of claim 1 as stated above. Further, Agrawal teaches wherein the plurality of MASAR cells are configured to receive the operands from operand inputs separate from the input activation inputs (Agrawal Fig. 10).
Regarding claim 9, Agrawal teaches all the limitations of claim 1 as stated above. Further, Agrawal teaches further comprising: a comparator having a comparator input and a comparator output, wherein each of the unit capacitors is connected to the comparator input via a common bit line, and the digital logic is configured to receive the comparator output (Agrawal Fig. 10 and paragraph [0071] comparator – 1024; common bit line – 1032),
wherein the common bit line is connected to a switch controllable by a RESET line, where, when the RESET line is set the common bit line is connected to a reference voltage, and when the RESET line is unset the common bit line is disconnected from the reference voltage (Agrawal Fig. 10 and paragraphs [0071, 0073-0074] “A precharge switch 1004 is configured to connect the common node net 1032 to a Vcm voltage source … During the first operating phase, the precharge switch 1004 is closed, such that Vsum, the voltage at common node net 1032, is equal to Vcm … During the second operating phase, the precharge switch 1004 is first opened and the common node net 1032 connecting the top plates of the capacitors 1020 is allowed to electrically float” switch – 1004; reference voltage – Vcm), and
wherein the RESET line is set when performing the digital multiplication, and the RESET line is unset when performing the analog summation of the analog charge (Agrawal Fig. 10 and paragraphs [0073-0074] “During the first operating phase, the precharge switch 1004 is closed … During the second operating phase, the precharge switch 1004 is first opened and the common node net 1032 connecting the top plates of the capacitors 1020 is allowed to electrically float”).
Regarding claim 23, it is directed to a method practiced by the MASAR column of claim 1. All steps performed by the method of claim 23 would be practiced by the MASAR column of claim 1. Claim 1 analysis applies equally to claim 23.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal in view of Srivastava et al. (US 11018687 B1), hereinafter Srivastava.
Regarding claim 20, Agrawal teaches a MASAR column, comprising (Agrawal Fig. 10 MASAR column – 1000):
a plurality of MASAR cells, each including (Agrawal Fig. 10 plurality of MASAR cells – AND gate-capacitor pairs):
a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result (Agrawal Fig. 10 paragraph [0073] “Simultaneously, the product of each pair of inputs Ai, Wi is computed by digital AND gates”; multiplier – AND gate 1012; input activation – Ai; operand – Wi; result – product),
a unit capacitor configured to store the result as analog charge (Agrawal Fig. 10 and paragraph [0073] “each capacitor 1020 stores the charge”; unit capacitor – capacitor 1020), and
a switch having at least first and second inputs and an output, wherein the switch is configured to receive the result on the first input, to receive a bit-guess input from digital logic on the second input, and to apply the output to the unit capacitor (Agrawal Fig. 10 and paragraphs [0073-0074] switch -1008; first input – left input; second input – right input; bit-guess input – D input bit; digital logic – SAR ADC; output – output);
the digital logic configured to utilize a SAR to perform analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of a MAC, by controlling the individual MASAR cell unit capacitances via the bit-guess input to form a CDAC (Agrawal Fig. 10 and paragraph [0072] “the same bank of capacitors 1020 is utilized for both input summation and SAR conversion”; paragraphs [0074-0076] “the switch pairs 1008 are configured to pass the output of the SAR controller 1028 (the sum switch of each switch pair 1008 is opened and the SAR switch of each switch pair 1008 is closed) such that the data output of the SAR controller 1028 controls the configuration of the transmission gates 1016. The capacitor bank is configured as an array of five binary weighted capacitances in this phase”; digital output – binary weighted code; paragraph [0079] “FIG. … 10 can be referred to as merged-CDAC”); and
a comparator having a comparator input and a comparator output, wherein each of the unit capacitors is connected to the comparator input via a common bit line, and the digital logic is configured to receive the comparator output, wherein the common bit line is connected to a RESET switch controllable by a RESET line (Agrawal Fig. 10 and paragraph [0071] comparator – 1024; common bit line – 1032; RESET switch – 1004),
wherein the switch is further configured to be controlled by an enable MAC control line to select between (i) storing the result to the unit capacitor and (ii) utilizing the unit capacitor to determine the analog summation of the charge (Agrawal Fig. 10 and paragraphs [0073-0074] enable MAC control line – sum/SAR line), and
wherein the RESET switch is further configured to be controlled to select between (i) connecting the common bit line to a reference voltage, and (ii) disconnecting the common bit line from the reference voltage (Agrawal Fig. 10 and paragraphs [0071, 0073-0074] “A precharge switch 1004 is configured to connect the common node net 1032 to a Vcm voltage source … During the first operating phase, the precharge switch 1004 is closed, such that Vsum, the voltage at common node net 1032, is equal to Vcm … During the second operating phase, the precharge switch 1004 is first opened and the common node net 1032 connecting the top plates of the capacitors 1020 is allowed to electrically float” reference voltage – Vcm).
Agrawal does not explicitly teach a multiplexer.
However, on the same field of endeavor, Srivastava discloses a multiplexer (MUX) having at least first and second inputs and an output, wherein the MUX is controlled by a control line to select an output from the set of inputs received (Srivastava Fig. 8 and col 8 lines 43-46; 49-51 and 55-57; multiplexer – 805 or 810).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Agrawal using Srivastava and replace the switch with a 2:1 multiplexer. One of ordinary skill in the art could have substituted the switch of Agrawal for a multiplexer, and the results of the substitution would have been predictable because both a switch and a multiplexer performs the same function of selecting an input to pass through to its output based on a control/selection signal. See MPEP 2141 subsection III(B) for more information.
Therefore, the combination of Agrawal as modified in view of Srivastava teaches a multiplexer (MUX) having at least first and second inputs and an output, wherein the MUX is configured to receive the result on the first input, to receive a bit-guess input from digital logic on the second input, and to apply the output to the unit capacitor, wherein the MUX is further configured to be controlled by an enable MAC control line to select between (i) storing the result to the unit capacitor and (ii) utilizing the unit capacitor to determine the analog summation of the charge.
Regarding claim 21, Agrawal as modified in view of Srivastava teaches all the limitations of claim 20 as stated above. Further, Agrawal as modified in view of Srivastava teaches wherein:
in a store charge operation of a MAC mode, the enable MAC control line is set to store the result to the unit capacitors and the RESET switch is set to connect the unit capacitor to the reference voltage (Agrawal Fig. 10 and paragraph [0073] “During the first operating phase, the precharge switch 1004 is closed … the sum switch of each switch pair 1008-1, 1008-2, 1008-3 ... , 1008-16, ... , 1008-31 (collectively referred to as switch pairs 1008 herein) to be closed and the SAR switch to be open … Thus, each capacitor 1020 stores the charge”),
in a sum charge operation of the MAC mode, the enable MAC control line is set to store the result to the unit capacitors and the RESET switch is unset to disconnect the unit capacitors from the reference voltage (Agrawal Fig. 10 and paragraphs [0073-0074] “During the second operating phase, the precharge switch 1004 is first opened and the common node net 1032 connecting the top plates of the capacitors 1020 is allowed to electrically float”), and
in an ADC conversion mode, the enable MAC control line is set to connect the bit- guess input of the digital logic to the unit capacitor and the RESET switch is unset to disconnect the unit capacitors from the reference voltage (Agrawal Fig. 10 and paragraph [0074] “During the second operating phase, the precharge switch 1004 is first … Next, the switch pairs 1008 are configured to pass the output of the SAR controller 1028 (the sum switch of each switch pair 1008 is opened and the SAR switch of each switch pair 1008 is closed) such that the data output of the SAR controller 1028 controls the configuration of the transmission gates 1016”).
Claims 3-4 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal as applied to claim 1 above, and further in view of Lee et al. (US 20230370082 A1), hereinafter Lee.
Regarding claim 3, Agrawal teaches all the limitations of claim 1 as stated above.
Agrawal does not explicitly teach wherein each of the plurality of MASAR cells further includes a memory configured to maintain the operand.
However, on the same field of endeavor, Lee discloses a MAC cell that includes a memory configured to maintain an operand (Lee Figs. 2-3 and 5 and paragraphs [0042-0044] “The 6-transistor bit cell portion 320 can be used for storage, and to read and write data”; memory - bit cell portion 320).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Agrawal using Lee and configure each MASAR cell to include a memory for storing the weight input in order to increase processing speed by implementing compute-in-memory bitcells that not only store filter weights but also function to multiply the stored filter weights with input bits from an input vector (Lee paragraph [0005]).
Therefore, the combination of Agrawal as modified in view of Lee teaches wherein each of the plurality of MASAR cells further includes a memory configured to maintain the operand.
Regarding claim 4, Agrawal as modified in view of Lee teaches all the limitations of claim 3 as stated above. Further, Agrawal as modified in view of Lee teaches wherein each memory has a memory input and a memory output, and each of the plurality of MASAR cells further includes a column select control line connected to the memory, wherein the memory is configured to utilize the value on the column select control line to switch between (i) saving the value on the memory input to the memory as the operand and (ii) applying the value in the memory from the memory output to the multiplier (Lee Figs. 2-3 and 5 and paragraphs [0044-0045] column select control line – line connected to the switch).
Regarding claim 11, Agrawal teaches all the limitations of claim 1 as stated above. Further, Agrawal teaches wherein the digital output is an
N
B
G
bit value,
2
N
r
(Agrawal Fig. 10 and paragraph [0074]
N
B
G
bit value – D<4:0>).
Agrawal does not explicitly teach the plurality of MASAR cells includes at least
2
N
r
cells.
However, on the same field of endeavor, Lee discloses a digital output by an ADC having an N-bit value and a plurality of compute cells in a column including at least
2
N
cells (Lee Fig. 2 and paragraphs [0040, 0049] N – 8-bit).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Agrawal using Lee and configure the MASAR column to include at least
2
N
cells in order to reduce data acquisition cycles and increase efficiency as more inputs can be multiplied at a time (Lee paragraph [0005]).
Therefore, the combination of Agrawal as modified in view of Lee wherein the digital output is an
N
B
G
bit value, and the plurality of MASAR cells includes at least
2
N
r
cells.
Regarding claim 12, Agrawal as modified in view of Lee teaches all the limitations of claim 11 as stated above. Further, Agrawal as modified in view of Lee teaches wherein the digital logic is configured to control the individual MASAR cell unit capacitances via a bit-guess input to form the capacitive digital to analog converter (CDAC) (Agrawal Fig. 10 and paragraphs [0074-0076]).
Regarding claim 13, Agrawal as modified in view of Lee teaches all the limitations of claim 12 as stated above. Further, Agrawal as modified in view of Lee teaches wherein the bit-guess input is
N
B
G
bits wide from M = 0:
N
B
G
-
1
, and each bit guess line M is connected to
2
M
of the plurality of MASAR cells (Agrawal Fig. 10 and paragraphs [0074-0076] “The capacitor bank is configured as an array of five binary weighted capacitances in this phase, i.e. the first capacitor 1020-1 is connected to the least significant bit (LSB) D0 output of the SAR controller 1028, capacitors 1020-2 and 1020-3 are connected to the second bit D1 output of the SAR controller 1028, ... and capacitors 1020-15 to capacitors 1020-31 are connected to the most significant bit (MSB) D4”).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Agrawal in view of Srivastava as applied to claim 21 above, and further in view of Lee.
Regarding claim 22, Agrawal teaches all the limitations of claim 21 as stated above.
Agrawal does not explicitly teach wherein each of the plurality of MASAR cells further includes a memory having a memory input and a memory output, the memory configured to maintain the operand and a column select control line connected to the memory, wherein the memory is configured to utilize the value on the column select control line to switch between (i) saving the value on the memory input to the memory as the operand and (ii) applying the value in the memory from the memory output to the multiplier.
However, on the same field of endeavor, Lee discloses a MAC cell that includes a memory configured to maintain an operand (Lee Figs. 2-3 and 5 and paragraphs [0042-0044] “The 6-transistor bit cell portion 320 can be used for storage, and to read and write data”; memory - bit cell portion 320). Further, Lee discloses the MAC cell including a column select control line connected to the memory, wherein the memory is configured to utilize the value on the column select control line to switch between (i) saving the value on the memory input to the memory as the operand and (ii) applying the value in the memory from the memory output to the multiplier ((Lee Figs. 2-3 and 5 and paragraphs [0044-0045] column select control line – line connected to the switch).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Agrawal using Lee and configure each MASAR cell to include a memory for storing the weight input and a column select control line configured to switch between (i) saving the value on the memory input to the memory as the operand and (ii) applying the value in the memory from the memory output to the multiplier in order to increase processing speed by implementing compute-in-memory bitcells that not only store filter weights but also function to multiply the stored filter weights with input bits from an input vector (Lee paragraph [0005]).
Therefore, the combination of Agrawal as modified in view of Lee teaches wherein each of the plurality of MASAR cells further includes a memory having a memory input and a memory output, the memory configured to maintain the operand and a column select control line connected to the memory, wherein the memory is configured to utilize the value on the column select control line to switch between (i) saving the value on the memory input to the memory as the operand and (ii) applying the value in the memory from the memory output to the multiplier.
Claims 6-8 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal as applied to claims 1 and 23 above, and further in view of Srivastava.
Regarding claim 6, Agrawal teaches all the limitations of claim 1 as stated above. Further, Agrwal teaches
wherein each of the plurality of MASAR cells further includes switch having at least first and second switch inputs and a switch output, wherein the switch is configured to receive the result on the first switch input, to receive a bit-guess input from the digital logic on the second switch input, and to apply the switch output to the unit capacitor (Agrawal Fig. 10 and paragraphs [0073-0074] switch -1008; first input – left input; second input – right input; bit-guess input – D input bit; digital logic – SAR ADC; output – output),
wherein the switch is further configured to be controlled by an enable MAC control line to select between (i) storing the result to the unit capacitor and (ii) utilizing the unit capacitor to determine the analog summation of the charge (Agrawal Fig. 10 and paragraphs [0073-0074] enable MAC control line – sum/SAR line).
Agrawal does not explicitly teach a multiplexer.
However, on the same field of endeavor, Srivastava discloses a multiplexer (MUX) having at least first and second inputs and an output, wherein the MUX is controlled by a control line to select an output from the set of inputs received (Srivastava Fig. 8 and col 8 lines 43-46; 49-51 and 55-57; multiplexer – 805 or 810).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Agrawal using Srivastava and replace the switch with a 2:1 multiplexer. One of ordinary skill in the art could have substituted the switch of Agrawal for a multiplexer, and the results of the substitution would have been predictable because both switch and multiplexer performs the same function of selecting an input to pass through to its output based on a control/selection signal. See MPEP 2141 subsection III(B) for more information.
Therefore, the combination of Agrawal as modified in view of Srivastava teaches wherein each of the plurality of MASAR cells further includes a multiplexer (MUX) having at least first and second MUX inputs and a MUX output, wherein the MUX is configured to receive the result on the first MUX input, to receive a bit-guess input from the digital logic on the second MUX input, and to apply the MUX output to the unit capacitor, wherein the MUX is further configured to be controlled by an enable MAC control line to select between (i) storing the result to the unit capacitor and (ii) utilizing the unit capacitor to determine the analog summation of the charge.
Regarding claim 7, Agrawal as modified in view of Srivastava teaches all the limitations of claim 6 as stated above. Further, Agrawal as modified in view of Srivastava teaches where the digital logic is further configured to utilize SAR to convert the analog charge to a digital result, by controlling the individual MASAR cell unit capacitances via the bit-guess input to form the CDAC (Agrawal Fig. 10 and paragraphs [0074, 0079]).
Regarding claim 8, Agrawal as modified in view of Srivastava teaches all the limitations of claim 7 as stated above. Further, Agrawal as modified in view of Srivastava teaches wherein the SAR includes guessing a plurality of bits of the digital output of the multiplication from most significant bit to least significant bit (Agrawal Fig. 10 and paragraphs [0075-0076]).
Regarding claim 24, it is directed to a method practiced by the MASAR column of claim 6. All steps performed by the method of claim 24 would be practiced by the MASAR column of claim 6. Claim 6 analysis applies equally to claim 24.
Allowable Subject Matter
Claims 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejections discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
Agrawal is the closest prior art found. Agrawal teaches a mixed signal circuit comprising a plurality of multipliers each for performing digital multiplication, a plurality of capacitors each for storing a respective product as an analog charge, and a digital logic for performing analog summation and analog to digital conversion using the plurality of capacitors as CDAC in a SAR ADC. The SAR is configured to generate N-bit output, where a corresponding one bit is applied to each capacitor during the conversion phase such that the plurality of capacitors are configured as an array of binary weighted capacitances. However, Agrawal fails to explicitly teach applying the N-bit output to only a subset of the plurality of capacitors. Therefore, Agrawal fails to explicitly teach or suggest “wherein the bit-guess input is M < MAX(
N
B
G
) bits wide from M = 0: MAX(
N
B
G
) – X and each bit guess line M is connected to
2
M
+
X
of the plurality of MASAR cells, thereby providing a coarse-precision mapping of the analog charge of the unit capacitors to determine the digital output” as recited in claim 14; “wherein bit guess line is connected to a spatially randomized set of the plurality of MASAR cells across the MASAR column” as recited in claim 15; and “wherein a first subset of the plurality of MASAR cells are connected to the bit-guess input for ADC conversion, and a second subset of the MASAR cells are connected to a reference voltage to perform a conversion range shift” as recited in claim 16.
Srivastava (US 11,018,687 B1) discloses MASAR column, comprising: a plurality of MASAR cells, each including a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result, a memory configured to store the operand and provide the operand to the multiplier, and a unit capacitor configured to store the result as analog charge; and digital logic configured to perform analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of the multiplication by configuring the unit capacitors as CDAC in a SAR ADC. However, Srivastava is silent as to how the output of the ADC is connected to the capacitors. Therefore, Srivastava fails to explicitly teach or suggest “wherein the bit-guess input is M < MAX(
N
B
G
) bits wide from M = 0: MAX(
N
B
G
) – X and each bit guess line M is connected to
2
M
+
X
of the plurality of MASAR cells, thereby providing a coarse-precision mapping of the analog charge of the unit capacitors to determine the digital output” as recited in claim 14; “wherein bit guess line is connected to a spatially randomized set of the plurality of MASAR cells across the MASAR column” as recited in claim 15; and “wherein a first subset of the plurality of MASAR cells are connected to the bit-guess input for ADC conversion, and a second subset of the MASAR cells are connected to a reference voltage to perform a conversion range shift” as recited in claim 16.
Yang et al. (US 20220276835 A1) discloses a MAC circuit configured to reuse the MAC capacitors as SAR ADC capacitors. The SAR is configured to generate an output, where the output is applied to each capacitor during the conversion phase. However, Yang fails to explicitly teach applying the output to only a subset of the plurality of capacitors. Therefore, Yang fails to explicitly teach or suggest “wherein the bit-guess input is M < MAX(
N
B
G
) bits wide from M = 0: MAX(
N
B
G
) – X and each bit guess line M is connected to
2
M
+
X
of the plurality of MASAR cells, thereby providing a coarse-precision mapping of the analog charge of the unit capacitors to determine the digital output” as recited in claim 14; “wherein bit guess line is connected to a spatially randomized set of the plurality of MASAR cells across the MASAR column” as recited in claim 15; and “wherein a first subset of the plurality of MASAR cells are connected to the bit-guess input for ADC conversion, and a second subset of the MASAR cells are connected to a reference voltage to perform a conversion range shift” as recited in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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