DETAILED ACTION
1. Claims 1-27 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
3. Claim 4 objected to because of the following informalities: Claim 4 recites “provide provides” in line 3. This appears to be typographical error and the word “provides” being in error. Appropriate correction is required.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claim(s) 1 and 5-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chettuvetty et al (hereafter Chettuvetty)(US Pub. 20210271959).
6. As to claim 1, Chettuvetty discloses a multiply-accumulate successive approximation (MASAR) array (abstract, array, [0018] successive approximation) for performing a plurality of parallel multiply-accumulate (MAC) calculations, ([0006]-[0007] MAC operations) comprising:
a plurality of MASAR columns, each MASAR column including a plurality of MASAR cells ([0007] array of memory cells arranged in rows and columns), each of the MASAR cells including a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result ([0008] for each bit multiplying the bit with the weight stored in each memory cell, by activating each memory cell based on a state of the bit to produce a weighted bit-line current from each activated memory cell proportional to a product of the bit and the weight stored therein.), and a unit capacitor configured to store the result as analog charge ([0058] charge storage element/capacitor); and
global digital logic configured to control analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of the multiplication by configuring the unit capacitors as a capacitive digital to analog converter (CDAC) in a successive approximation register (SAR) analog to digital converter (ADC) ([0062]-[0064]).
7. As to claim 5, Chettuvetty discloses wherein each of the plurality of MASAR columns includes local SAR digital logic, and the global digital logic is further configured to utilize the local SAR digital logic of each of the MASAR columns to perform parallel ADC conversion of the analog charge for each of the plurality of MASAR columns ([0062]-[0067]).
8. As to claim 6, Chettuvetty discloses wherein the local SAR digital logic is configured to apply ADC guess signals through the respective MASAR column to each MASAR cell of the respective MASAR column ([0062]-[0064]).
9. As to claim 7, Chettuvetty discloses wherein each of the MASAR cells includes a memory, and the global digital logic is configured to apply input activations to row drivers in a MAC mode, and to provide provides weight memory values for programming the operands to the memories in a weight programming mode ([0008]).
10. As to claim 8, Chettuvetty discloses wherein the digital output of each of the plurality of MASAR columns is an N bit value, and the plurality of MASAR cells of each MASAR column include at least 2^N cells ([0007]-[0008]).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chettuvetty in view of Singh et al (hereafter Singh)(US Pat 12580575).
12. As to claim 2, Chettuvetty does not disclose a row driver configured to selectively connect a row driver input to a respective one of the inputs to the plurality of MASAR columns; and
global SAR digital logic, configured to utilize the row driver to iteratively connect to the input of each of the plurality of MASAR columns and to a respective comparator of the MASAR column to serially perform ADC conversion of the analog charge utilizing the global SAR digital logic for each of the plurality of MASAR columns.
13. However, Singh discloses a row driver configured to selectively connect a row driver input to a respective one of the inputs to the plurality of MASAR columns (Column 2, line 39-column 3 line 12, comparator driver); and
global SAR digital logic, configured to utilize the row driver to iteratively connect to the input of each of the plurality of MASAR columns and to a respective comparator of the MASAR column to serially perform ADC conversion of the analog charge utilizing the global SAR digital logic for each of the plurality of MASAR columns (Column 11, lines 4-28; column 14, lines 44-54 … cause the comparator circuit and the storage circuits to perform successive approximation analog to digital conversion.).
14. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Chettuvetty, by incorporating the comparator driver and to serially perform ADC conversion of the analog charge utilizing the global SAR digital logic for each of the plurality of MASAR columns, as taught by Singh, in order to process data efficiently in the digital domain (Singh, column 1, lines 20-40).
15. As to claim 3, the combination of Chettuvetty and Singh discloses wherein the global SAR digital logic is configured to apply ADC guess signals to the row driver input during SAR mode (Chettuvetty, ([0062]-[0064]).
16. As to claim 4, the combination of Chettuvetty and Singh discloses wherein each of the MASAR cells includes a memory, and the global SAR digital logic is configured to apply input activations to the row driver in a MAC mode, and to provide provides weight memory values for programming the operands to the memories in a weight programming mode (Chettuvetty, [0008]).
Allowable Subject Matter
18. Claims 9-27 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least a plurality of scalars, each configured to digitally scale the single-bit digital outputs of each MASAR column by the bit significance to produce scaled digital outputs; and an adder configured to add the scaled digital outputs to produce a multi-bit digital result of the multiplication as in claim 9; and a plurality of scalars, each configured to digitally scale the intermediate results of each MASAR column by the bit significance to produce scaled digital outputs; an adder configured to add the scaled digital outputs; and control logic configured to iterate the single row of MASAR cells through each bit of the multi-bit input activation and to utilize the adder to sum a multi-bit digital result of the multiplication, as in claim 18.
The closest prior art of record US Pub. 20210271959 teaches architecture for performing multi-bit multiplication. However, the prior art of record does not teach or suggest at least a plurality of scalars, each configured to digitally scale the single-bit digital outputs of each MASAR column by the bit significance to produce scaled digital outputs; and an adder configured to add the scaled digital outputs to produce a multi-bit digital result of the multiplication as in claim 9; and a plurality of scalars, each configured to digitally scale the intermediate results of each MASAR column by the bit significance to produce scaled digital outputs; an adder configured to add the scaled digital outputs; and control logic configured to iterate the single row of MASAR cells through each bit of the multi-bit input activation and to utilize the adder to sum a multi-bit digital result of the multiplication, as in claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pat. 9425814 – related to analog-to-digital converters (ADCs), and more particularly, to flash-assisted successive approximation register (SAR) ADCs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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