D ETAILED ACTION This office acknowledges receipt of the following items from the Applicant: Information Disclosure Statement (IDS) filed on 12/29/22 was considered. Claims 1-20 are presented for examination. Specification Title The title of the invention is too long and overly descriptive. A new t itle is required which should be concise and clearly indicative of the invention to which the claims are directed to. Claim Rejections - 35 U S C § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- 6 and 8-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar et al, U.S. Patent Application No. 2019/0259807. With regard to claim 1 and 16 , Kumar discloses a semiconductor device (fig. 11, 6 0 0) comprising (fig. 1, a magneto-resistive random access memory formed at a backside of a wafer (MRAM) ( Fig. 11, Examiner’s Mark-up, back MTJ 217) (page 5, [0063], line 4) ; a micro stud ( Fig. 11, Examiner’s Mark-up, 212 ) electrically connecting the MRAM to a source/drain (S/D) ( Fig. 11, Examiner’s Mark-up, S/D) of a transistor ( Fig. 11, Examiner’s Mark-up, transistor 608) . With regard to claim 2 , Kumar discloses further comprising a silicide layer (fig. 11, Ti material (i.e. silicide, layer) is electrically connecting the MRAM ( Fig. 11, Examiner’s Mark-up, MRAM (MTJ 217)) with the micro stud ( Fig. 11, Examiner’s Mark-up, MRAM , 212). With regard to claim 3 , Kumar discloses wherein the S/D ( Fig. 11, Examiner’s Mark-up, source/drain S/D ) is directly electrically connected to the MRAM ( Fig. 11, Examiner’s Mark-up, MRAM (MTJ 217)) with the micro stud ( Fig. 11, Examiner’s Mark-up, 212). With regard to claim 4 and 17 , Kumar discloses wherein the micro stud ( Fig. 11, Examiner’s Mark-up, 212) and the silicide layer (fig. 11, Ti material ( Ti consists of silicide, layer) are aligned with the S/D ( Fig. 11, Examiner’s Mark-up, source/drain S/D ) of the transistor (( Fig. 11, Examiner’s Mark-up, transistor 608) . With regard to claim 5, 6, 13 and 18 , Kumar discloses wherein the micro stud ( Fig. 11, Examiner’s Mark-up, 212) has a critical dimension (CD) that is smaller than a width of the MRAM ( Fig. 11, Examiner’s Mark-up, the micro stud 212 encased by the shallow trench isolation region 104) (labeled as 104 in fig. 1) & (Fig. 11, Examiner’s Mark-up, (labeled as 104 in fig. 1, see also paragraph [0045]), which is smaller than a width of the MRAM) (see also page 3, [0045]) ( also with regard to claim 6 and 19 ). With regard to claim 8, 9, and 14 , Kumar discloses device further comprising: a backside power distribution network at the backside of the wafer; and a bit line connection via interconnecting the MRAM to a bit line at the backside power distribution network (page 1, [0007]) . With regard to claim 10 , Kumar further comprising: a word line (fig. 12, WL 0 -WL n ) electrical connection interconnecting the MRAM (fig. 12, 712 MTJ) to a word line (fig. 12, WL 0 -WL n ) at a front side of the wafer (fig. 12, FRONT 704) ; and a source line electrical (fig. 12, source line 708) connection interconnecting the MRAM (fig. 12, 712 MTJ) o f a source line (fig. 12, source line 708) at a front side of the wafer (fig. 12, FRONT 704 ) . With regard to claim 11 and 15 , Kumar discloses , wherein a logic region placeholder is encased in interlayer dielectric during formation of the micro stud (page 3, [0043]) (fig. 12) . With regard to claim 12 , Kumar discloses a semiconductor device ( Fig. 11, Examiner’s Mark-up, 600) comprising: a magneto-resistive random access memory (MRAM) formed at a backside of a wafer (MRAM) ( Fig. 11, Examiner’s Mark-up, back MTJ 217) (page 5, [0063], line 4) ; a micro stud ( Fig. 11, Examiner’s Mark-up, 212) directly electrically connecting the MRAM to a source/drain (S/D) of a transistor ( Fig. 11, Examiner’s Mark-up, source/drain terminal S/D) of a transistor ( Fig. 11, Examiner’s Mark-up, i.e. transistor 608) via an intermediate silicide layer ( Examiner’s Mark-up, Ti material ( Ti layer, consists t o silicide material ) is electrically connecting the MRAM ( Examiner’s Mark-up, MRAM (MTJ 217)) with the micro stud ( Examiner’s Mark-up, 212) , Allowable Subject Matter Claim s 7 and 20 are objected as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not show the limitation of wherein the MRAM has a pillar size of 2 contacted poly pitch (CPP) Conclusion . The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Manipatruni et al ( 2020/0006627 ) disclose s a memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side , and Yokoyama et al (US 11,043,532) discloses a semiconductor device according to an embodiment of the present technology, and the semiconductor device includes: a first substrate provided with a memory array; and a second substrate that is stacked with the first substrate, and is provided with a peripheral circuit that controls operation of the memory array . When responding to the office action, Applicants’ are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)). Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha , whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov Should you have questions on access to the Private Pair system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /CONNIE C YOHA/ Primary Examiner, Art Unit 2825