Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 4/8/26 was considered
Claims 7 and 20 are canceled.
Claims 1-6 and 8-19 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Kumar et al, Patent Application No. 2019/0259807 in view of Lin et al, Patent Application US 2023/0268910.
With regard to claims 1,12 and 16, Kumar discloses a semiconductor device (see fig. 11, Examiner’s Mark-Up, (fig. 11, 600) comprising: a magneto-resistive random access memory (MRAM) formed at a backside of a wafer (fig. 11, Kurmar Examiner’s Mark-Up, back MTJ 217) (page 5, [0063], line 4); a micro stud (fig. 11, Kurmar, Examiner’s Mark-Up, 212) electrically connecting the MRAM to a source/drain (S/D) (fig. 11, Kumar, Examiner’s Mark-up, S/D) of a transistor (fig. 1, Examiner’s Mar-up, transistor 608). Kumar, does not disclose wherein the MRAM has a pillar size of 2 contacted poly pitch (CCP). However, Lin discloses an MRAM memory device having an MRAM pillar with size of 2 contacted poly pitch (see Examiner’s markup of Lin’s Figure 8B, MRAM PILLAR and with size of 2 contacted poly pitch CPP1 + CPP2) (page 2, [0117]). Therefore, it would have been obvious for one having an ordinary skill in the art, before the effective filing date, to implement MRAM pillar having pillar size of 2 contact poly pitch (CPP1 and CPP3) as taught by Lin’s into Kumar’s MRAM memory to accommodate the MRAM cell within the logic pitch layout while providing adequate area fabrication and electrical contact.
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With regard to claim 2, Kumar discloses further comprising a silicide layer (fig.
11, Ti material (i.e. silicide, layer) is electrically connecting the MRAM (Fig. 11,
Examiner’s Mark-up, MRAM (MTJ 217)) with the micro stud (Fig. 11, Examiner’s Mark-
up, MRAM, 212).
With regard to claim 3, Kumar discloses wherein the S/D (Fig. 11, Examiner’s
Mark-up, source/drain S/D ) is directly electrically connected to the MRAM (Fig. 11,
Examiner’s Mark-up, MRAM (MTJ 217)) with the micro stud (Fig. 11, Examiner’s Mark-
up, 212).
With regard to claim 4 and 17, Kumar discloses wherein the micro stud (Fig.
11, Examiner’s Mark-up, 212) and the silicide layer (fig. 11, Ti material (Ti consists of
silicide, layer) are aligned with the S/D (Fig. 11, Examiner’s Mark-up, source/drain S/D )
of the transistor (Fig. 11, Examiner’s Mark-up, transistor 608).
With regard to claim 5, 13 and 18, Kumar discloses wherein the micro stud
(Fig. 11, Examiner’s Mark-up, 212) has a critical dimension (CD) that is smaller than a
width of the MRAM (Fig. 11, Examiner’s Mark-up, the micro stud 212 encased by the
shallow trench isolation region 104) (labeled as 104 in fig. 1) & (Fig. 11, Examiner’s
Mark-up, (labeled as 104 in fig. 1, see also paragraph [0045]), which is smaller than a
width of the MRAM) (see also page 3, [0045]) (also with regard to claim 6 and 19).
With regard to claim 8, 9, and 14, Kumar discloses device further comprising: a
backside power distribution network at the backside of the wafer; and a bit line connection via interconnecting the MRAM to a bit line at the backside power distribution
network (page 1, [0007]).
With regard to claim 10, Kumar further comprising: a word line (fig. 12, WL0-
WLn) electrical connection interconnecting the MRAM (fig. 12, 712 MTJ) to a word line
(fig. 12, WL0-WLn) at a front side of the wafer (fig. 12, FRONT 704); and a source line
electrical (fig. 12, source line 708) connection interconnecting the MRAM (fig. 12, 712
MTJ) of a source line (fig. 12, source line 708) at a front side of the wafer (fig. 12,
FRONT 704).
With regard to claim 11 and 15, Kumar discloses, wherein a logic region
placeholder is encased in interlayer dielectric during formation of the micro stud (page
3, [0043]) (fig. 12).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Chu et al (20210376093) discloses a semiconductor memory device having a backside source contact electrically coupled to a source/drain region, an intervening silicide layer for reducing contact resistance, a self-aligned backside contact structure, and a backside power rail. However, Cho does not teach or suggest claimed MRAM formed at the backside of the wafer, an MRAM pillar having a side of 2 cpp, or a micro stud electrically connecting the MRAM to the transistor source/drain.
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) days from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825
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