DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1, 2, 4, 11, 12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Al-Shamma (US Pub. 20200020393).
5. As to claim 1, Al-Shamma discloses a hybrid structure for computing-in-memory applications (abstract and [0028], which is controlled by a first word line and a second word line ([0019] word lines), and the hybrid structure for computing-in-memory applications comprising:
at least one memory cell storing a weight, wherein the at least one memory cell is controlled by the first word line and comprises a local bit line transmitting the weight ([0005] and [0024]-[0026]; and
at least one digital-analog-hybrid local computing cell controlled by the second word line and having a plurality of input lines, a digital output line and an analog output line, wherein the input lines are configured to transmit a plurality of multi-bit input values ([0031]-[0033] … the output control lines might comprise bit lines of an NVM array coupled to output terminals of individual NVM cells; and [0035]), and the at least one digital-analog-hybrid local computing cell comprises:
at least one digital local computing cell connected to the at least one memory cell, wherein the at least one digital local computing cell receives the weight via the local bit line and is configured to generate a digital output value on the digital output line according to a higher bit of the multi-bit input values multiplied by the weight ([0039] and [0048]); and
at least one voltage local computing cell connected to the at least one memory cell and the at least one digital local computing cell, wherein the at least one voltage local computing cell receives the weight via the local bit line and is configured to generate an analog output value on the analog output line according to a lower bit of the multi-bit input values multiplied by the weight ([0045]-[0049]).
6. As to claims 2 and 12, Al-Shamma discloses wherein the at least one digital local computing cell comprises: a first digital transistor connected between the at least one memory cell and the digital output line, wherein the first digital transistor is controlled by the higher bit; and a second digital transistor connected to the first digital transistor, wherein the second digital transistor is controlled by an inverted higher bit opposite to the higher bit ([0060]).
7. As to claims 4 and 14, Al-Shamma discloses a local digital adder tree connected to the at least one digital local computing cell via the digital output line; wherein a number of the at least one digital local computing cell is plural, the digital local computing cells are configured to generate a plurality of the digital output values on a plurality of the digital output lines according to a plurality of the higher bits of the multi-bit input values multiplied by the weight, and the local digital adder tree is configured to receive the digital output values and add the digital output values to generate a digital partial multiply-and-accumulate value ([0058] and [0074] adder circuitry).
8. As to claim 11, the claim is rejected for similar reasons as claim 11 above.
Allowable Subject Matter
9. Claims 3, 5-10,13, and 15-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least wherein the at least one voltage local computing cell comprises: a first analog transistor connected between the at least one memory cell and the analog output line, wherein the first analog transistor is controlled by the lower bit; a second analog transistor connected to the first analog transistor, wherein the second analog transistor is controlled by an inverted lower bit opposite to the lower bit; and a third analog transistor connected to the first analog transistor and the second analog transistor, wherein the third analog transistor is controlled by an enable signal, as in claims 3 and 13;
at least one analog-to-digital converter connected to the at least one voltage local computing cell via the analog output line; wherein a number of the at least one digital-analog-hybrid local computing cell is plural, the digital-analog-hybrid local computing cells are configured to generate a plurality of the analog output values on the analog output line, an analog shared output value is formed by charge sharing according to the analog output values, and the at least one analog-to-digital converter is configured to receive the analog shared output value and convert the analog shared output value into an analog partial multiply-and-accumulate value, as in claims 5 and 15;
and
wherein, a number of the at least one memory cell is plural, and the memory cells comprise a first memory cell storing a first weight, a second memory cell storing a second weight and a third memory cell storing a third weight; a number of the at least one digital local computing cell is plural, a number of the at least one voltage local computing cell is plural, and the at least one digital-analog-hybrid local computing cell further comprises: a first column structure connected to the first memory cell, wherein the first column structure comprises a first global bit line, a first global bit line bar, seven of the digital local computing cells and one of the voltage local computing cells; a second column structure connected to the second memory cell, wherein the second column structure comprises a second global bit line, a second global bit line bar, six of the digital local computing cells and two of the voltage local computing cells; and a third column structure connected to the third memory cell, wherein the third column structure comprises a third global bit line, a third global bit line bar and first eight of the digital local computing cells; and the one of the voltage local computing cells of the first column structure is connected to the first global bit line bar, the two of the voltage local computing cells of the second column structure are connected to the second global bit line and the third global bit line, respectively, and the second column structure is connected between the first column structure and the third column structure, as in claims and 7 and 17.
The closest prior art of record US Pub. 20200020393 teaches the claimed hybrid structure for computing-in-memory applications. However, the prior art of record does not teach or suggest at least wherein the at least one voltage local computing cell comprises: a first analog transistor connected between the at least one memory cell and the analog output line, wherein the first analog transistor is controlled by the lower bit; a second analog transistor connected to the first analog transistor, wherein the second analog transistor is controlled by an inverted lower bit opposite to the lower bit; and a third analog transistor connected to the first analog transistor and the second analog transistor, wherein the third analog transistor is controlled by an enable signal, as in claims 3 and 13;
at least one analog-to-digital converter connected to the at least one voltage local computing cell via the analog output line; wherein a number of the at least one digital-analog-hybrid local computing cell is plural, the digital-analog-hybrid local computing cells are configured to generate a plurality of the analog output values on the analog output line, an analog shared output value is formed by charge sharing according to the analog output values, and the at least one analog-to-digital converter is configured to receive the analog shared output value and convert the analog shared output value into an analog partial multiply-and-accumulate value, as in claims 5 and 15;
and
wherein, a number of the at least one memory cell is plural, and the memory cells comprise a first memory cell storing a first weight, a second memory cell storing a second weight and a third memory cell storing a third weight; a number of the at least one digital local computing cell is plural, a number of the at least one voltage local computing cell is plural, and the at least one digital-analog-hybrid local computing cell further comprises: a first column structure connected to the first memory cell, wherein the first column structure comprises a first global bit line, a first global bit line bar, seven of the digital local computing cells and one of the voltage local computing cells; a second column structure connected to the second memory cell, wherein the second column structure comprises a second global bit line, a second global bit line bar, six of the digital local computing cells and two of the voltage local computing cells; and a third column structure connected to the third memory cell, wherein the third column structure comprises a third global bit line, a third global bit line bar and first eight of the digital local computing cells; and the one of the voltage local computing cells of the first column structure is connected to the first global bit line bar, the two of the voltage local computing cells of the second column structure are connected to the second global bit line and the third global bit line, respectively, and the second column structure is connected between the first column structure and the third column structure, as in claims and 7 and 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20210124793 – related to an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.
US Pub. 20210150328 – related to computing apparatuses. More specifically, embodiments disclosed herein relate to hierarchical hybrid network-on-chip architectures for compute-in-memory probabilistic machine learning accelerators.
US Pub. 20210271597 – related to in-memory computing and matrix-vector multiplication.
US Pub. 20220236869 – related to in-memory computing, or compute-in-memory (“CIM”), and more specifically relates to memory arrays used in data processing, such as multiply-accumulate (“MAC”) operations. Compute-in-memory or in-memory computing systems store information in the main random-access memory (RAM) of computers and perform calculations at memory cell level, rather than moving large quantities of data between the main RAM and data store for each computation step
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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