DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1–20 are pending for examination in the reply filed on 07/07/2026.
Claim Rejections - 35 USC § 101 (Computer Medium)
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
3. Claims 15–20 are rejected under 35 U.S.C. 101 because it is directed to non-statutory subject matter and thus do not fall within at least one of the four categories of patent eligible subject matter.
4. As to claims 15–20, they are directed to a “computer readable storage medium comprising a set of instructions.”
Under current Office examination procedure, and absent clear definition or exclusion by the Applicant to the contrary, the broadest reasonable interpretation of a computer readable storage medium can encompass non-statutory, transitory forms of signal transmission, such as a propagating electrical or electromagnetic signal per se. See MPEP § 2106.03, Eligibility Step 1: The Four Categories of Statutory Subject Matter.
See specifically, PTAB precedential decision Ex parte Mewherter (Appeal 2012-007692), affirming the Examiner’s findings “that, because Appellants’ Specification fails to limit expressly the term ‘machine readable storage medium’ to exclude signals, carrier waves, etc., the term encompasses transitory propagating signals” (Mewherter, pg. 5); and holding that “those of ordinary skill in the art would understand the claim term ‘machine-readable storage medium’ would include signals per se. Further, where, as here, the broadest reasonable interpretations of all the claims each covers a signal per se, the claims must be rejected under 35 U.S.C. § 101 as covering non-statutory subject matter” (Mewherter, pg. 13).
Accordingly, the claimed “computer readable storage medium” is directed to non-statutory subject matter.
Applicant is advised to amend this portion of the claim to recite a “non-transitory computer readable storage medium” to overcome the 101 rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
5. Claims 1–20 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
6. As to independent claims 1, 9, and 15, they recite the limitation of “bypasses the IPU to enable direct memory access (DMA) from the host system to the physical storage device based on the first transaction identifier.” However, this limitation is not supported by the specification as the specification fails to disclose entirely (the feature of) providing “direct memory access (DMA) from the host system to the physical storage device based on the first transaction identifier.”
In page 10 of Applicant’s specification, the specification merely sets forth that “the requested application data to be retrieved from the host local memory 120 and routed to a location in one of the physical SSDs” without describing enabling or performing direct memory access (DMA) from the host system to the physical storage device.
Therefore, claims 1–20 contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed inventions.
Claim Interpretation Under 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
7. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
8. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
a. “an infrastructure processing unit (IPU)” and
b. “a switch,”
recited in independent claim 1, and
c. “an infrastructure processing unit (IPU)” and
d. “a multi-root (MR) switch,”
recited in independent claim 9,
configured or capable of performing one or more claimed functions.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
9. Claim limitations:
a. “an infrastructure processing unit (IPU),”
b. “a switch,”
c. “an infrastructure processing unit (IPU),” and
d. “a multi-root (MR) switch,”
recited in independent claims 1 and 9, invoke 35 U.S.C. 112(f).
However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. In this instance, and as filed, the disclosure is either devoid of any structure that performs the function in the claims, or (to the extent that a structure is sufficiently disclosed) that the structure described in the specification does not perform the entire function in the claim.
10. Therefore, claims 1–14 are indefinite and rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Examiner’s Remarks
11. Examiner refers to and explicitly cites particular pages, sections, figures, paragraphs or columns and lines in the references as applied to Applicant’s claims to the extent practicable to streamline prosecution.
Although the cited portions of the references are representative of the best teachings in the art and are applied to meet the specific limitations of the claims, other uncited but related teachings of the references may be equally applicable as well. It is respectfully requested that, in preparing responses to the rejections, the Applicant fully considers not only the cited portions of the references, but also the references in their entirety, as potentially teaching, suggesting or rendering obvious all or one or more aspects of the claimed invention.
Abbreviations
12. Where appropriate, the following abbreviations will be used when referencing Applicant’s submissions and specific teachings of the reference(s):
i. figure / figures: Fig. / Figs.
ii. column / columns: Col. / Cols.
iii. page / pages: p. / pp.
References Cited
13. (A) Makhervaks et al., US 2021/0349841 A1 (“Makhervaks”).
(B) Naven et al., US 2014/0376548 A1 (“Naven”).
(C) Thomas et al., US 10,360,155 B1 (“Thomas”).
Makhervaks, Naven, and Thomas were cited in the previous Office action.
Notice re prior art available under both pre-AIA and AIA
14. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A.
15. Claims 1–2, 5, 9–10, 12, 15–16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Makhervaks.
See “References Cited” section, above, for full citations of references.
16. Regarding claim 1, (A) Makhervaks teaches/suggests the invention substantially as claimed, including:
“A semiconductor apparatus comprising:
an infrastructure processing unit (IPU) to interface with a host system with a virtual function to provide a control path for application data from the host system to a physical storage device, by remapping a transaction identifier field in a data transfer message between a first transaction identifier associated with the virtual function and a second transaction identifier associated with the physical storage device”
(¶ 2: server system may further comprise a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device may be configured to virtualize hardware resources of the plurality of SSD devices and present a virtual SSD device to the host software of the one or more compute nodes;
¶ 25: The LNV device 108 may be configured to manage read/write requests for the locally attached NVMe devices;
¶ 30: The LNV device 302 has NVMe functions or virtual functions 318 and LNV function 320 that are PCIe functions;
Fig. 11 and ¶¶ 76–78: FIG. 11 illustrates an example of RID and tag remapping performed by the NT switch …
As illustrated, using a RID and TAG remapping table 1012, the NT switch 1110 may be configured to remap the SSD RID used in the request to the LNV RID. Specifically, the NT switch 1110 will remap the RID to the LNV function RID for the PCIe domain of the target host 1102 of that request. For example, if the first SSD device is making a request to host1, then the NT switch 1110 may be configured to remap the SSD1 RID in the request to the LNV F1 RID to route the request to the host1;
Fig. 12 and ¶¶ 79–80: FIG. 12 illustrates an example of mapping virtual functions (VF) to physical functions (PF) for the LNV device … In this example, the NT switch 1202 may be configured to map those VFs 1206 to PFs 1208 of the NT switch 1202, and to present those VFs 1206 as the PFs 1208 …
In another example, the NT switch 1202 may be further configured to present a subset of the VFs of the LNV device 1200 as VFs 1210 associated with one of the PFs 1208 represented by the NT switch 1202;
¶ 121: methods and processes may be implemented as a computer-application program or service,
¶ 122: Computing system 2000 may take the form of one or more personal computers, server computers, tablet computers, home-entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smart phone), and/or other computing devices, and wearable computing devices such as smart wristwatches and head mounted augmented reality devices
the Examiner notes: these are examples of “applications”); and
“a switch to route the data transfer message to the physical storage device …”
(¶ 2: server system may further comprise a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device may be configured to virtualize hardware resources of the plurality of SSD devices and present a virtual SSD device to the host software of the one or more compute nodes;
¶ 25: The LNV device 108 may be configured to manage read/write requests for the locally attached NVMe devices;
¶ 26: NVMe commands (Admin and Data In/Out) from each VM 102 are processed by the LNV 108, which in turn will generate new NVMe commands for the locally attached NVMe devices 110
Fig. 11 and ¶¶ 76–78: FIG. 11 illustrates an example of RID and tag remapping performed by the NT switch …
the NT switch 1110 may be configured to remap the SSD1 RID in the request to the LNV F1 RID to route the request to the host1);
“wherein the physical storage device is to be managed by the IPU”
(¶ 25: The LNV device 200 is configured to generate NVMe commands 210 and place those commands into the submission queues (SQ) of respective SSDs 202 ( e.g. NVMe devices) that are allocated to the LNV device 200 and offloaded onto hardware 208).
Makhervaks do not expressly teach “a switch … to provide a data path that bypasses the IPU to enable direct memory access (DMA) from the host system to the physical storage device based on the first transaction identifier.”
However Makhervaks teaches in one embodiment the implementation of “an input-output memory management unit (IOMMU) 822, that connects a direct-memory-access-capable (DMA-capable) I/O bus to the main memory. The IOMMU 822 translates processor-visible virtual addresses to physical addresses, and maps device-visible virtual addresses to physical addresses. Furthermore, the IOMMU 822 is configured to allow the LNV device 812 to access VM GPA space in VM memory 806 using the VF RID of the LNV device 812 …
LNV device 812 is configured to perform functions to let the GPA 808 referenced by the SQE 816 and PRP 818 translated into corresponding HPAs 810, which would allow the SSD devices 824 to directly access the data buffers 820 of VM address space in the host memory of compute node 800”
(Fig. 8 and ¶¶ 65 and 66;
See also ¶ 99: At 1608, the method 1600 may include directly accessing data buffers of the host memory device of each compute node using the plurality of SSD devices. The SSD device itself may initiate a PCie transaction to access the data buffers in the host memory, as shown in FIG. 7. By accessing the data buffers directly, input/output flow to the SSD device is not limited by the uplink of the LNV device; and
¶ 134: The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node).
Accordingly, it is inherent in or would have been obvious to a person of ordinary skill in the art in view of Makhervaks’ teachings that Makhervaks’ switch provides “a data path that bypasses the IPU to enable direct memory access (DMA) from the host system to the physical storage device based on the first transaction identifier” i.e. where the SSD devices 824 can directly access the data buffers 820 of VM address space in the host memory of compute node.
17. Regarding claim 2, Makhervaks teaches or suggests:
“wherein the data transfer message is a WRITE request issued by the physical storage device, and wherein remapping the transaction identifier field in the data transfer message:
(¶ 76: When one of the SSD devices 1108 initiates a read/write request to one of the hosts 1102, that request includes a RID of that SSD device);
comprises substituting, in the write request, the first transaction identifier associated with the virtual function in place of the second transaction identifier associated with the physical storage device”
(Fig. 11 and ¶¶ 76–78: FIG. 11 illustrates an example of RID and tag remapping performed by the NT switch …
As illustrated, using a RID and TAG remapping table 1012, the NT switch 1110 may be configured to remap the SSD RID used in the request to the LNV RID. Specifically, the NT switch 1110 will remap the RID to the LNV function RID for the PCIe domain of the target host 1102 of that request. For example, if the first SSD device is making a request to host1, then the NT switch 1110 may be configured to remap the SSD1 RID in the request to the LNV F1 RID to route the request to the host1).
18. Regarding claim 5, Makhervaks teaches or suggests:
“maintain a remapping table to hold the first transaction identifier and the second transaction identifier”
(¶ 78: the NT switch 1110 may further keep track of tag remapping using the RID and tag remapping table 1012;
¶ 39: Using internal mapping tables, the LNV device 302 may then determine how the NVMe
commands from both VMs should be mapped to the SSD device 304).
19. Regarding claims 9–10 and 12, they are the corresponding system claims reciting similar limitations of commensurate scope as the apparatus of claims 1–2 and 5, respectively. Therefore, they are rejected on the same basis as claims 1–2 and 5 above, including the following rationale:
Makhervaks teaches or suggests: “a host system comprising a host processor coupled to a host memory;
an infrastructure processing unit (IPU); (LNV device)
a plurality of storage devices; and
a multi-root (MR) switch coupled to the host system, the IPU and the plurality of storage devices” (NT switch for multiple hosts/domains)
(Fig 9 and ¶ 70: FIG. 9 illustrates a multi-host configuration 900 that shares a same set of LNV device 902 and SSD devices 904 among a plurality of compute nodes for a plurality of hosts 906. Each host may include separate host memory devices 912 … NT switch 908 may be configured to create separate PCI domains for HOST1, HOST2, HOST3, HOST4;
Figs. 5 and 6 and ¶ 47: each compute node 500 in the node cluster 502 includes at least one processor 508 communicatively coupled).
20. Regarding claims 15–16 and 18, they are the corresponding computer program product claims reciting similar limitations of commensurate scope as the apparatus of claims 1–2 and 5, respectively. Therefore, they are rejected on the same basis as claims 1–2 and 5 above.
B.
21. Claims 3–4, 6–7, 11, 13, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Makhervaks, as applied to claims 1, 9, and 15 above, and further in view (B) Naven.
22. Regarding claim 3, Makhervaks teaches or suggests:
“… a data completion issued by the host system, and wherein to perform remapping the transaction identifier field in the data transfer message:
(¶ 26: execute the request, and report completion of the request to the CQ 114 to inform the standard NVMe storage stack 104 of the VM 102 that the request has been completed;
¶ 78: NT switch 1110 may further keep track of tag remapping using the RID and tag remapping table 1012. For example, the NT switch 1012 may remap tag0 for a request from the first SSD device to Tag1, remap tag0 for a request from the second SSD device to tag2, and remap tag0 for a request from the third SSD device to tag3. Completion of the read request will also include a corresponding tag that was sent to the host for the request, and the NT switch 1110 may remap those tags back to the local tag of the respective SSD device 1108 using the table 1012);
comprises substituting, in the data completion, the second transaction identifier associated with the physical storage device in place of the first transaction identifier associated with the virtual function”
(¶ 26: execute the request, and report completion of the request to the CQ 114 to inform the standard NVMe storage stack 104 of the VM 102 that the request has been completed;
¶ 78: the NT switch 1110 may remap those tags back to the local tag of the respective SSD device 1108 using the table 1012).
Makhervaks do not expressly teach that the data transfer message is data completion (message).
(but see ¶ 26: “execute the request, and report completion of the request” which highly suggests this feature).
(B) Naven however teaches or suggests:
“the data transfer message is data completion (message)”
(¶ 79: FIG. 8 schematically illustrates the structure of a standard memory write ( or memory read) data packet header 40 ….A PCIe transaction may be made up of a request data packet and one or more corresponding completion data packets;
¶¶ 105 and 106: performing the memory read operation specified in the memory read request data packet 100) and generates a memory read completion data packet 102 …. The memory read completion data packet 102 is then transmitted to the server 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (B) Naven with those of (A) Makhervaks to generate and return a data completion packet in response to receiving and performing a read request. The motivation or advantage to do so is to complete the PCIe transaction/protocol.
23. Regarding claim 4, Makhervaks and Naven teach or suggest:
“substitute, in a read request to be issued by the physical storage device, the first transaction identifier associated with the virtual function in place of the second transaction identifier associated with the physical storage device; and
wherein the switch is to route, via the switch, the read request to the host system”
(Makhervaks, ¶ 76: When one of the SSD devices 1108 initiates a read/write request to one of the hosts 1102, that request includes a RID of that SSD device;
Fig. 11 and ¶¶ 76–78: FIG. 11 illustrates an example of RID and tag remapping performed by the NT switch …
As illustrated, using a RID and TAG remapping table 1012, the NT switch 1110 may be configured to remap the SSD RID used in the request to the LNV RID. Specifically, the NT switch 1110 will remap the RID to the LNV function RID for the PCIe domain of the target host 1102 of that request. For example, if the first SSD device is making a request to host1, then the NT switch 1110 may be configured to remap the SSD1 RID in the request to the LNV F1 RID to route the request to the host1);
“wherein the data completion is to be issued by the host system responsive to the read
Request”
(Makhervaks — ¶ 26: execute the request, and report completion of the request to the CQ 114 to inform the standard NVMe storage stack 104 of the VM 102 that the request has been completed;
¶ 78: NT switch 1110 may further keep track of tag remapping using the RID and tag remapping table 1012. For example, the NT switch 1012 may remap tag0 for a request from the first SSD device to Tag1, remap tag0 for a request from the second SSD device to tag2, and remap tag0 for a request from the third SSD device to tag3. Completion of the read request will also include a corresponding tag that was sent to the host for the request, and the NT switch 1110 may remap those tags back to the local tag of the respective SSD device 1108 using the table 1012;
Naven — ¶ 79: FIG. 8 schematically illustrates the structure of a standard memory write ( or memory read) data packet header 40 ….A PCIe transaction may be made up of a request data packet and one or more corresponding completion data packets;
¶¶ 105 and 106: performing the memory read operation specified in the memory read request data packet 100) and generates a memory read completion data packet 102 …. The memory read completion data packet 102 is then transmitted to the server 1).
24. Regarding claim 6, Makhervaks and Naven teach or suggest:
“wherein the first transaction identifier includes a virtual requester identifier associated with the virtual function, wherein the second transaction identifier includes a requester identifier for the physical storage device, and wherein the transaction identifier field includes a requester identifier field”
(Makhervaks — Fig. 11 and ¶¶ 76–78: FIG. 11 illustrates an example of RID and tag remapping performed by the NT switch …
As illustrated, using a RID and TAG remapping table 1012, the NT switch 1110 may be configured to remap the SSD RID used in the request to the LNV RID. Specifically, the NT switch 1110 will remap the RID to the LNV function RID for the PCIe domain of the target host 1102 of that request. For example, if the first SSD device is making a request to host1, then the NT switch 1110 may be configured to remap the SSD1 RID in the request to the LNV F1 RID to route the request to the host1;
¶ 78: NT switch 1110 may further keep track of tag remapping using the RID and tag remapping table 1012. For example, the NT switch 1012 may remap tag0 for a request from the first SSD device to Tag1, remap tag0 for a request from the second SSD device to tag2, and remap tag0 for a request from the third SSD device to tag3;
Fig. 12 and ¶¶ 79–80: FIG. 12 illustrates an example of mapping virtual functions (VF) to physical functions (PF) for the LNV device … In this example, the NT switch 1202 may be configured to map those VFs 1206 to PFs 1208 of the NT switch 1202, and to present those VFs 1206 as the PFs 1208 …
In another example, the NT switch 1202 may be further configured to present a subset of the VFs of the LNV device 1200 as VFs 1210 associated with one of the PFs 1208 represented by the NT switch 1202;
Naven — Fig. 8 and ¶ 79: FIG. 8 schematically illustrates the structure of a standard memory write ( or memory read) data packet header 40 …. the header 40 comprises a sixteen bit requester ID field 40a indicating the device that issued the data packet to which header 40a belongs. As described above, the requester ID field of a PCIe data packet comprises a function, device and bus number. The header 40 further comprises an eight bit tag field 40b. A PCIe transaction may be made up of a request data packet and one or more corresponding completion data packets. Each request data packet is associated with a value which is stored in the tag field 40b).
25. Regarding claim 7, Makhervaks and Naven teach or suggest:
“wherein the first transaction identifier further includes a first tag, wherein the second transaction identifier further includes a second tag, and wherein the transaction identifier field further includes a TAG FIELD”
(Makhervaks — Fig. 11 and ¶¶ 76–78; and Fig. 12 and ¶¶ 79–80, as applied in rejecting claim 6 above;
Naven — Fig. 8 and ¶ 79: as applied in rejecting claim 6 above).
26. Regarding claims 11 and 13, they are the corresponding system claims reciting similar limitations of commensurate scope as the apparatus of claims 4 and 7, respectively. Therefore, they are rejected on the same basis as claims 4 and 7 above.
27. Regarding claims 17 and 19, they are the corresponding computer program product claims reciting similar limitations of commensurate scope as the apparatus of claims 4 and 7, respectively. Therefore, they are rejected on the same basis as claims 4 and 7 above.
C.
28. Claims 8, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over (A) Makhervaks, as applied to claims 1, 9, and 15 above, and further in view (C) Thomas.
29. Regarding claim 8, Makhervaks teaches or suggests:
“transferring stored data, via the switch … while bypassing temporary storage of the stored data in the memory local to the IPU”
(see ¶ 2, ¶ 25, and ¶ 30, as applied in rejecting claim 1 above;
Fig. 11 and ¶¶ 76–78: FIG. 11 illustrates an example of RID and tag remapping performed by the NT switch …
As illustrated, using a RID and TAG remapping table 1012, the NT switch 1110 may be configured to remap the SSD RID used in the request to the LNV RID. Specifically, the NT switch 1110 will remap the RID to the LNV function RID for the PCIe domain of the target host 1102 of that request. For example, if the first SSD device is making a request to host1, then the NT switch 1110 may be configured to remap the SSD1 RID in the request to the LNV F1 RID to route the request to the host1;
Fig. 12 and ¶¶ 79–80: FIG. 12 illustrates an example of mapping virtual functions (VF) to physical functions (PF) for the LNV device … In this example, the NT switch 1202 may be configured to map those VFs 1206 to PFs 1208 of the NT switch 1202, and to present those VFs 1206 as the PFs 1208 …
In another example, the NT switch 1202 may be further configured to present a subset of the VFs of the LNV device 1200 as VFs 1210 associated with one of the PFs 1208 represented by the NT switch 1202;
Fig. 14 and ¶ 89: The LNV device 1412 may generate backend NVMe commands and place those commands as SQEs 1422 in the backend NVME SQ 1424 of backend memory 1426;
Fig. 1 and ¶ 26: standard NVMe interface defines a set of submission queues (SQ) 112 and a set of completion queues (CQ) 114. New disk read/write requests for the standard NVMe device 106 may be submitted by the standard NVMe storage stack of a VM 102 to a SQ 112. The standard NVMe device 106, whose functions are performed by the LNV 108 and the virtualized locally attached NVMe devices 110, will perform read the request in the SQ 112, execute the request, and report completion of the request to the CQ 114 to inform the standard NVMe storage stack 104 of the VM 102 that the request has been completed).
Makhervaks do not teach “to perform data compaction by transferring stored data … between the physical storage device and another physical storage device.”
(C) Thomas, in the context of Makhervaks’ teachings, however teaches or suggests:
“to perform data compaction by transferring stored data … between the physical storage device and another physical storage device”
(Col. 7, lines 1–5: allows compaction of data as the data is moved from the fast tier to the slow tier. This reduces write amplification (write delay) in the slow tier layer;
Col. 9, lines 33–38: Typically, the slow tier 204 is a larger and less expensive memory (e.g., implemented using TLC technology). For example, the slow tier 204 may be capable of storing more data in one of its memory cells than the fast tier 206 … data from a fast tier block 216 is copied to a slow tier block 218 and data from a fast tier block 220 is copied to a slow tier block 222 …. Thus, data may be compacted as it is copied into the slow tier 204;
Col. 10, lines 65–67: the copy operation involves compaction, data from multiple SLC blocks (e.g., the fast tier blocks 216 and 220) could be written to a single TLC block).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (C) Thomas with those of (A) Makhervaks to compact data when relocating data between different SSD storage devices (tiers). The motivation or advantage to do so is to optimize the spaces and usages of different storage tiers (types) and to improve data/storage access performances.
30. Regarding claim 14, it is the corresponding system claim reciting similar limitations of commensurate scope as the apparatus of claim 8. Therefore, it is rejected on the same basis as claim 8 above.
31. Regarding claim 20, it is the corresponding computer program product claim reciting similar limitations of commensurate scope as the apparatus of claim 8. Therefore, it is rejected on the same basis as claim 8 above.
Response to Arguments
32. Applicant’s arguments with respect to the claims have been considered but are moot because the arguments do not apply to any of the newly applied teachings or references being used in the current rejection.
In the Remarks, the Applicant also contends the following:
a. Regarding the 101 rejection, Applicant's claims are expressly directed to a “computer readable storage medium,” and anyone of skill in the art will understand that a signal is not a transitory signal if it is stored on a medium. Accordingly, the rejection is improper.
The Examiner disagrees.
As to (a), as applied and noted in the rejection, PTAB precedential decision Ex parte Mewherter (Appeal 2012-007692), specifically affirms that case’s Examiner’s findings “that, because Appellants’ Specification fails to limit expressly the term ‘machine readable storage medium’ to exclude signals, carrier waves, etc., the term encompasses transitory propagating signals.”
Accordingly, the Board held that “those of ordinary skill in the art would understand the claim term ‘machine-readable storage medium’ would include signals per se.” And if “the broadest reasonable interpretations of all the claims each covers a signal per se, the claims must be rejected under 35 U.S.C. § 101 as covering non-statutory subject matter.” See Mewherter, pages 5 and 13.
In this instant application, Applicant’s Specification does not expressly limit the term “computer readable storage medium” as excluding signals, carrier waves, etc.; therefore the Examiner similarly finds that this term “computer readable storage medium” encompasses transitory propagating signals.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Saghi et al., US 2014/0281106 A1, teaching direct routing between address
spaces through a nontransparent PCIe bridge.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN C WU whose telephone number is (571)270-5906. The examiner can normally be reached Monday through Friday, 8:30 A.M. to 5:00 P.M..
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/BENJAMIN C WU/Primary Examiner, Art Unit 2195
September 14, 2026
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