DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 9-19, 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the battery pack" in line 7 and in line 10. There is insufficient antecedent basis for this limitation in the claim. It is unclear as to which of the plurality of battery packs said limitation refers to.
Claim 1 recites the limitation "the discharge capabilities of the battery group" in line 14. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim. It is unclear as to which of the plurality of battery packs said limitation refers to.
Claim 2 recites the limitation "the discharge capabilities of the battery group". There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation “the system”. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation “the lowest discharge capability of the plurality of battery packs”. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the battery pack" in line 7 and in line 10. There is insufficient antecedent basis for this limitation in the claim. It is unclear as to which of the plurality of battery packs said limitation refers to.
Claim 6 recites the limitation “the discharge voltage”. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the different discharge capabilities of the battery group" in lines 13-14. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation “the lowest discharge” in line 17. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “the lowest discharge capability of the plurality of battery packs”. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation “the lowest discharge capability of the plurality of battery packs”. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “the lowest discharge capability of the plurality of battery pack”. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation “the power load of the computing system”. There is insufficient antecedent basis for this limitation in the claim. It is unclear as to which of the power load of the computing system in line 7 or in line 14 said limitation refers to.
Claim 16 recites the limitation "the processor". There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Claim 22 recites the limitation "the battery pack". There is insufficient antecedent basis for this limitation in the claim.
Further, dependent claims 2-6, 9-19, 21-22 are rendered indefinite due to their dependency on any of the indefinite claims above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-14, 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (US 2017/0310130A1).
Regarding claim 1, Yoshida discloses a computing system (see Title, Abstract), comprising:
a battery group comprising a plurality of battery packs connected in at least one series connection (battery pack 10 including battery cells [0025]); and
at least one processor coupled to the battery group (processor unit 606 [0136]), wherein each of the battery packs comprises control circuitry configured to detect a system interrupt of the computing system, and in response to the system interrupt, monitor a voltage of the battery pack during a discharge to a power load comprising the at least one processor and determine a discharge capability of the battery pack (measurement unit 200 that measures voltage and current of the battery cells, battery control unit 400 calculates an estimation value of the residual capacity of the present battery cell 100 by integrating a current; battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200; alarm voltage value [0026]);
wherein in response to determining that the power load exceeds a lowest discharge capability of the discharge capabilities of the battery group, the at least one
processor is configured to reduce a respective clock frequency to reduce the power load
below the lowest discharge capability (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]; load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 2, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses for each of the battery packs, in response to the system interrupt, the control circuitry is configured to monitor the voltage of the battery pack packs during charging of the battery group and determine charging capability of the battery pack (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]); and in response to determining that the power load exceeds a lowest discharge capability of the discharge capabilities of the battery group, the at least one processor is configured to reduce the a charging level of the battery group below a lowest charging capability of charging capabilities of the battery packs (load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 3, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the processor is configured to: detect a change of use profile for the plurality of battery packs in a first configuration; in response to the detected change of use profile, reconfigure the plurality of battery packs into a second configuration ([0043]-[0045]); determine an updated lowest discharge capability for the plurality of battery packs in the second configuration (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]); and reduce the power load of the at least one system component below the updated lowest discharge capability for the plurality of battery packs in the second configuration (load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 4, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the plurality of battery packs of the battery group are mounted in a multi-battery carrier, and wherein the multi-battery carrier is mounted in a battery bay of the system (mounted [0141]).
Regarding claim 5, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the multi-battery carrier comprises a carrier power rail to connect the plurality of battery packs in the at least one series connection (series [0026]), and wherein the multi-battery carrier further comprises carrier control circuitry to determine the lowest discharge capability of the plurality of battery packs (battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200 [0026]).
Regarding claim 6, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses for each of the battery packs, the control circuitry comprises a protection circuit configured to: determine whether the voltage of the battery pack is lower than a minimum discharge voltage; and in response to a determination that the discharge voltage of the battery pack is lower than the minimum discharge voltage, shut down the battery pack (A reference voltage value V1 serving as a trigger of a process of correcting the estimation value of the residual capacity and an alarm voltage value Va which is a voltage higher than the reference voltage value are set as the voltages of the battery cells 100. In addition, the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition. [0026]; shut down [0045]).
Regarding claim 21, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses in response to the determining that the power load exceeds the lowest discharge capability, the at least one processor is configured to reduce the clock frequency of a turbo mode of the at least one processor (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]; load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 9, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses a computing device (see Title, Abstract, computer [0045], comprising:
a battery group comprising a plurality of battery packs connected in at least one series connection (battery pack 10 including battery cells [0025]);
at least one processor (processor unit 606 [0136]);
a memory (memory [0041]); and
a machine-readable storage storing instructions (storage [0041]), wherein the instructions are executable by the at least one processor to:
monitor a voltage of each battery pack in the battery group during a discharge to a power load comprising the at least one processor (measurement unit 200 that measures voltage and current of the battery cells [0026]);
determine different discharge capabilities of different battery packs in the battery
group (battery control unit 400 calculates an estimation value of the residual capacity of the present battery cell 100 by integrating a current [0026]);
determine a lowest discharge capability of the different discharge capabilities of the battery group (battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200 [0026]); and
in response to a determination that the power load exceeds the lowest discharge
capability, reduce the power load to less than the lowest discharge, wherein the reducing the power load comprises reducing a clock frequency of a turbo mode of the at least one processor (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]; load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 10, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the instructions are executable by the at least one processor to: during charging of the battery group, monitor a voltage of each battery pack in the battery group, and determine different charging capabilities of the different battery packs; and in response to a determination that a charging level of the battery group exceeds a lowest charging capability of the different charging capabilities reduce the charging level of the battery group to less than the lowest charging capability (battery control unit 400 calculates an estimation value of the residual capacity of the present battery cell 100 by integrating a current; battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200; the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]; load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 11, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the instructions are executable by the at least one processor to: detect a change of use profile for the plurality of battery packs in a first configuration; in response to the detected change of use profile, reconfigure the plurality of battery packs into a second configuration ([0043]-[0045]); determine a lowest discharge capability for the plurality of battery packs in the second configuration (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]); and reduce the power load to less than the lowest discharge capability for the plurality of battery packs in the second configuration (load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 12, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the plurality of battery packs of the battery group are mounted in a multi-battery carrier, and wherein the multi-battery carrier is mounted in a battery bay (mounted [0141]).
Regarding claim 13, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the multi-battery carrier comprises a carrier power rail to connect the plurality of battery packs in the at least one series connection (series [0026]), and the at least one processor comprises carrier control circuitry of the multi-battery carrier to determine the lowest discharge capability of the plurality of battery packs (battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200 [0026]).
Regarding claim 14, Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses each of the different battery packs comprises: module control circuitry to determine whether the discharge voltage of the battery pack is lower than a predefined minimum discharge voltage; and a protection circuit configured to, in response to a determination that the discharge voltage of the battery pack is lower than the predefined minimum discharge voltage, shut down the battery pack (A reference voltage value V1 serving as a trigger of a process of correcting the estimation value of the residual capacity and an alarm voltage value Va which is a voltage higher than the reference voltage value are set as the voltages of the battery cells 100. In addition, the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition. [0026]; shut down [0045]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15-19, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 2017/0310130A1), as applied to claims 1-6, 9-14, 21 above, in view of Matsumura et al. (US 2020/0412153A1).
Regarding claim 15, Yoshida discloses all of the claim limitations as set forth above. However, Yoshida does not further disclose to determine the different discharge capabilities, the instructions are executable by the at least one processor to: determine an impedance of each battery pack; and determine the discharge capability of each battery pack based on a difference between the monitored voltage during the discharge and a minimum discharge voltage of the battery pack, divided by the impedance of the battery pack.
Matsumura discloses, to determine degrade battery cells, a battery manager monitoring a voltage change dV (dV=dl*R) during discharge and/or charge, where dl is current change and R is impedance of the battery (R.sub.bat) and impedance of the FET (R.sub.FET). Since dl is monitored by the battery management 1108, and impedance of the FET (R.sub.FET) is known, battery impedance (R.sub.bat) can be calculated by R.sub.bat=dV/dl−R.sub.FET; then the FET of the next cell is turned on and all other FETs are turned off, and the impedance of the next cell is calculated in the same manner; this process is then repeated for all of the battery cells to determine which battery cells (if any) should be electrically removed (and/or electrically separated) from the battery pack by turning off the corresponding FET ([0077]).
Yoshida and Matsumura are analogous art because they are concerned with the same field of endeavor, namely monitoring battery health.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine degrade in battery cells using the method disclosed in Matsumura to improve battery efficiency.
Regarding claim 16, Yoshida discloses a multi-battery carrier (see Title, Abstract; mounted [0141]), comprising:
an enclosure to be inserted into a battery bay of a computing system (computer [0045]);
a carrier power rail to be electrically coupled to a plurality of battery packs mounted in the multi-battery carrier (series [0026]); and
control circuitry to:
monitor a voltage of each battery pack in the plurality of battery packs during a
discharge to a power load of the computing system, wherein the power load comprises
a processor (measurement unit 200 that measures voltage and current of the battery cells [0026]);
determine a discharge capability of each battery pack of the plurality of battery
packs (battery control unit 400 calculates an estimation value of the residual capacity of the present battery cell 100 by integrating a current [0026]);
determine whether a power load of the computing system exceeds a lowest
discharge capability of the plurality of battery packs (battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200 [0026]); and
in response to a determination that the power load of the computing system
exceeds the lowest discharge capability, reduce the power load of the computing system below the lowest discharge capability, wherein the reducing the power load comprises reducing a clock frequency of the processor (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]; load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
However, Yoshida does not further disclose determine a discharge capability of each battery pack of the plurality of battery packs based on a difference between the monitored voltage during the discharge and a minimum discharge voltage of the battery pack, divided by an impedance of the battery pack, wherein the impedance is different for different battery packs of the plurality of battery packs.
Matsumura discloses, to determine degrade battery cells, a battery manager monitoring a voltage change dV (dV=dl*R) during discharge and/or charge, where dl is current change and R is impedance of the battery (R.sub.bat) and impedance of the FET (R.sub.FET). Since dl is monitored by the battery management 1108, and impedance of the FET (R.sub.FET) is known, battery impedance (R.sub.bat) can be calculated by R.sub.bat=dV/dl−R.sub.FET; then the FET of the next cell is turned on and all other FETs are turned off, and the impedance of the next cell is calculated in the same manner; this process is then repeated for all of the battery cells to determine which battery cells (if any) should be electrically removed (and/or electrically separated) from the battery pack by turning off the corresponding FET ([0077]).
Yoshida and Matsumura are analogous art because they are concerned with the same field of endeavor, namely monitoring battery health.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine degrade in battery cells using the method disclosed in Matsumura to improve battery efficiency.
Regarding claim 17, modified Yoshida discloses all of the claim limitations as set forth above. Modified Yoshida further discloses the control circuitry is configured to:
monitor a voltage of each battery pack of the plurality of battery packs during
charging of the plurality of battery packs (Yoshida: measurement unit 200 that measures voltage and current of the battery cells [0026]);
determine a charging capability of each battery pack of the plurality of battery packs based on a difference between the monitored voltage during the charging and a maximum charging voltage of the battery pack, divided by the impedance of the battery pack (Matsumura: [0077]);
determine whether a charging level of the multi-battery carrier exceeds a lowest charging capability of the plurality of battery packs (Yoshida: battery control unit 400 specifies a minimum capacity cell having the lowest voltage on the basis of the voltages measured by the measurement unit 200 [0026]); and
in response to a determination that the charging level of the multi-battery carrier exceeds the lowest charging capability of the plurality of battery packs, reduce the charging level of the multi-battery carrier below the lowest charging capability of the plurality of battery packs (Yoshida: the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]; load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 18, modified Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses the control circuitry is configured to: detect a change of use profile for the plurality of battery packs in a first configuration; in response to the detected change of use profile, reconfigure the plurality of battery packs into a second configuration ([0043]-[0045]); determine a lowest discharge capability for the plurality of battery packs in the second configuration (the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition [0026]); and reduce the power load of the computing system below the lowest discharge capability for the plurality of battery packs in the second configuration (load control unit 640 lowers clock frequency of the processor unit 606 [0136]).
Regarding claim 19, modified Yoshida discloses all of the claim limitations as set forth above. Yoshida further discloses each battery pack of the plurality of battery packs comprises a protection circuit to: determine whether a discharge voltage of the battery pack is lower than the minimum discharge voltage; and in response to a determination that the discharge voltage of the battery pack is lower than the minimum discharge voltage, shut down the battery pack (A reference voltage value V1 serving as a trigger of a process of correcting the estimation value of the residual capacity and an alarm voltage value Va which is a voltage higher than the reference voltage value are set as the voltages of the battery cells 100. In addition, the battery control unit 400 continues the discharge of all the battery cells 100, as it is, when an alarm condition in which the voltage of the minimum capacity cell is equal to or less than the alarm voltage value is not satisfied, and outputs a first signal when the voltage of the minimum capacity cell satisfies the alarm condition. [0026]; shut down [0045]).
Regarding claim 22, Yoshida discloses all of the claim limitations as set forth above. However, Yoshida does not further disclose for each of the battery packs, to determine the discharge capability of the battery pack, the control circuitry of the battery pack is configured to: determine an impedance of the battery pack; and determine the discharge capability of the battery pack based on a difference between the monitored voltage during the discharge and a minimum discharge voltage of the battery pack, divided by the impedance of the battery pack.
Matsumura discloses, to determine degrade battery cells, a battery manager monitoring a voltage change dV (dV=dl*R) during discharge and/or charge, where dl is current change and R is impedance of the battery (R.sub.bat) and impedance of the FET (R.sub.FET). Since dl is monitored by the battery management 1108, and impedance of the FET (R.sub.FET) is known, battery impedance (R.sub.bat) can be calculated by R.sub.bat=dV/dl−R.sub.FET; then the FET of the next cell is turned on and all other FETs are turned off, and the impedance of the next cell is calculated in the same manner; this process is then repeated for all of the battery cells to determine which battery cells (if any) should be electrically removed (and/or electrically separated) from the battery pack by turning off the corresponding FET ([0077]).
Yoshida and Matsumura are analogous art because they are concerned with the same field of endeavor, namely monitoring battery health.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine degrade in battery cells using the method disclosed in Matsumura to improve battery efficiency.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 9-19, 21-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES LEE whose telephone number is (571)270-7937. The examiner can normally be reached M-F: 9AM - 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, NICOLE BUIE-HATCHER can be reached at (571)270-3879. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/James Lee/Primary Examiner, Art Unit 1725 10/9/2026
