DETAILED ACTION
Claims 1 – 22 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thyagaturu et al (US 2022/0075655, hereinafter referred to as Thyagaturu).
As per claim 1, 9 and 17:
Taking claim 1 as exemplary: Thyagaturu discloses an apparatus to allocate processing unit usage comprising: interface circuitry to obtain instructions (Thyagaturu: Paragraph [0024], interconnects to communicate workloads between cores and accelerators); and processor circuitry including one or more of: at least one of a central processor unit, a graphics processor unit, or a digital signal processor, the at least one of the central processor unit, the graphics processor unit, or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus; a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and the plurality of the configurable interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations; the processor circuitry to perform at least one of the first operations, the second operations, or the third operations (Thyagaturu: Paragraph [0021], Cores implemented as CPU with GPUs FPGAs and other programmable logic) to instantiate: application scheduler circuitry to store data identifying at least one processing unit in communication with the processing circuitry and at least one class (Thyagaturu: Paragraph [0061] and figure 5 block 506 – 508, service request forwarded to acceleration user library, and paragraph [0039] – [0040], accelerator cost table to identify accelerator type and function, interpreting that as the claimed class); hardware predictor circuitry to predict a processing unit a workload is to be executed upon based on at least one capability (Thyagaturu: Paragraph [0061], selecting accelerator device for the requested function based on lowest core to accelerator cost, and paragraph [0026] cost is the term used to describe latency, latency being interpreted as the claimed capability); and scheduler engine circuitry to schedule which class of processing unit the workload to run on based on at least one of (i) hardware predictor circuitry or (ii) user priority parameters (Thyagaturu: Paragraph [0062] and figure 5 block 510, instance created for the application on the accelerator device based on the cost determined in step 508).
As per claim 2, 10 and 18:
Taking claim 2 as exemplary: Thyagaturu disclose the at least one capability is based of at least one of performance, efficiency, power, latency, model size, execution time, or throughput (Thyagaturu: Paragraph [0026], the cost described is equivalent to latency).
As per claim 3, 11 and 19:
Taking claim 3 as exemplary: Thyagaturu disclose in hardware feedback circuitry is to determine at least one performance capability of at least one of accelerator for at least one type of instruction or instruction mix in communication with the processing circuitry (Thyagaturu: Paragraph [0039] – [0040] and figure 3B, run time values in field 356 show performance of accelerator during runtime, interpreted as the claimed determining of a performance capability of the accelerator as it processes workload).
As per claim 4, 12 and 20:
Taking claim 4 as exemplary: Thyagaturu disclose hardware feedback circuitry is to determine at least one efficiency capability of at least one of accelerator for at least one type of instruction or instruction mix in communication with the processing circuitry (Thyagaturu: Paragraph [0032], run time values include latency and duration, considered to be efficiency capabilities).
As per claim 5 and 13:
Taking claim 5 as exemplary: Thyagaturu disclose application engine circuitry is to store the data in at least one of a register, an external memory, an internal memory, a thread context block maintained by a scheduler, or a memory table (Thyagaturu: Paragraph [0032] and figure 2a, memory for storing data).
As per claim 6 and 14:
Taking claim 6 as exemplary: Thyagaturu disclose application engine circuitry is to determine that the processing unit is available when the processing unit boots (Thyagaturu: Paragraph [0064], enumerating accelerators at platform boot).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8, 15-16 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Thyagaturu.
As per claim 7, 15 and 21:
Taking claim 7 as exemplary: Thyagaturu does not specifically disclose application engine circuitry is to detect when a new processing unit is available and add a new processing unit capability associated with the new processing unit to a hardware feedback memory table. However, it would have been obvious to one of ordinary skill in the art at the time of filing that when a new processing unit is made available, it should be added and made accessible just like the existing processing units.
As per claim 8, 16 and 22:
Taking claim 8 as exemplary: Thyagaturu does not specifically disclose application engine circuitry is to detect when an existing processing unit is removed and to remove an existing processing unit capability associated with the removed processing unit from a hardware feedback memory table. However, it would have been obvious to one of ordinary skill in the art at the time of filing that when an existing processing unit is removed, then it should not be listed with the still available processing units that can be used.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dune et al (US 9,984,044) discloses allocating work between processors based on predicted performance of the system. Imade (US 2015/0365343) teaches a scheduling apparatus between parallel computer systems based on priority and efficiency. Conte et al (US 2010/0268912) teaches thread mapping in multi-core processors.
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/ZACHARY K HUSON/Primary Examiner, Art Unit 2181