The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant’s amendments and remarks filed 5/28/26 are acknowledged. Claims 1 – 4, 6 – 9, and 12 – 21 have been amended. Claims 1 – 21 are pending.
Response to Amendments / Arguments
Applicant's arguments regarding the amended claims versus the previously-raised rejections under 35 USC 103(a) have been fully considered but they are moot in view of the new grounds of rejections, as necessitated by the Applicant’s amendments. During the 5/27/26 interview, the Examiner pointed to “Ramalingam et al (US 11,107,770 B1) which was cited as pertinent art and disclosed (Fig. 1) electronic dies 102, coupled by solder bumps 162 to an underlying secondary package substrate 150 (interposer), the latter coupled by solder bumps 110 to an underlying primary package substrate 108.” In combination with other prior art, Ramalingam teaches expressly or renders obvious the limitations recited by the amended claims, as detailed below.
Claim Objections
Claims 1 – 7 are objected to because of the following informalities:
Claim 1 recites the limitation “facing towards the semiconductor die” which refers to the first and second semiconductor dies and has a typographical error. For the purposes of this Action, the limitation is interpreted as “facing towards the first and second semiconductor dies”. Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 4, 8 – 12, and 16 – 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam et al (US 11,107,770 B1) in view of Mayukh et al (US 2023/0367087 A1), and further in view of Tang (US 2023/0178500 A1).
Regarding claim 1, Ramalingam discloses (Fig. 1; 3:33 – 5:37) an apparatus 100 (chip package), comprising (see annotated Fig. 1 below):
a primary package substrate 108 (“a package substrate 108” at 3:35 – 36) including a glass core 108 (its part 202, as shown in Fig. 2 and detailed below) and first contacts (at the upper ends of circuits/traces 136 which are directly coupled to solder bumps 110, as shown in annotated Fig. 1) along an outer (upper) surface 124 of the primary package substrate 108;
a photonic integrated circuit (PIC) 106 (“the third die 106 is an optical die” at 3:43; “The third die 106 includes solid state circuitry that is configured to receive optical signal, and convert the optical signals into electrical signals (e.g. current) … In one example, the circuitry of the third die 106 includes an optical modulator and a photo-detector” at 4:61 – 67) disposed/fixed within (a recess/notch of) the primary package substrate 108 adjacent a surface 140,142 of its core (as seen in Fig. 1; “The geometry of the package substrate 108 is configured to enable the different routings 152, 154, 156 as discussed above by accommodating the third die 106 in the notch 140 formed in the package substrate 108 in a manner that compensates for the differences in the diameter of the solder balls 116 and the diameter of the micro-bumps comprising the interconnects 114” at 7:51 – 57); and
a secondary package substrate 150 (interposer) supporting first and second semiconductor dies 104,102 on a first (top) side of the secondary package substrate 150, the first (top) side facing towards the first and second semiconductor dies 102,104 and away from the primary package substrate 108 (as seen in annotated Fig. 1), the secondary package substrate 150 including second contacts (at the lower ends of circuits/traces 154,156, as identified in annotated Fig. 1) on a second (bottom) side of the secondary package substrate 150, the second (bottom) side opposite the first (top) side, the first contacts (in 108) electrically coupled to the second contacts (in 150) with solder 110 (solder bumps, as seen in annotated Fig. 1), the secondary package substrate 150 including third contacts (at the upper ends of circuits/traces 152,154,156) on the first (top) side of the secondary package substrate 150, the first semiconductor die 104 including first bumps 166 and second bumps 164, the first bumps 166 connected to a first (right) subset of the third contacts (at the upper ends of the rightmost circuits/trances 154), the second bumps 164 connected to a second (left) subset of the third contacts (at the upper ends of circuits/trances 156), ones of the first (rightmost) subset of the third contacts electrically coupled to respective ones of the second contacts via internal interconnects 154 extending through the secondary package substrate 150, ones of the second (left) subset of the third contacts electrically coupled (via bumps 164 and U-shaped bridges 152) to the second semiconductor die 102 (as seen in annotated Fig. 1).
PNG
media_image1.png
519
975
media_image1.png
Greyscale
Annotated Fig. 1 of Ramalingam.
It is noted that Ramalingam teaches (Fig. 2) that “The package substrate 108 has a build-up layer 200 formed on a core substrate 202 … the core substrate 202 is generally fabricated from a rigid dielectric material. Suitable materials for used as the core substrate 202 include an inorganic materials, such as silicon, ceramic, glass reinforced plastic, or other suitable rigid dielectric material” (8:6 – 16, emphasis added) and, hence, considers that the primary package substrate 108 including a glass core 202.
Finally, Ramalingam teaches that the primary package substrate 108 has a recess/notch that results in an uneven outer surface 124 and different sizes of solder bumps 110 and 114. Ramalingam renders obvious that at least one of the PIC die 106 and the first semiconductor die 104 may have an uneven surface facing the other one of the PIC die 106 and the first semiconductor die 104 in which case the first bumps 166 would need to be larger than the second bumps 164 in order to bridge across a wider gap/separation between the PIC die 106 and the first semiconductor die 104, a matter of suitable/workable design choices/shapes that work equally well and do not change the principle of operation. It would be well within ordinary skill in the art to select proper sizes of solder bumps to accommodate different outer surfaces (flat and non-flat) of packaged dies. It has also been further held by the courts that a change in shape or configuration, without any criticality in operation of the device, is nothing more than one of numerous shapes that one of ordinary skill in the art will find obvious to provide based on the suitability for the intended final application. See In re Dailey, 149 USPQ 47 (CCPA 1976). In light of the foregoing analysis, Ramalingam teaches expressly or renders obvious all of the recited limitations.
As an aside and relevant comment, it is also noted that Ramalingam has essential structural features that are substantially similar/identical to those of the claimed apparatus, as evident from a direct side-by-side comparison of Figure 1 of Ramalingam with Fig. 1 of the instant application, Fig. 1 showing two vertically stacked package substrates 101,103 that are electrically coupled, the first package substrate 101 comprising an embedded PIC 130, the second package substrate comprising a mold compound 112 covering/encapsulating an semiconductor die 106,108 (para. 0024).
Regarding claim 8, Ramalingam (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited limitations, as detailed above for claim 1 (see annotated Fig. 1 provided above for claim 1), by a simple remapping of the first package substrate 108,106 to the second package substrate 150 to the second package substrate and the first package substrate 108,106 respectively. Specifically, Ramalingam an integrated circuit (IC) package 100, comprising:
a first package substrate 150 having a region of electrical routing 152,154,156, the electrical routing 152,154,156to electrically couple first contacts on a first (top) side of the region with respective second contacts on a second (bottom) side of the region, the second (bottom) side opposite the first (top) side;
a semiconductor die 104,102 including first and second bumps 162,164,166 on a (bottom) surface of the semiconductor die 104,102, the first bumps 166 connected (via solder bumps 114 and routings/traces 154 of the first package substrate/interposer 150) to first (right) ones of the first contacts on the first (top) side of the region, the second 162,164 bumps connected to second (left) ones of the first contacts on the first (top) side of the region, wherein the first bumps 166 can be larger than the second bumps 162,164 (as detailed above for claim 1);
a second package substrate 108,106 including third contacts, the third contacts attached to the second (bottom) side the first package substrate 150 contacts by solder interconnects 110,114 extending between the first package substrate 150 and the second package substrate 108,106 (as seen in annotated Fig. 1), the second package substrate 108,106 including a glass core 202 (as shown in Fig. 2 and detailed above for claim 1), the region of electrical routing between the semiconductor die 102,104 and the second package substrate 108,106 with the first (top) side facing towards the semiconductor die 102,104 and the second (bottom) side facing towards the second package substrate 108,106; and
a photonic integrated circuit (PIC) 106 within the second package substrate 108,106 adjacent the glass core 202 (as seen in Fig. 2), the semiconductor die 102,104 (its part 104) electrically coupled to the PIC 106 through the solder interconnects 114,166 (as seen in Fig. 1).
Regarding claim 16, Ramalingam (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited limitations, as detailed above for claim 1 (see annotated Fig. 1 provided above for claim 1). Specifically, Ramalingam considers a method of manufacturing an integrated circuit (IC) package, the method comprising:
providing a primary (lower) package substrate 108,106, the primary package substrate 108,106 including a glass core 202 (as shown in Fig. 2 and detailed above for claim 1);
positioning a photonic integrated circuit (PIC) 106 adjacent a (top) surface of the glass core 202 (as shown in Fig. 2);
providing first contacts on a first (upper) side of the glass core 202;
embedding an interconnect bridge 152 in a secondary package substrate 150 (interposer);
mounting a semiconductor die 104,102 supported by the secondary package substrate on a first (top) side of the secondary package substrate 150, the semiconductor die 104,102 include first and second bumps 162,164,166 to connect with respective second and third contacts on the first side of the secondary package substrate 150, the first bumps 166 larger than the second bumps 164,166 (as detailed above for claim 1), the second contacts electrically coupled with fourth contacts on a second (bottom) side of the secondary package substrate 150 including second contacts, the third contacts electrically coupled to fifth contacts on the first side of the secondary package substrate 150; and
soldering the first contacts to the fourth contacts with the semiconductor die 164,166 already mounted on the secondary package substrate 150.
The following is also noted:
The semiconductor package 100 in Fig. 1 comprises 3 main building blocks/parts, i.e., 102/104, 150 and 108/106 which can be mounted in a variety of suitable order of steps (and their permutations), e.g., 102/104 can first be mounted on 150 with the subassembly 102,104,150 subsequently mounted on 108,106, or 150 is first mounted on 108,106, and 104,102 are subsequently mounted on the subassembly 108,106,150.
The order of processing steps is non-binding unless expressly recited.
Regarding claims 2 and 17, Ramalingam renders obvious wherein the semiconductor die 102 is a logic circuit die (3:33 – 43), the logic circuit die electrically coupled (e.g., via the semiconductor die 104) to the PIC 106 via the coupled first and second contacts (as seen in Fig. 1; para. 0133 – 0135 of Amano).
Regarding claims 3 and 18, Ramalingam considers (4:23 – 47) that the second semiconductor die 104 is an electronic integrated circuit (EIC) driver and renders obvious that the EIC driver can be electrically coupled to the PIC 106 via the coupled first and second contacts (electrical connections through solder bumps 110,116, 166,114).
Regarding claims 4 and 19, Ramalingam considers (Fig. 1) that the apparatus 100 further includes an interconnect bridge 152 embedded in the secondary package substrate 150 (interposer), the logic circuit die 102 and the EIC driver (in the die 104) electrically coupled via the interconnect bridge 152.
Regarding claims 9 – 12, Ramalingam teaches expressly or renders obvious all of the recited limitations, as detailed above for claims 2 – 4.
Claims 5 – 7, 13 – 15, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ramalingam in view of Mayukh et al (US 2023/0367087 A1).
Regarding claims 5 and 20, Ramalingam discloses only embodiments (Fig. 1) wherein the PIC 106 is disposed on a top surface of a trench/notch of the primary package substrate 108 and Ramalingam does not teach that the PIC 106 can be embedded into the primary package substrate 108 and surrounded by it. However, Mayukh discloses (Figs. 2 and 3; para. 0030 – 0037) an apparatus, comprising:
a primary package substrate 305 including a glass core 310 (“the PIC 320 and/or EIC 325 may be embedded within the substrate 305. In some examples, the PIC is embedded inside a transmissive glass core 310 of the substrate 305, and configured to carry an optical signal to and/or from the PIC 320” at para. 0035, emphasis added);
a photonic integrated circuit (PIC) 310 embedded and disposed within the primary package substrate 305; and
a semiconductor die 325, the semiconductor die 325 having contacts electrically coupled to contacts of the PIC 310 (“the EIC 325 may be coupled to the PIC 320 using one or more vias in the substrate 305. For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320” at para. 0037).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the apparatus of Ramalingam can be modified, in accordance with the teachings of Mayukh, to have a PIC 106 die embedded and disposed within the primary package substrate 108. The motivation for such arrangement is that “by embedding PIC 320 within the substrate 305, the effects of warpage may be mitigated or altogether eliminated, and signal integrity preserved” (para. 0037 of Mayukh).
The Ramalingam – Mayukh combination considers (Fig. 3 of Mayukh) that the primary package substrate 305 can include a build-up region disposed between between the glass core 310 and the outer (top) surface and partially covering the top surface of the embedded PIC 220 while leaving a portion of the top surface exposed to the outside (Figs. 2 and 3 show embodiments with a partially embedded PIC 220 (para. 0032) and a fully embedded PIC 320 (para. 0035 and 0037), respectively), the build-up region including electrical routing (connecting the EIC die 325 and the PIOC die 320), the build-up (spacer) region between the glass core 310 and a first (right) subset of the first contacts (“the EIC 325 may be coupled to the PIC 320 using one or more vias in the substrate 305. For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320” at para. 0037 of Mayukh), a second (left) subset of the first contacts electrically coupled (by solder bumps) to (an exposed top surface of the PIC) independent of the electrical routing (through-glass-vias) in the build-up (spacer) region.
Regarding claim 6, the Ramalingam – Mayukh combination considers, as detailed above for claim 5, that the build-up region (spacer portion of the primary package substrate 305 between the EIC 325 and the PIC die 320 in Fig. 3 of Mayukh) is a first build-up region and the electrical routing is first electrical routing, the primary package substrate including a second build-up region including second electrical routing, the glass core between the first and second build-up regions, the glass core including a through glass via (TGV) extending through the glass core 310 to electrically couple the second electrical routing to the first electrical routing (“the EIC 325 may be coupled to the PIC 320 using one or more vias in the substrate 305. For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320” at para. 0037 of Mayukh), the first electrical routing electrically coupled to the first subset of the first contacts.
Regarding claim 7, the Ramalingam – Mayukh combination considers, as detailed above for claim 5, that the PIC (220 in Fig. 2 and 320 in Fig. 3 of Mayukh) is embedded in a cavity in the glass core 310, the primary package substrate 305 including a build-up (spacer) region containing electrical routing (through-glass vias), the build-up region positioned between the first contacts (of the EIC die 325) and the PIC 320, the electrical routing to electrically couple the PIC 320 to the first contacts (“the EIC 325 may be coupled to the PIC 320 using one or more vias in the substrate 305. For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320” at para. 0037 of Mayukh).
Regarding claim 21, the Ramalingam – Mayukh combination considers, as detailed above for claim 5, a step of electrically coupling (the exposed top surface of) the PIC 200 (as in the embodiment in Fig. 2 of Mayukh) to the fourth contacts (by solder bumps, as shown in Fig. 2) without a build-up region disposed therebetween.
Regarding claims 13 – 15, the Ramalingam – Mayukh combination teaches expressly or renders obvious all of the recited limitations, as detailed above for claims 5 – 7 and 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
Prosecution Insights