The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Claim Objections
Claims 8 – 15 are objected to because of the following informalities:
Claim 8 recites the limitation “attached to the second side the first package substrate”, which has a typographical error/omission. For the purposes of this Action, the limitation is interpreted as “attached to the second side of the first package substrate”. Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5 – 9, 11 – 17, 20, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Amano et al (US 2021/0104637 A1) in view of Mayukh et al (US 2023/0367087 A1), and further in view of Tang (US 2023/0178500 A1).
Regarding claim 1, Amano discloses (Fig. 27; para. 0131 – 0135) an apparatus 10, comprising:
a primary package substrate 100,300 including a core and first contacts 302 along an outer (upper) surface of the primary package substrate 100,300; a photonic integrated circuit (PIC) 200 (“Each of the semiconductor chips 200 is a photonic integrated circuit (PIC), and is, more specifically, a silicon photonics chip” at para. 0081) within the primary package substrate 100,300 adjacent a surface of the core (as seen in Fig. 27); and
a semiconductor die 420, the semiconductor die 420 including second contacts 426 on a second (bottom) side of the semiconductor die 420, the first contacts 302 electrically coupled (by conductive paths/vias 310; para. 0083) to the second contacts 426 (“One end of the conductive path 340 is connected to the electrode 302 connected to the bump 406 of the semiconductor chip 400, and the other end of the conductive path 340 is connected to the electrode 302 connected to the bump 426 of the semiconductor chip 420” at para. 0134; The semiconductor chip 420 (second semiconductor chip) is electrically connected to the semiconductor chip 200 through the conductive path 310. One end of the conductive path 310 is connected to the electrode 302 connected to the bump 426 of the semiconductor chip 420, and the other end of the conductive path 310 is connected to the electrode 206 of the semiconductor chip 200” at para. 0135).
Amano does not expressly teach that (i) the core of the primary package substrate 100 can be a glass core, and that (ii) the semiconductor die 400,420 can be supported on its upper side by a mold compound and thereby form a secondary package substrate which supports the semiconductor die 400,420 on a first (upper) side of the secondary package substrate. However, Mayukh and Tang provide features (i) and (ii), respectfully.
As for feature (i), Mayukh discloses (Figs. 2 and 3; para. 0030 – 0037) an apparatus, comprising:
a primary package substrate 305 including a glass core 310 (“the PIC 320 and/or EIC 325 may be embedded within the substrate 305. In some examples, the PIC is embedded inside a transmissive glass core 310 of the substrate 305, and configured to carry an optical signal to and/or from the PIC 320” at para. 0035, emphasis added);
a photonic integrated circuit (PIC) 310 within the primary package substrate 305 adjacent a surface of the glass core 310 (as seen in Fig. 27; ibid); and
a semiconductor die 325, the semiconductor die 325 having contacts electrically coupled to contacts of the PIC 310 (“the EIC 325 may be coupled to the PIC 320 using one or more vias in the substrate 305. For example, vias may be drilled into the glass core 310, allowing copper (or other metal) traces, pillars, and/or wires to couple the EIC 325 to the PIC 320” at para. 0037).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the core of the primary package substrate 100,300 in Amano can be, in accordance with the teachings of Mayukh, a glass core so that its optically transparent material can carry optical signals (e.g., from/to a fiber optic connector 500,510 to the PIC 200 via waveguides 320 the fiber optic connector 500, as shown in Fig. 25 of Amano; the fiber optic connector 500 corresponds to a fiber optical connector (FOC) 330b in Fig. 3 of Mayukh) to the PIC 200 directly through the primary package substrate 305 (“the substrate itself may be transmissive (e.g., glass), and thus the FOC may be bonded directly to the substrate, which may be configured to carry an optical signal between the FOC and the PIC. In further examples, the FOC may be coupled to the substrate via the one or more waveguides of the substrate” at para. 0050 of Mayukh; also para. 0035).
As for feature (ii), Tang discloses (Fig. 12B; para. 0036) an apparatus, comprising:
a primary package substrate 11 including a glass core (para. 0020 and 0022); and
a secondary package substrate 91,51 (mold compound with electric traces/vias; para. 0029, 0030, and 0036) supporting a semiconductor die 72 (IC die) on a first (upper) side of the secondary package substrate 91,51, the secondary package substrate 91,51 including second contacts 51A,51B on a second (lower) side of the secondary package substrate 91,51, first contacts (top surfaces of vias 41) of the primary package substrate 11 electrically coupled to the second contacts 51A,51B.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor die 400,420 of Amano can be supported, in accordance with the teachings of Tang, by a secondary package substrate that is formed as a mold compound that envelops the semiconductor die 400,420 and thereby provides mechanical and environmental protection for it.
An apparatus of the Amano – Mayukh – Tang combination is illustrated in Figure A below which is produced from Fig. 27 of Amano by identifying a glass core within the primary package substrate 100,300 (as taught by Mayukh) and disposing a mold compound (secondary package substrate) over the semiconductor die 400,420.
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Figure A. An apparatus of the Amano – Mayukh – Tang combination.
In light of the foregoing analysis, the Amano – Mayukh – Tang combination teaches expressly or renders obvious all of the recited limitations.
As an aside and relevant comment, it is also noted that the apparatus of the Amano – Mayukh – Tang combination has essential structural features that are substantially similar/identical to those of the claimed apparatus, as evident from a direct side-by-side comparison of Figure A with Fig. 1 of the instant application, Fig. 1 showing two vertically stacked package substrates 101,103 that are electrically coupled, the first package substrate 101 comprising an embedded PIC 130, the second package substrate comprising a mold compound 112 covering/encapsulating an semiconductor die 106,108 (para. 0024).
Regarding claim 8, the teachings of Amano, Mayukh, and Tang combine (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited limitations, as detailed above for claim 1. Specifically, the Amano – Mayukh – Tang combination considers an integrated circuit (IC) package 10, comprising:
a first (upper/secondary) package substrate (mold compound taught by Tang) having a first (upper) side and a second (lower) side opposite the first (upper) side;
a semiconductor die 420 mounted on the first (upper) side of the first package substrate;
a second (lower/primary) package substrate 100,300 attached to the second (lower) side of the first (upper) package substrate by solder (bump) interconnects 310,206,426 extending between the first and second package (upper and lower) substrates, the second (lower) package substrate 100,300 including a glass core (according to Mayukh); and
a photonic integrated circuit (PIC) 200 within the second (lower) package substrate 100,300 adjacent the glass core, the semiconductor die 420 electrically coupled to the PIC 200 through the solder (bump) interconnects 302,426 (as seen in Figure A; para. 0133 – 0135 of Amano; para. 0024, 0031, 0033, and 0040 of Mayukh).
Regarding claim 16, the teachings of Amano, Mayukh, and Tang combine (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited step limitations of a corresponding method of manufacturing of the contemplated IC package, as detailed above for claims 1 and 16. Specifically, the Amano – Mayukh – Tang combination considers a method of manufacturing an integrated circuit (IC) package, the method comprising:
providing a primary (lower) package substrate 100,300, the primary package substrate 100,300 including a glass core (a taught by Mayukh);
positioning a photonic integrated circuit (PIC) 200 adjacent a surface of the glass core;
providing first contacts 302 on a first (upper) side of the glass core;
providing a secondary (upper) package substrate and a semiconductor die 400,420 supported by the secondary (upper) package substrate on a first (upper) side of the secondary package substrate, a second (lower) side of the secondary package substrate including second contacts 426;
soldering the first contacts 302 to the second contacts 426 (para. 0133 – 0135 of Amano; para. 0024, 0031, 0033, and 0040 of Mayukh).
Regarding claims 2 and 17, the Amano – Mayukh – Tang combination renders obvious wherein the semiconductor die (at least one of 400 and 420) is a logic circuit die (para. 0054 of Mayukh), the logic circuit die electrically coupled to the PIC 320 via the coupled first and second contacts 302,426 (as seen in Figure A; para. 0133 – 0135 of Amano).
Regarding claims 7 and 20, the Amano – Mayukh – Tang combination considers (Figure A provided above for claim 1) that the PIC 200 is embedded in a cavity in the glass core, the primary (lower) package substrate 100,300 including a build-up region 300 containing electrical routing 102,340,310, the build-up region 300 positioned between the first contacts 302 and the PIC 200, the electrical routing 102,340,310 (its part 310) to electrically couple the PIC 200 to the first contacts 302 (para. 0086, 0087, and 0135 of Amano).
Regarding claims 5, 6, and 21, the Amano – Mayukh – Tang combination considers (see Figure A provided above for claim 1) that the primary (lower) package substrate 100,300 includes a build-up region 300 (some or all of the layers 300a-300f) between the glass core and the outer (upper) surface (separating 300f and the mold compound), the build-up region including electrical routing 102 (shown in Figure A and Fig. 27 of Amano and connecting contacts 106 and the semiconductor die 400), the build-up region between the glass core and a first (left) subset of the first contacts 302 (under the semiconductor die 400), a second (right) subset of the first contacts 302 (under the semiconductor die 420) electrically coupled to the PIC 200 independent of the electrical routing 102 in the build-up region 300 (as seen in Figure A).
Further for claim 21, the Amano – Mayukh – Tang combination considers BOTH embodiments (Fig. 27 of Amano) wherein optical waveguides 320 connecting a fiber optic connector 500,510 to the PIC 200 extend through a build-up region (some or all of the layers 300a-300f) and the PIC 200 is electrically connected to the semiconductor die 420 through the build-up region AND embodiments (Fig. 3 of Mayukh) wherein the PIC 320 is electrically connected to the semiconductor die 325 directly and without any intervening build-up region. Hence, the Amano – Mayukh – Tang combination renders obvious a composite/hybrid embodiment wherein the PIC 200 is electrically coupled to the second contacts 426 directly and without a build-up region disposed therebetween. Selection of a proper location and/or shape of the PIC 200 and/or the semiconductor die 420 is well within ordinary skill in the art.
Further for claim 6, the Amano – Mayukh – Tang combination renders obvious that the primary package substrate can have a build-up region on one or both sides thereof in order provide proper electrical routing and accommodate a difference(s) between the distances/pitches of electrical electrodes/wires on opposite sides of the primary package substrate: as seen in Fig. 27 of Amano the electrodes 106,206 can be disposed at a spacing/pitch different from that of solder bumps 108.
In such arrangement, the build-up region comprises a first (upper) build-up region and the electrical routing 102 is first electrical routing, the primary (lower) package including a second build-up (lower) region including second electrical routing, the glass core between the first (upper) and second (lower) build-up regions, the glass core including a through glass via (TGV) extending through the glass core to electrically couple the second (lower) electrical routing to the first (upper) electrical routing 102, the first electrical routing 102 electrically coupled to the first (left) subset of the first contacts 302 (under the semiconductor die 400).
Regarding claim 9, the Amano – Mayukh – Tang combination considers that the semiconductor die 420 is a first semiconductor die, the IC package further including a second semiconductor die 400 mounted on the first (upper) side of the first (upper) package substrate (with mold compound).
Regarding claims 11 and 12, the Amano – Mayukh – Tang combination considers that
the first semiconductor die 420 is electrically coupled to the second semiconductor die 400 through the first (upper) package substrate, wherein the first semiconductor die 420 is electrically coupled to the second semiconductor die 400 via an interconnect bridge 340, the interconnect bridge 340 positioned within the first package substrate: if some or all of the layers 300a-300f are interpreted as comprised in the first (upper) package substrate, rather than in the second (lower) package substrate. In other words, the first (upper) package substrate and the second (lower) package substrate can each comprise a respective build-up portion.
Regarding claims 13 and 14, the Amano – Mayukh – Tang combination considers that the second (lower) package substrate includes a build-up region (some or all of the layers 300a-300f) and a through glass via (TGV) (for traces 310), the build-up region between the glass core and the second side of the glass core, the TGV to extend through the glass core, the build-up region including electrical routing 310 to electrically couple the TGV to ones of the solder interconnects 302,426, wherein the build-up region (some or all of the layers 300a-300f) is positioned between the PIC 200 and the second (lower) side of the first (upper) package substrate, the PIC 200 electrically coupled to the semiconductor die 420 via the electrical routing 310 (para. 0135 of Amano).
Regarding claim 15, the Amano – Mayukh – Tang combination does not limit a relative location of the PIC 200 with respect to the upper and lower surfaces/sides of the glass core and renders obvious embodiments wherein the PIC 200 is fully or partially embedded into the glass core and protrudes from it towards the semiconductor die (compare Figs. 23 and 27 of Amano). In the latter case, the PIC 200 is a first distance away from the second (lower) side of the first (upper) package substrate, and the build-up region is a second distance away from the second (lower) side of the first (upper) package substrate, and the first distance may be less than or equal to the second distance. Determination of a proper/workable location of the PIC would be well within ordinary skill in the art.
Claims 3, 4, 10, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Amano in view of Mayukh, in view of Tang, and further in view of Winzer (US 2023/0077979 A1).
Regarding claim 3, 4, and 10, the Amano – Mayukh – Tang combination considers that the semiconductor die 400,420 comprises a first semiconductor die 400 and a second semiconductor die 420 of which at least one (e.g., 420) is a logic circuit die (as detailed above for claim 2). While the Amano – Mayukh – Tang combination considers that the other/first semiconductor die 400 can be an electronic integrated circuit (EIC), the Amano – Mayukh – Tang combination does not list an EIC driver as a particular possible/suitable type. However, Winzer discloses (Figs. 2 and 3; para. 0310 – 0327) an apparatus 210, comprising:
a PIC 214 (“a photonic integrated circuit 214” at para. 0317) that is embedded into a package substrate 211 and electrically coupled via contacts 212 to a first semiconductor die 217 and a second semiconductor die 216 of which at least one die is an EIC driver (“the electronic communication integrated circuit 215 can include electrical pre-amplifiers and/or electrical driver amplifiers electrically coupled, respectively, to photodetectors and modulators within the photonic integrated circuit 214” at para. 0319).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor die 400,420 in Amano can comprise a logic circuit die and an EIC driver die so that the latter is used to drive modulators formed/disposed within the PIC (para. 0319 of Winzer).
The logic circuit die is electrically coupled to an EIC driver via an interconnection bridge (corresponding to 340 in Fig. 27 of Amano) which can be formed in the secondary package substrate and/or the primary package substrate, depending on relative locations and shapes/sizes of the logic circuit die, the EIC driver die, and the PIC.
Regarding claims 18 and 19, the Amano – Mayukh – Tang – Winzer combination teaches expressly or renders obvious all of the recited limitations, as detailed above for claims 3, 4, and 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 12,189,195 B2 Figs. 28 – 32
US 11,107,770 B1 Fig. 1
US 2021/0149128 A1 Fig. 1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
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/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896