DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1, 9, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das et al (hereafter Das)(US Pub. 20200257527) in view of Mei et al (hereafter Mei)(US Pub. 20220309124).
Das was cited in the IDS filed 12/30/2022.
5. As to claim 1, Das discloses a floating-point unit incorporating functionality to enable a fused- multiply-add instruction (abstract fma operations), comprising:
logic to receive a first input operand, a second input operand ([0041]-[0043] and fig. 2 inputs), and a result format selector value, wherein the first input operand and the second input operand comprise floating-point values ([0052] and fig. 2, floating-point); and
fused multiply-add logic to process the first input operand, the second input operand, and the third input operand to produce a final result comprising one of a binary integer value and a floating point value based on the result format selector value ([0058]-[0060] FMA processing).
6. Das does not explicitly disclose a third input operand. However, Mei discloses a third input operand ([0143] up to 3 operands). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Das, by incorporating 3 operands, as taught by Mei. Using a plurality of different operands would not have limiting, as one of ordinary skill in the art would have the option of using different amounts of inputs as needed. This would have also been well-known knowledge to one of ordinary skill in the art prior to the effective filing date of the claimed invention, and thus; in views of Mei and the well-known knowledge, one of ordinary skill in the art would have been able to select from as many input operands as seen fit.
7. As to claim 9, Das discloses a system, comprising:
a plurality of processing cores ([0029] core architecture);
a cache memory ([0156] Cache); and
a plurality of accelerators that produce processing results to return to the cache memory (fig, 12A, 12B) for processing by the processing cores, wherein each of the plurality of accelerators include a plurality of floating-point units incorporating functionality to enable a fused multiply-add instruction ([0183]), wherein a floating-point unit of the plurality of floating-point units comprises:
logic to receive a first input operand, a second input operand, and a result format selector value, wherein the first input operand and the second input operand comprise floating-point values; and
fused multiply-add logic to process the first input operand and the second input operand to produce a final result comprising one of a binary integer value and a floating point value based on the result format selector value.
8. Das does not explicitly disclose artificial intelligence accelerators and a third input operand. However, Mei discloses artificial intelligence accelerators ([0044] and [0108]) and a third input operand ([0143] up to 3 operands). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Das, by incorporating 3 operands and applying them to artificial intelligence accelerators, as taught by Mei. Using a plurality of different operands would not have limiting, as one of ordinary skill in the art would have the option of using different amounts of inputs as needed. This would have also been well-known knowledge to one of ordinary skill in the art prior to the effective filing date of the claimed invention, and thus; in views of Mei and the well-known knowledge, one of ordinary skill in the art would have been able to select from as many input operands as seen fit.
9. As to claim 15, the claim is rejected for similar reasons as claims 1 and 9 above.
Allowable Subject Matter
10. Claims 2, 10, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least wherein the fused multiply-add logic comprises: inputting the result selector format value to a multiplexor, wherein the multiplexor passes a first shift amount in response to the result selector format value indicating that the final result is to be the binary integer value, and wherein the multiplexor passes a second shift amount in response to the result selector format value indicating that the final result is to be the floating point value.
The closest prior art of record US Pub. 20200257527 teaches the claimed floating-point with fused multiply add. However, the prior art of record does not teach or suggest at least wherein the fused multiply-add logic comprises: inputting the result selector format value to a multiplexor, wherein the multiplexor passes a first shift amount in response to the result selector format value indicating that the final result is to be the binary integer value, and wherein the multiplexor passes a second shift amount in response to the result selector format value indicating that the final result is to be the floating point value.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20140188968 – related to the field of processors and, in particular, to an energy efficient variable precision floating point computation circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151
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