DETAILED ACTION
Claims 1-20 are presented for examination.
Claims 6, 13, 16, and 17 are canceled.
This office action is in response to amendment of application on 27-APRIL-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 7, filed 27-APRIL-2026, with respect to objections to the drawings and claims have been fully considered and are persuasive due to amendments. The objections to the drawings and claims have been withdrawn.
Examiner notes that while not argued, Applicant has canceled claims 6, 13, 16, and 17. Rejections associated with these claims have therefore been withdrawn.
Applicant's arguments filed 27-APRIL-2026 have been fully considered but they are not persuasive.
1. Regarding Applicant’s argument that claims 4, 11, and 18 have been amended to overcome the rejections under 35 U.S.C. 112, Examiner respectfully disagrees. While Applicant has fixed one of the “local tag” recitations in each of the claims, Applicant has not fixed the second “local tag” recitation in each of the claims. Therefore, for the same reasons as in the last office action, claims 4, 11, and 18 remain rejected under 35 U.S.C. 112(b).
2. Regarding Applicant’s argument that the Farmahini’s access bit is fundamentally different from the used tag of claim 1 because it does not indicate whether data has recently been accessed, Examiner respectfully disagrees. As discussed in the previous office action’s rejection of claim 1 and in [0032], Farmahini teaches that the access bit indicates when a cache line has been accessed, with respect to the start of a critical section when the bit is initialized. While not strictly described as a recency bit, given that the access bit tells which cache lines were accessed since a known point in time in the same critical section (time period), it effectively indicates recent accesses.
3. Regarding Applicant’s argument that the flushing and loading of new data based on the first access bit is not a cache replacement selection based on a lowest combined tag value of claim 1, it is noted that the features upon which applicant relies (i.e., cache replacement selection based on a lowest combined tag value) are not recited in the rejected claim 1 that Applicant argues. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Claim 1 only broadly requires that some selection for a cache replacement in the partition is made and that it is somehow based, in no particular way, on some values of the local and used tags of the cachelines. According to Applicant’s own admission, Farmahini clearly teaches flushing and loading new data to the cache (cache replacement) which uses some consideration involving whether the data is remote or accessed, which clearly falls within the broadest reasonable interpretation of selecting cachelines for replacement based on values of the tags.
4. Regarding Applicant’s arguments that the bulk invalidation of Farmahini does not teach combining the bits into a composite cacheline value because it does not select individual cachelines for replacement based on a lowest combined tag value as supposedly claimed in claim 1, Examiner again notes that this feature of combining bits into a composite value, or selecting individual cachelines or a lowest combined tag value are features not even present within claim 1, and are not read into the claims. Furthermore, as discussed above, Farmahini involves a cache replacement process considering remoteness or access as required in the argued claim 1, because claim 1 contains broad limitations which the teachings of Farmahini fall within.
5. Regarding Applicant’s arguments that the stepping-through approach of Farmahini is distinct from selecting a cacheline having a lowest cacheline tag value supposedly found in claim 1, Examiner notes that selecting the cacheline with a lowest cacheline tag value is not recited in claim 1, and the argument is therefore not convincing for the same reasons as above.
6. Regarding Applicant’s request to withdraw the rejections under 35 U.S.C. 102 of the independent claims, and the rejections under 35 U.S.C. 103 of the dependent claims for the reasons above, since the arguments were not found to be convincing, the rejections are not withdrawn. However, since the claims have been amended, the rejections are updated below to address the amendments.
Examiner further notes that amendments to some claims that were not argued in Applicant’s remarks have necessitated new grounds of rejection, and the rejections are updated below to address those amendments.
Information Disclosure Statement
Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action.
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, lines 2-3, “processing circuitry to: receiving” should read “processing circuitry configured to: receive”.
In claim 5, line 5, “including” should read “includes”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 9, 11, 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4, in lines 3-4, recites the limitation “a second value of the local tag indicating that the cacheline is not recently accessed”, which represents an inconsistency between the claimed subject matter and the specification, which renders the scope of the claim uncertain (see MPEP 2173.03). For example, the specification describes the local tag to represent whether the data element stored in the cacheline is local data or remote data, and does not describe it to indicate whether the cacheline is recently accessed (see [0391-0392]). The claimed limitations present confusion about whether the functionality of the local tags should be interpreted to be changed, or if it is merely a drafting error.
For the purposes of examining over prior art, the limitation is interpreted to be “a second value of the used tag indicating that the cacheline is not recently accessed”, to maintain consistency with [0391-0393].
Claim 9 recites the limitation "the storage med" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 11, in lines 3-4, recites the limitation “a second value of the local tag indicating that the cacheline is not recently accessed”, which represents an inconsistency between the claimed subject matter and the specification, which renders the scope of the claim uncertain (see MPEP 2173.03). For example, the specification describes the local tag to represent whether the data element stored in the cacheline is local data or remote data, and does not describe it to indicate whether the cacheline is recently accessed (see [0391-0392]). The claimed limitations present confusion about whether the functionality of the local tags should be interpreted to be changed, or if it is merely a drafting error.
For the purposes of examining over prior art, the limitation is interpreted to “a second value of the used tag indicating that the cacheline is not recently accessed”, to maintain consistency with [0391-0393].
Claim 18, in lines 3-4, recites the limitation “a second value of the local tag indicating that the cacheline is not recently accessed”, which represents an inconsistency between the claimed subject matter and the specification, which renders the scope of the claim uncertain (see MPEP 2173.03). For example, the specification describes the local tag to represent whether the data element stored in the cacheline is local data or remote data, and does not describe it to indicate whether the cacheline is recently accessed (see [0391-0392]). The claimed limitations present confusion about whether the functionality of the local tags should be interpreted to be changed, or if it is merely a drafting error. For the purposes of examining over prior art, the limitation is interpreted to be “a second value of the used tag indicating that the cacheline is not recently accessed”, to maintain consistency with [0391-0393].
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 8-12, 14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
Claim 8 does not fall within at least one of the four categories of patent eligible subject matter because the broadest reasonable interpretation of the “computer-readable medium” recited in line 1 encompasses signals per se. The specification discloses that “Portions of various embodiments may be provided as a computer program product, which may include a computer-readable medium having stored thereon computer program instructions, which may be used to program a computer (or other electronic devices) for execution by one or more processors to perform a process according to certain embodiments. The computer-readable medium may include, but is not limited to, magnetic disks, optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or other type of computer-readable medium suitable for storing electronic instructions.” (see [0445]). The specification attempts provide examples of what a “computer-readable medium” could include, but fails to define “computer-readable medium” to clearly not include transitory signals per se. This rejection may be overcome by specifying “non-transitory computer-readable medium” in the claim.
Claims 9-12, 14 inherit this “computer-readable medium” element without further limiting it to exclude transitory signals per se, and also do not fall within at least one of the four categories of patent eligible subject matter for the same reasons as for claim 8.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-11, 14-15, 18, 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by
Farmahini Farahani et al., U.S. Pub. No. 20180239702 (hereinafter “Farmahini”)
Regarding claim 1: Farmahini teaches An apparatus comprising:
processing circuitry to receiving, by processing circuitry of the computing device, a request for data for a cluster of cores being associated with a cache partition, the cache partition storing data fetched from one or more of a local memory partition or a remote memory partition, the cache partition including cachelines, wherein a cacheline comprises: ([0019-0024], Farmahini teaches that the processing system includes a distributed memory system, which includes memory portions distributed across the processors, with each memory portion being local to one processor, which are further considered to be clusters of cores. Further, the caches include cache lines. Furthermore, in [0026], Farmahini teaches that the invention specifically associates the cache of a processor to the memory portion associated with the processor. Futhermore, in [0024], Farmahini teaches that the cache lines have a data portion, and that each processor may have memory addresses in the memory portion that can be accessed via the cache lines, the accesses for the data for the processor is interpreted to be the claimed request for data for a cluster of cores.)
a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition; and a used tag to indicate whether data stored in the cacheline is recently accessed, wherein ([0024], Farmahini teaches that cache lines include a metadata portion that includes bits, one of which indicates whether the cache line is associated with a memory address in a remote memory or memory local to its processor. Furthermore, in [0032], Farmahini teaches a first access bit in the metadata portion of the cache line which specifies whether the cache line has been accessed in a particular section of execution.)
wherein the cachelines are selected for a cache replacement in the cache partition based on values associated with the local and used tags of the cachelines. ([0032], Farmahini teaches a method of invalidation in which according to the first access bit and remote bit values of a cache line, the processor may flush a cache line and load new data for that cache line, which is a replacement selection based on values of the tags.)
Regarding claim 2: Farmahini teaches all limitations of claim 1, from which claim 2 depends.
Farmahini further teaches selecting the cachelines for cache replacement includes preferring replacement of remote data over local data. ([0034], Farmahini teaches that the invalidation according to the remote bits leaves cache lines associated with local memory unaffected, and only invalidates cache lines associated with remote memory.)
Regarding claim 3: Farmahini teaches all limitations of claim 1, from which claim 3 depends.
Farmahini further teaches the local tag of a cacheline tag of a cacheline comprises one bit, a first value of the local tag indicating local data and a second value of the local tag indicating remote data. ([0026] and [0028], Farmahini teaches that the remote bit is set to 0 when the cache line is associated with local data, and set to 1 when the cache line is associated with remote data.)
Regarding claim 4: Farmahini teaches all limitations of claim 1, from which claim 4 depends.
Farmahini further teaches the used tag of a cacheline tag of a cacheline comprises one bit, a first value of the used tag indicating that the cacheline is recently accessed and a second value of the local tag indicating that the cacheline is not recently accessed ([0032] and [0037], Farmahini teaches first access bits for each cache line, where each cache line has a one bit indicator, which indicates whether a cache line has been accessed for the first time in a particular section of a program execution, with one particular value indicating that the cache lines have not yet been accessed, and another value indicating the cache lines have been accessed.)
Regarding claim 7: Farmahini teaches all limitations of claim 1, from which claim 7 depends.
Farmahini further teaches the processing circuitry comprises graphics processing circuitry. ([0022], Farmahini teaches that the processors of the invention may include GPUs.)
Regarding claim 8: Farmahini teaches at least one computer-readable storage medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising: ([0041], Farmahini teaches that the disclosed invention is implemented using software encoded in a non-transitory computer readable medium which is executed on a processor.)
Receiving, by processing circuitry of the computing device, a request for data for a cluster of cores being associated with a cache partition, the cache partition storing data fetched from one or more of a local memory partition or a remote memory partition ([0018], Farmahini teaches a system which applies different operations (including loads) for caches, depending on whether an instruction’s operands indicate memory addresses local to a processor or addresses to memory remote to the processor. Further, in [0026] and [0028], Farmahini teaches that loads are specifically made by the processor to load new data from a memory portion either local to the processor or remote to the processor to a cache. Furthermore, in [0019-0022], Farmahini teaches that the processing system includes multiple processors, each with a cache including multiple cache levels and multiple cores, with each processor being distributed a memory portion. Therefore, Farmahini teaches the claimed receiving the request for data for a cluster of cores in a computing system (a processor which can load data from memory according to an instruction), the cluster of cores (processor) being associated with a cache partition, the cache partition storing data fetched from a local memory partition and a remote memory partition).
the cache partition including cachelines ([0024], Farmahini teaches that the caches have cache lines)
wherein a cacheline comprises: a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed, wherein ([0024], Farmahini teaches that cache lines include a metadata portion that includes bits, one of which indicates whether the cache line is associated with a memory address in a remote memory or memory local to its processor. Furthermore, in [0032], Farmahini teaches a first access bit in the metadata portion of the cache line which specifies whether the cache line has been accessed in a particular section of execution.)
the cachelines are selected for cache replacement in the cache partition based on values associated with the local and used tags of the cachelines. ([0032], Farmahini teaches a method of invalidation in which according to the first access bit and remote bit values of a cache line, the processor may flush a cache line and load new data for that cache line, which is a replacement selection based on values of the tags.)
Regarding claim 9: Farmahini teaches all limitations of claim 8, from which claim 9 depends.
Farmahini further teaches selecting the cachelines for cache replacement includes preferring replacement of remote data over local data. ([0034], Farmahini teaches that the invalidation according to the remote bits leaves cache lines associated with local memory unaffected, and only invalidates cache lines associated with remote memory.)
Regarding claim 10: Farmahini teaches all limitations of claim 8, from which claim 10 depends.
Farmahini further teaches the local tag of a cacheline tag of a cacheline comprises one bit, a first value of the local tag indicating local data and a second value of the local tag indicating remote data. ([0026] and [0028], Farmahini teaches that the remote bit is set to 0 when the cache line is associated with local data, and set to 1 when the cache line is associated with remote data.)
Regarding claim 11: Farmahini teaches all limitations of claim 8, from which claim 11 depends.
Farmahini further teaches the used tag of a cacheline tag of a cacheline comprises one bit, a first value of the used tag indicating that the cacheline is recently accessed and a second value of the local tag indicating that the cacheline is not recently accessed. ([0032] and [0037], Farmahini teaches first access bits for each cache line, where each cache line has a one bit indicator, which indicates whether a cache line has been accessed for the first time in a particular section of a program execution, with one particular value indicating that the cache lines have not yet been accessed, and another value indicating the cache lines have been accessed.)
Regarding claim 14: Farmahini teaches all limitations of claim 8, from which claim 14 depends.
Farmahini further teaches the processing circuitry comprises graphics processing circuitry. ([0022], Farmahini teaches that the processors of the invention may include GPUs.)
Regarding claim 15: Farmahini teaches A method comprising:
Receiving, by processing circuitry of a computing device, a request for data for a cluster of cores being associated with a cache partition, the cache partition storing data fetched from one or more of a local memory partition or a remote memory partition, ([0018], Farmahini teaches a system which applies different operations (including loads) for caches, depending on whether an instruction’s operands indicate memory addresses local to a processor or addresses to memory remote to the processor. Further, in [0026] and [0028], Farmahini teaches that loads are specifically made by the processor to load new data from a memory portion either local to the processor or remote to the processor to a cache. Furthermore, in [0019-0022], Farmahini teaches that the processing system includes multiple processors, each with a cache including multiple cache levels and multiple cores, with each processor being distributed a memory portion. Therefore, Farmahini teaches the claimed receiving the request for data for a cluster of cores in a computing system (a processor which can load data from memory according to an instruction), the cluster of cores (processor) being associated with a cache partition, the cache partition storing data fetched from a local memory partition and a remote memory partition).
the cache partition including cachelines, wherein ([0024], Farmahini teaches that the caches have cache lines)
a cacheline comprises: a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition; and a used tag to indicate whether data stored in the cacheline is recently accessed, wherein ([0024], Farmahini teaches that cache lines include a metadata portion that includes bits, one of which indicates whether the cache line is associated with a memory address in a remote memory or memory local to its processor. Furthermore, in [0032], Farmahini teaches a first access bit in the metadata portion of the cache line which specifies whether the cache line has been accessed in a particular section of execution.)
the cachelines are selected for a cache replacement in the cache partition based on values associated with the local and used tags of the cachelines. ([0032], Farmahini teaches a method of invalidation in which according to the first access bit and remote bit values of a cache line, the processor may flush a cache line and load new data for that cache line, which is a replacement selection based on values of the tags.)
Regarding claim 18: Farmahini teaches all limitations of claim 15, from which claim 18 depends.
Farmahini further teaches the used tag of a cacheline tag of a cacheline comprises one bit, a first value of the used tag indicating that the cacheline is recently accessed and a second value of the local tag indicating that the cacheline is not recently accessed ([0032] and [0037], Farmahini teaches first access bits for each cache line, where each cache line has a one bit indicator, which indicates whether a cache line has been accessed for the first time in a particular section of a program execution, with one particular value indicating that the cache lines have not yet been accessed, and another value indicating the cache lines have been accessed.)
Regarding claim 20: Farmahini teaches all limitations of claim 15, from which claim 20 depends.
Farmahini further teaches the processing circuitry comprises graphics processing circuitry. ([0022], Farmahini teaches that the processors of the invention may include GPUs.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 12, 19 are rejected under 35 U.S.C. 103 as being unpatentable over
Farmahini Farahani et al., U.S. Pub. No. 20180239702 (hereinafter “Farmahini”) in view of
COORAY et al., U.S. Pub. No. 20210349831 (hereinafter “Cooray”)
Regarding claim 5: Farmahini teaches all limitations of claim 4, from which claim 5 depends.
Farmahini further teaches a reset is triggered and all the used tags of the cachelines of the cache partition are set to the second value. ([0037], Farmahini teaches that at the start of the particular section of a program execution, the cache controller initializes all first access bits in the cache to a state indicating the cache lines have not yet been accessed for the first time in this section.)
Farmahini does not appear to explicitly disclose performing that reset when all used tags are set to the first value.
However, Cooray teaches upon the used tags of the cachelines of a cache partition being set to the first value, a reset is triggered and the used tags of the cachelines of the cache partition are set to the second value, wherein selecting the cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used, and that upon determining that there are no ways that were not recently used, the LRU bit proceeds to reset the LRU bits of other ways to the not recently used value. Further, the value of the bit indicating a not-recently-used way is a 0, which is the lowest value of the invention.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy which selects a cacheline for replacement with the lowest cacheline tag value, in which upon the used tags of a cache all being set to a used value, triggering a reset to set all the used tags of the cachelines of the cache to an unused value.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 12: Farmahini teaches all limitations of claim 11, from which claim 12 depends.
Farmahini further teaches triggering a reset and setting the used tags of the cachelines of the cache partition to the second value. ([0037], Farmahini teaches that at the start of the particular section of a program execution, the cache controller initializes all first access bits in the cache to a state indicating the cache lines have not yet been accessed for the first time in this section.)
Farmahini does not appear to explicitly disclose performing that reset when all used tags are set to the first value.
However, Cooray teaches upon the used tags of the cachelines of a cache partition being set to the first value, triggering a reset and setting the used tags of the cachelines of the cache partition to the second value, wherein selecting the cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used, and that upon determining that there are no ways that were not recently used, the LRU bit proceeds to reset the LRU bits of other ways to the not recently used value. Further, the value of the bit indicating a not-recently-used way is a 0, which is the lowest value of the invention.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy which selects a cacheline for replacement with the lowest cacheline tag value, in which upon the used tags of a cache all being set to a used value, triggering a reset to set all the used tags of the cachelines of the cache to an unused value.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 19: Farmahini teaches all limitations of claim 18, from which claim 19 depends.
Farmahini further teaches triggering a reset and setting the used tags of the cachelines of the cache partition are set to the second value. ([0037], Farmahini teaches that at the start of the particular section of a program execution, the cache controller initializes all first access bits in the cache to a state indicating the cache lines have not yet been accessed for the first time in this section.)
Farmahini does not appear to explicitly disclose performing that reset when all used tags are set to the first value.
However, Cooray teaches upon the used tags of the cachelines of a cache partition being set to the first value, triggering a reset and setting the used tags of the cachelines of the cache partition to the second value, wherein selecting the cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used, and that upon determining that there are no ways that were not recently used, the LRU bit proceeds to reset the LRU bits of other ways to the not recently used value. Further, the value of the bit indicating a not-recently-used way is a 0, which is the lowest value of the invention.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy which selects a cacheline for replacement with the lowest cacheline tag value, in which upon the used tags of a cache all being set to a used value, triggering a reset to set all the used tags of the cachelines of the cache to an unused value.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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