DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to submission of application on 30-DEC-2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action.
Drawings
The drawings are objected to because in the bottom of Fig. 32, “0: Remote Data, Note Recently Used” should read “0: Remote Data, Not Recently Used”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 4, 11, 18 are objected to because of the following informalities:
In claim 4, lines 2-3 “the local tag” should read “the used tag”
In claim 11, lines 2-3, “the local tag” should read “the used tag”
In claim 18, lines 2-3, “the local tag” should read “the used tag”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 11, 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4, in lines 2-3, recites the limitations “a first value of the local tag indicating that the cacheline is recently accessed” and “a second value of the local tag indicating that the cacheline is not recently accessed”, which represents an inconsistency between the claimed subject matter and the specification, which renders the scope of the claim uncertain (see MPEP 2173.03). For example, the specification describes the local tag to represent whether the data element stored in the cacheline is local data or remote data, and does not describe it to indicate whether the cacheline is recently accessed (see [0391-0392]). The claimed limitations present confusion about whether the functionality of the local tags should be interpreted to be changed, or if it is merely a drafting error. For the purposes of examining over prior art, the limitations are interpreted to be “a first value of the used tag indicating that the cacheline is recently accessed” and “a second value of the used tag indicating that the cacheline is not recently accessed”, to maintain consistency with [0391-0393].
Claim 11, in lines 2-3, recites the limitations “a first value of the local tag indicating that the cacheline is recently accessed” and “a second value of the local tag indicating that the cacheline is not recently accessed”, which represents an inconsistency between the claimed subject matter and the specification, which renders the scope of the claim uncertain (see MPEP 2173.03). For example, the specification describes the local tag to represent whether the data element stored in the cacheline is local data or remote data, and does not describe it to indicate whether the cacheline is recently accessed (see [0391-0392]). The claimed limitations present confusion about whether the functionality of the local tags should be interpreted to be changed, or if it is merely a drafting error. For the purposes of examining over prior art, the limitations are interpreted to be “a first value of the used tag indicating that the cacheline is recently accessed” and “a second value of the used tag indicating that the cacheline is not recently accessed”, to maintain consistency with [0391-0393].
Claim 18, in lines 2-3, recites the limitations “a first value of the local tag indicating that the cacheline is recently accessed” and “a second value of the local tag indicating that the cacheline is not recently accessed”, which represents an inconsistency between the claimed subject matter and the specification, which renders the scope of the claim uncertain (see MPEP 2173.03). For example, the specification describes the local tag to represent whether the data element stored in the cacheline is local data or remote data, and does not describe it to indicate whether the cacheline is recently accessed (see [0391-0392]). The claimed limitations present confusion about whether the functionality of the local tags should be interpreted to be changed, or if it is merely a drafting error. For the purposes of examining over prior art, the limitations are interpreted to be “a first value of the used tag indicating that the cacheline is recently accessed” and “a second value of the used tag indicating that the cacheline is not recently accessed”, to maintain consistency with [0391-0393].
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-11, 14-16 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by
Farmahini Farahani et al., U.S. Pub. No. 20180239702 (hereinafter “Farmahini”)
Regarding claim 1: Farmahini teaches An apparatus comprising:
a plurality of clusters of cores; ([0019] and [0022], Farmahini teaches a system with multiple processors, each with multiple cores together).
a clustered cache including a plurality of cache partitions for the plurality of clusters of cores, each cache partition including a plurality of cachelines; and ([0022], Farmahini teaches that each processor includes a cache with multiple cache levels, which is interpreted to be the plurality of cache partitions for the plurality of processors (clusters of cores). Each cluster of cores having a corresponding cache is interpreted to be the clustered cache. Furthermore, in [0024], Farmahini teaches that the caches have cache lines)
a computer memory including a plurality of memory partitions, each of the cache partitions being associated with a respective local memory partition; wherein ([0019], Farmahini teaches that the processing system includes a distributed memory system, which includes memory portions distributed across the processors, with each memory portion being local to one processor. Furthermore, in [0026], Farmahini teaches that the invention specifically associates the cache of a processor to the memory portion associated with the processor.)
each cacheline of the cache partitions includes a cacheline tag, each cacheline tag including: a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed; and ([0024], Farmahini teaches that cache lines include a metadata portion that includes bits, one of which indicates whether the cache line is associated with a memory address in a remote memory or memory local to its processor. Furthermore, in [0032], Farmahini teaches a first access bit in the metadata portion of the cache line which specifies whether the cache line has been accessed in a particular section of execution.)
wherein the clustered cache includes circuitry to select cachelines for cache replacement in a cache partition based on values of the tags of the cachelines. ([0032], Farmahini teaches a method of invalidation in which according to the first access bit and remote bit values of a cache line, the processor may flush a cache line and load new data for that cache line, which is a replacement selection based on values of the tags.)
Regarding claim 2: Farmahini teaches all limitations of claim 1, from which claim 2 depends.
Farmahini further teaches the selection of the cachelines for cache replacement includes preferring replacement of remote data over local data. ([0034], Farmahini teaches that the invalidation according to the remote bits leaves cache lines associated with local memory unaffected, and only invalidates cache lines associated with remote memory.)
Regarding claim 3: Farmahini teaches all limitations of claim 1, from which claim 3 depends.
Farmahini further teaches the local tag of a cacheline tag of a cacheline comprises one bit, a first value of the local tag indicating local data and a second value of the local tag indicating remote data. ([0026] and [0028], Farmahini teaches that the remote bit is set to 0 when the cache line is associated with local data, and set to 1 when the cache line is associated with remote data.)
Regarding claim 4: Farmahini teaches all limitations of claim 1, from which claim 4 depends.
Farmahini further teaches the used tag of a cacheline tag of a cacheline comprises one bit, a first value of the local tag indicating that the cacheline is recently accessed and a second value of the local tag indicating that the cacheline is not recently accessed ([0032] and [0037], Farmahini teaches first access bits for each cache line, where each cache line has a one bit indicator, which indicates whether a cache line has been accessed for the first time in a particular section of a program execution, with one particular value indicating that the cache lines have not yet been accessed, and another value indicating the cache lines have been accessed.)
Regarding claim 7: Farmahini teaches all limitations of claim 1, from which claim 7 depends.
Farmahini further teaches the apparatus comprises a graphical processing unit (GPU). ([0022], Farmahini teaches that the processors of the invention may include GPUs.)
Regarding claim 8: Farmahini teaches One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising: ([0041], Farmahini teaches that the disclosed invention is implemented using software encoded in a non-transitory computer readable medium which is executed on a processor.)
receiving a request for data for a cluster of cores in a computing system, the cluster of cores being associated with a cache partition, the cache partition storing data fetched from a local memory partition and a remote memory partition ([0018], Farmahini teaches a system which applies different operations (including loads) for caches, depending on whether an instruction’s operands indicate memory addresses local to a processor or addresses to memory remote to the processor. Further, in [0026] and [0028], Farmahini teaches that loads are specifically made by the processor to load new data from a memory portion either local to the processor or remote to the processor to a cache. Furthermore, in [0019-0022], Farmahini teaches that the processing system includes multiple processors, each with a cache including multiple cache levels and multiple cores, with each processor being distributed a memory portion. Therefore, Farmahini teaches the claimed receiving the request for data for a cluster of cores in a computing system (a processor which can load data from memory according to an instruction), the cluster of cores (processor) being associated with a cache partition, the cache partition storing data fetched from a local memory partition and a remote memory partition).
the cache partition including a plurality of cachelines ([0024], Farmahini teaches that the caches have cache lines)
each cacheline including: a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed; ([0024], Farmahini teaches that cache lines include a metadata portion that includes bits, one of which indicates whether the cache line is associated with a memory address in a remote memory or memory local to its processor. Furthermore, in [0032], Farmahini teaches a first access bit in the metadata portion of the cache line which specifies whether the cache line has been accessed in a particular section of execution.)
and selecting cachelines for cache replacement in the cache partition based on values of the tags of the cachelines. ([0032], Farmahini teaches a method of invalidation in which according to the first access bit and remote bit values of a cache line, the processor may flush a cache line and load new data for that cache line, which is a replacement selection based on values of the tags.)
Regarding claim 9: Farmahini teaches all limitations of claim 8, from which claim 9 depends.
Farmahini further teaches selecting the cachelines for cache replacement includes preferring replacement of remote data over local data. ([0034], Farmahini teaches that the invalidation according to the remote bits leaves cache lines associated with local memory unaffected, and only invalidates cache lines associated with remote memory.)
Regarding claim 10: Farmahini teaches all limitations of claim 8, from which claim 10 depends.
Farmahini further teaches the local tag of a cacheline tag of a cacheline comprises one bit, a first value of the local tag indicating local data and a second value of the local tag indicating remote data. ([0026] and [0028], Farmahini teaches that the remote bit is set to 0 when the cache line is associated with local data, and set to 1 when the cache line is associated with remote data.)
Regarding claim 11: Farmahini teaches all limitations of claim 8, from which claim 11 depends.
Farmahini further teaches the used tag of a cacheline tag of a cacheline comprises one bit, a first value of the local tag indicating that the cacheline is recently accessed and a second value of the local tag indicating that the cacheline is not recently accessed. ([0032] and [0037], Farmahini teaches first access bits for each cache line, where each cache line has a one bit indicator, which indicates whether a cache line has been accessed for the first time in a particular section of a program execution, with one particular value indicating that the cache lines have not yet been accessed, and another value indicating the cache lines have been accessed.)
Regarding claim 14: Farmahini teaches all limitations of claim 8, from which claim 14 depends.
Farmahini further teaches the apparatus comprises a graphical processing unit (GPU). ([0022], Farmahini teaches that the processors of the invention may include GPUs.)
Regarding claim 15: Farmahini teaches A method comprising:
receiving a request for data for a cluster of cores in a computing system, the cluster of cores being associated with a cache partition, the cache partition storing data fetched from a local memory partition and a remote memory partition, ([0018], Farmahini teaches a system which applies different operations (including loads) for caches, depending on whether an instruction’s operands indicate memory addresses local to a processor or addresses to memory remote to the processor. Further, in [0026] and [0028], Farmahini teaches that loads are specifically made by the processor to load new data from a memory portion either local to the processor or remote to the processor to a cache. Furthermore, in [0019-0022], Farmahini teaches that the processing system includes multiple processors, each with a cache including multiple cache levels and multiple cores, with each processor being distributed a memory portion. Therefore, Farmahini teaches the claimed receiving the request for data for a cluster of cores in a computing system (a processor which can load data from memory according to an instruction), the cluster of cores (processor) being associated with a cache partition, the cache partition storing data fetched from a local memory partition and a remote memory partition).
the cache partition including a plurality of cachelines ([0024], Farmahini teaches that the caches have cache lines)
each cacheline including: a local tag to indicate whether data stored in the cacheline is local data stored in the local memory partition or remote data stored in a remote memory partition, and a used tag to indicate whether data stored in the cacheline is recently accessed; ([0024], Farmahini teaches that cache lines include a metadata portion that includes bits, one of which indicates whether the cache line is associated with a memory address in a remote memory or memory local to its processor. Furthermore, in [0032], Farmahini teaches a first access bit in the metadata portion of the cache line which specifies whether the cache line has been accessed in a particular section of execution.)
and selecting cachelines for cache replacement in the cache partition based on values of the tags of the cachelines. ([0032], Farmahini teaches a method of invalidation in which according to the first access bit and remote bit values of a cache line, the processor may flush a cache line and load new data for that cache line, which is a replacement selection based on values of the tags.)
Regarding claim 16: Farmahini teaches all limitations of claim 15, from which claim 16 depends.
Farmahini further teaches selecting the cachelines for cache replacement includes preferring replacement of remote data over local data. ([0034], Farmahini teaches that the invalidation according to the remote bits leaves cache lines associated with local memory unaffected, and only invalidates cache lines associated with remote memory.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 12, 13, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Farmahini Farahani et al., U.S. Pub. No. 20180239702 (hereinafter “Farmahini”) in view of
COORAY et al., U.S. Pub. No. 20210349831 (hereinafter “Cooray”)
Regarding claim 5: Farmahini teaches all limitations of claim 4, from which claim 5 depends.
Farmahini further teaches a reset is triggered and all the used tags of the cachelines of the cache partition are set to the second value. ([0037], Farmahini teaches that at the start of the particular section of a program execution, the cache controller initializes all first access bits in the cache to a state indicating the cache lines have not yet been accessed for the first time in this section.)
Farmahini does not appear to explicitly disclose performing that reset when all used tags are set to the first value.
However, Cooray teaches upon the used tags of all the cachelines of a cache partition being set to the first value, a reset is triggered and… the used tags of the cachelines of the cache partition are set to the second value (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used, and that upon determining that there are no ways that were not recently used, the LRU bit proceeds to reset the LRU bits of other ways to the not recently used value.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy, in which upon the used tags of a cache all being set to a used value, triggering a reset to set all the used tags of the cachelines of the cache to an unused value.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 6: Farmahini teaches all limitations of claim 1, from which claim 6 depends.
Farmahini does not appear to explicitly disclose selecting cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value.
However, Cooray teaches selecting cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used (the 0 value, which is the lowest), and if there is one, it is selected as the victim candidate for cache replacement.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy, which selects a cacheline having the lowest cacheline tag value for replacement.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 12: Farmahini teaches all limitations of claim 11, from which claim 12 depends.
Farmahini further teaches triggering a reset and setting all the used tags of the cachelines of the cache partition are set to the second value. ([0037], Farmahini teaches that at the start of the particular section of a program execution, the cache controller initializes all first access bits in the cache to a state indicating the cache lines have not yet been accessed for the first time in this section.)
Farmahini does not appear to explicitly disclose performing that reset when all used tags are set to the first value.
However, Cooray teaches upon the used tags of all of the cachelines of a cache partition being set to the first value, triggering a reset and setting… the used tags of the cachelines of the cache partition are set to the second value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used, and that upon determining that there are no ways that were not recently used, the LRU bit proceeds to reset the LRU bits of other ways to the not recently used value.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy, in which upon the used tags of a cache all being set to a used value, triggering a reset to set all the used tags of the cachelines of the cache to an unused value.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 13: Farmahini teaches all limitations of claim 8, from which claim 13 depends.
Farmahini does not appear to explicitly disclose selecting cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value.
However, Cooray teaches selecting cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used (the 0 value, which is the lowest), and if there is one, it is selected as the victim candidate for cache replacement.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy, which selects a cacheline having the lowest cacheline tag value for replacement.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 18: Farmahini teaches all limitations of claim 15, from which claim 18 depends.
Farmahini further teaches the used tag of a cacheline tag of a cacheline comprises one bit, a first value in the local tag indicating that the cacheline is recently accessed and second value in the local tag indicating that the cacheline is not recently accessed. ([0032] and [0037], Farmahini teaches first access bits for each cache line, where each cache line has a one bit indicator, which indicates whether a cache line has been accessed for the first time in a particular section of a program execution, with one particular value indicating that the cache lines have not yet been accessed, and another value indicating the cache lines have been accessed.)
Farmahini does not appear to explicitly disclose a value of 1 or a value of 0 for the used tag.
However, Cooray teaches the used tag of a cache way tag of a cache way comprises one bit, a value of 1 in the local tag indicating that the cache way is recently accessed and a value of 0 in the local tag indicating that the cache way is not recently accessed. ([0205], Cooray teaches a least recently used bit for a cache way, in which a 1 indicates that it was accessed, and a 0 being a default not-accessed value.)
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement method in which used tags are one bit, in which a 1 value indicates that the cacheline was recently accessed, and a 0 value indicating that the cacheline was not.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Regarding claim 19: The combination of Farmahini and Cooray teaches all limitations of claim 18, from which claim 19 depends.
Farmahini/Cooray further teaches upon the used tags of all of the cachelines of a cache partition being set to a value of 1, triggering a reset and setting all the used tags of the cachelines of the cache partition are set to a value of 0. ([0037], Farmahini teaches that at the start of the particular section of a program execution, the cache controller initializes all first access bits in the cache to a state indicating the cache lines have not yet been accessed for the first time in this section. As discussed with respect to claim 18, state indicating non-accessed is a 0 value. Further, in Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 0 value indicating that there is a way that was not recently used, and that upon determining that there are no ways that were not recently used, the LRU bit proceeds to reset the LRU bits of other ways to 0. The combination of the two teachings is that upon the used tags being set to 1, resetting all the used bits to 0.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in claim 18.
Regarding claim 20: Farmahini teaches all limitations of claim 15, from which claim 20 depends.
Farmahini does not appear to explicitly disclose selecting cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value.
However, Cooray teaches selecting cachelines for cache replacement in a cache partition including selecting a cacheline having a lowest cacheline tag value. (Fig. 16 and [0205], Cooray teaches a cache replacement policy which determines if there are any ways with a 1-bit least recently used (LRU bit) value indicating that there is a way that was not recently used (the 0 value, which is the lowest), and if there is one, it is selected as the victim candidate for cache replacement.).
Farmahini and Cooray are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Farmahini and Cooray to achieve the combined result of the cache replacement strategy, which selects a cacheline having the lowest cacheline tag value for replacement.
One of ordinary skill in the art would have been motivated to make this modification in order to provide a way to facilitate allocating a cache to fulfill a request to cache new data when all eligible ways are full as discussed in Cooray [0204].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over
Farmahini Farahani et al., U.S. Pub. No. 20180239702 (hereinafter “Farmahini”)
Regarding claim 17: Farmahini teaches all limitations of claim 15, from which claim 17 depends.
Farmahini further teaches the local tag of a cacheline tag of a cacheline comprises one bit, a value of 1 in the local tag indicating local data and a value of 0 in the local tag indicating remote data. ([0026] and [0028], Farmahini teaches that the remote bit is set to 0 when the cache line is associated with local data, and set to 1 when the cache line is associated with remote data. While this is different from the claimed value of 1 in the tag indicating local data and the value of 0 in the tag indicating remote data, Farmahini teaches the bit as a remote bit, and not a local bit, which is merely an obvious inverse of the local bit. The remote bit of Farmahini fulfills the same purpose as the claimed local tag, done only in the inverse logic, and the difference is merely an obvious design choice difference.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ramanujan et al., U.S. Pub. No. 20140129767, teaches a memory system with a near and far memory, in which some of the near memory may be assigned to act as a cache for a range of the far memory for providing memory to applications.
Zyulkyarov et al., U.S. Pub. No. 20150227469, teaches a memory system with a near memory in which a portion is allocated as a cache for the far memory, which also implements a least recently used replacement policy to unpin data to pin new data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAITLYN HUNG PHAM whose telephone number is (571)272-6333. The examiner can normally be reached Mon-Thurs 8:00-6:00 EST.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133