CTNF 18/149,045 CTNF 100990 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement It is desirable to avoid the submission of long lists of documents if it can be avoided. An applicant's duty of disclosure of material and information is not satisfied by presenting a patent examiner with "a mountain of largely irrelevant [material] from which he is presumed to have been able, with his expertise and with adequate time, to have found the critical [material]. It ignores the real world conditions under which examiners work." Rohm & Haas Co. V. Crystal Chemical Co., 722 F.2d 1556, 1573 [220 USPQ 289] (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984). (Emphasis in original). Patent applicant has a duty not just to disclose pertinent prior art references but to make a disclosure in such way as not to "bury" it within other disclosures of less relevant prior art; See Golden Valley Microwave Foods Inc. V. Weaver Popcorn Co. Inc., 24 USPQ2d 1801 (N.D. Ind. 1992); Molins PLC V. Textron Inc., 26 USPQ2d 1889, at 1899 (D.Del 1992); Penn Yan Boats, Inc. V. Sea Lark Boats, Inc. et al., 175 USPQ 260, at 272 (S.D. FI. 1972). Eliminate clearly irrelevant and marginally pertinent cumulative information. If a long list is submitted, highlight those documents which have been specifically brought to applicant's attention and/or are known to be of most significance. See Penn Yan Boats, Inc. V. Sea Lark Boats, Inc., 359 F. Supp. 948, 175 USPQ 260 (S.D. Fla. 1972), aff'd, 479 F.2d 1338, 178 USPQ 577 (5th Cir. 1973), cert. denied, 414 U.S. 874 (1974). But cf. Molins PLC V. Textron Inc., 48 F.3d 1172, 33 USPQ2d 1823 (Fed. Cir. 1995). See MPEP 2004. Drawings Figs. 22-25, 28, 33-36, and 38 are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When zooming into the figures, pixelation of the letters, numbers and/or lines can be seen. This is a sign that the drawings were not drawn in a durable, clean, solid black, sufficiently dense and dark, and uniformly thick and well-defined manner. Furthermore, some of the drawings include text typed in white, which should instead be black Figs. 22, 24, 33-36, and 38 are objected for failing to comply with 37 CFR 1.84(p)(3), which requires that all numbers, letters, and reference characters are not to be placed upon hatched or shaded surfaces. Figs. 21, 31-32, and 41 are objected for failing to comply with 37 CFR 1.84(p)(3), which requires that all numbers, letters, and reference characters are not to cross or mingle with the lines. Figs. 24, 28, 33-35, and 37 are objected for failing to comply with 37 CFR 1.84(p)(3), which requires that all numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. Examiner believes that the text in the drawings do not meet this requirement, although every letter has not been measured. Figs. 33-36 and 38 are objected for failing to comply with 37 CFR 1.84(q), which requires lead lines for each reference character except for those which indicate the surface or cross section on which they are placed. The issues are as followed: Fig. 33: There is no lead line for 2105-EX and 2105. Fig. 34: There is no lead line for 2105-EX, 2105, and 3404. Fig. 35: There is no lead line for 3502 and 3504. Fig. 36: There is no lead line for 2117-4. Fig. 38: There is no lead line for 3106 and 3808. Note that such a reference character must be underlined to make it clear that a lead line has not been left out by mistake 06-22 AIA The drawings are objected to because of the following informalities: Fig. 6: Applicant should either delete the colons next to each “N” in the figure or clarify the use of the colon. Fig. 6: Bottom right element needs an opening bracket inserted before “N-1]”. Fig. 10: In box 1015, “SINGED” is a misspelling and should be corrected to “SIGNED”. Fig. 32: Applicant should either delete the colons next to each “N” in the figure or clarify the use of the colon. Fig. 32: Bottom right element needs an opening bracket inserted before “N-1]” . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The abstract of the disclosure is objected to because of the following informalities: The length of the abstract exceeds 150 words. Applicant is advised to make the abstract more concise as per 37 CFR 1.72(b). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). 07-29 AIA The disclosure is objected to because of the following informalities: [0076]: The phrase “strided memory accesses allows” is grammatically incorrect and should be addressed. [00128]: Second-to-last line, the word “intenger” is a misspelling and should be corrected to “integer”. [00136]: Second-to-last line, the phrase “a register maps” is grammatically incorrect and should be corrected to “a register map”. [00144]: Third-to-last line, the phrase “a register maps” is grammatically incorrect and should be corrected to “a register map”. [00153]: The matrices are not lined up correctly and should be fixed. [00155]: “kl” should be shifted right such that it’s under “ij”. [00157]: The extra “in” should be deleted. [00268+]: The example embodiments suffer the same issues with respect to the claim objections/rejections and should be fixed when appropriate. [00282]: Line 6, insert “computing” after “(throughput)” for clarity. [00292]: Line 18, the phrase “a register maps” is grammatically incorrect and should be corrected to “a register map” . Appropriate correction is required. Claim Objections 07-29-01 AIA Claim s 1-20 are objected to because of the following informalities: Claim 1 , line 6: The phrase “a first, a second, and a destination two-dimensional floating-point matrices” is grammatically incorrect. Examiner recommends that Applicant either removes all instances of “a” in the phrase, or replace “matrices” with “matrix”. Claim 2 , line 4: Insert “and” at the end of the line to improve grammar. Claim 9 , lines 5-6: The phrase “a first, a second, and a destination two-dimensional floating-point matrices” is grammatically incorrect. Examiner recommends that Applicant either removes all instances of “a” in the phrase, or replace “matrices” with “matrix”. Claim 10 , line 4: Insert “and” at the end of the line to improve grammar. Claim 17 , line 5: The phrase “a first, a second, and a destination two-dimensional floating-point matrices” is grammatically incorrect. Examiner recommends that Applicant either removes all instances of “a” in the phrase, or replace “matrices” with “matrix”. Claim 18 , line 4: Insert “and” at the end of the line to improve grammar. Claims 2-8, 10-16, and 18-24 are objected to for inheriting the objections of the claims in which they depend on . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-16 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph , as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the single instruction" in lines 9-10. There is insufficient antecedent basis for this limitation in the claim. It’s unclear if the limitation is referring to the “single instruction” in claim 1, line 9, or the “decoded single instruction” in claim 1, line 9. For the sake of examination, Examiner will interpret this limitation to be referring to the “decoded single instruction” in claim 1, line 9. Claim 9 is rejected for the same reason as claim 1. Claims 2-8 and 9-16 are rejected for inheriting the rejections of the claims in which they depend on. Claim 7 recites the limitation “the third two-dimensional floating-point matrix is stored in the storage for the destination two-dimensional floating-point matrix” in lines 1- 2. It’s unclear how the “third two-dimensional floating-point matrix” and the “destination two-dimensional floating-point matrix” are related. For the sake of examination, Examiner will interpret the “third two-dimensional floating-point matrix” and the “destination two-dimensional floating-point matrix” as referring to the same element. Claims 15 and 23 are rejected for the same reasons as claim 7. 07-36 AIA The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. 07-36-01 AIA Claim s 6-7, 14-15, and 22-23 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Regarding claim 6 , the claim recites “before the store of the resultant floating-point matrix…” then later indicates “wherein the store is of the updated resultant floating-point matrix…”. The limitations suggest that the “resultant floating-point matrix” is not stored, but instead the “updated resultant floating-point matrix” is instead stored. Therefore, claim 6 does not include all limitations of claim 1, specifically the “store the resultant floating-point matrix” in claim 1, second-to-last line. For the sake of compact prosecution, Examiner will interpret that the “updated resultant floating-point matrix” corresponds to the “resultant floating-point matrix”. Claims 14 and 22 are rejected for the same reasons as claim 6. Claims 7, 15, and 23 are rejected for inheriting the rejection of claims 6, 14, and 22 . Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 5-9, 13-17, and 21-24 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 21 of copending Application No. 17/929,749 (hereinafter Reference Application) in view of Subbareddy et al. (US 20210326135 A1). "Intel Architecture instruction Set Extensions and Future Features Programming Reference" is cited as extrinsic evidence to explain the details of the TDPBF16PS instruction. Regarding claim 1 , the Reference Application teaches an apparatus comprising: a matrix operations accelerator circuit (Claim 21: deep neural network accelerator) comprising: a two-dimensional grid of fixed-point processing elements (Claim 21: An array of processing elements) , and floating-point support circuitry coupled to the two-dimensional grid of fixed-point processing elements (Claim 21: One or more first digital circuits and one or more second digital circuits as the floating-point support circuitry) ; and determine, by the floating-point support circuitry, an extreme exponent for each row of the first two-dimensional floating-point matrix and for each column of the second two-dimensional floating-point matrix (Claim 21: The one or more first digital circuits retrieve the first extreme exponent of a row and the second extreme exponent of a column, which would indicate that the circuitry would have determined the extreme exponent for each row of a first floating-point matrix and each column of a second floating-point matrix) , generate, by the floating-point support circuitry, a first fixed-point matrix from the first two-dimensional floating-point matrix and a second fixed-point matrix from the second two-dimensional floating-point matrix (Claim 21: see “perform” step) , and generate, by the two-dimensional grid of fixed-point processing elements, corresponding fixed-point results by a multiplication of fixed-point elements of the first fixed-point matrix by corresponding fixed-point elements of the second fixed-point matrix (Claim 21: The array of processing elements would generate fixed-point results of the multiplication of the first fixed-point matrix and second fixed-point matrix) , scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents to generate scaled fixed-point results, and generate, by the floating-point support circuitry, a resultant floating-point matrix from the scaled fixed-point results (Claim 21: The one or more second digital circuits uses the first extreme exponents and second extreme exponents to generate a scaled fixed-point results, which creates the resultant floating-point matrix) . The Reference Application does not teach that the apparatus further comprises a hardware processor core coupled to the matrix operations accelerator circuit and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field that identifies the first two-dimensional floating-point matrix, a second field that identifies the second two-dimensional floating-point matrix, and an opcode . The Reference Application further does not teach that the matrix operations accelerator circuit comprises storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the floating-point support circuitry and that the matrix operations accelerator circuit is to store the resultant floating-point matrix into the destination two-dimensional floating-point matrix . Subbareddy teaches a hardware processor core coupled to the matrix operations accelerator circuit (Fig. 10 and [0081-0082]: out-of-order core 402 coupled to a TMUL matrix multiplication unit 207. The core 402 as the hardware processor core and the TMUL matrix multiplication unit as the matrix operations accelerator circuit) and comprising a decoder circuit to decode a single instruction into a decoded single instruction (Figs. 2B and 10, [0029, 0033, 0081-0083]: The core 402 may refer to processor core 52, which would indicate that core 402 includes a decoder circuit to decode instructions. Since the processor core can support AMX instructions, one of these instructions may be a tile matrix multiply instruction, such as TDPBF16PS (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17), which are to be performed by the TMUL matrix multiplication unit 207 through a matrix multiply command output by the core 402) , the single instruction including a first field that identifies the first two-dimensional floating-point matrix (The TDPBF16PS includes a field for a first operand, tmm2, which is a matrix comprising of floating point elements (BF16) (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , a second field that identifies the second two-dimensional floating-point matrix (The TDPBF16PS includes a field for a second operand, tmm3, which is a matrix comprising of floating point elements (BF16) (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , and an opcode (VEX.128.F3.0F38.W0 5C 11:rrr:bbb as the opcode for the TDPBF16PS instruction (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)). It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of the Reference Application with the teachings of Subbareddy to have a processor be coupled to an accelerator to handle instruction processing and command the matrix multiplication apparatus of Wu to perform fixed-point matrix multiplication. Separating the instruction processing pipeline with the matrix execution pipeline decreases the overhead of the processor core, which improve the performance of the processing system. Subbareddy further teaches storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the FMA computation grid (Fig. 10 and [0083]: 2D data buffer 416 coupled to the FMA computation grid 420 stores the input matrices (Matrix A and B) and the destination matrix (Matrix C). The matrices may be floating point if the instruction is recognized to use floating-point data elements, such as TDPBF16PS (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) and that the FMA computation grid is to store the resultant floating-point matrix into the destination two-dimensional floating-point matrix (Fig. 10 and [0083]: After an operation, such as multiplying matrices A and B together, the result is updated in matrix C and re-stored in the 2D data buffer) . It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of the Reference Application with the teachings of Subbareddy to have stored the matrix operands in a buffer coupled with the array of processing elements and to have stored the result of performing matrix multiplication in the same buffer. One of ordinary skill would recognize that by using a buffer to have data be transferred between two or more components, the component sending the data can work on other tasks without waiting for the component receiving the data to accept it, resulting in an increase in performance. Regarding claim 5 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 1, wherein the opcode further indicates the matrix operations accelerator circuit is to determine, by the floating-point support circuitry, the extreme exponent for each row of the first two-dimensional floating-point matrix before the first two-dimensional floating-point matrix is loaded into the storage and the extreme exponent for each column of the second two-dimensional floating-point matrix before the second two-dimensional floating-point matrix is loaded into the storage (Reference Application, claim 21; Subbareddy, Fig. 10 and [0083]: In the current combination, the matrices are first loaded into the 2D data buffer 416 before they are then loaded into the array of processing elements, in which the extreme exponents are then fetched from memory to then perform the conversion of floating-point matrices to fixed-point matrices. In other words, they are calculated prior to loading the floating-point matrices) . The Reference Application, in view of Subbareddy, does not teach to determine the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage . However, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of the Reference Application, in view of Subbareddy, to have determined the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage. Given the components of the Reference Application and Subbareddy, one of ordinary skill would have recognized that to have the extreme exponents be determined as they are loaded into the storage, they would move the components which calculates the extreme exponents to be located alongside the storage unit of Subbareddy. Hence, rearrangement of parts, i.e., rearranging the components to be placed alongside the storage unit, is deemed a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(C)). Regarding claim 6 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 1, wherein the single instruction includes a third field that identifies a third two-dimensional floating-point matrix (The TDPBF16PS includes a field for a third operand, tmm1, which is a matrix comprising of floating point elements (BF16) (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) . The Reference Application, in view of Subbareddy, does not teach that the opcode further indicates the matrix operations accelerator circuit is to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix, wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix . Note that the instruction TDPBF16PS includes an additional field, tmm1, to use as part of an accumulation step at the end of the matrix multiplication process (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17). Subbareddy also teaches to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix (Fig. 10 and [0083]: When executing the instruction TDPBF16PS, the matrix multiplication result of matrices A and B and Matrix C are added together, creating an updated resultant floating-point matrix. The matrix multiplication result as the resultant floating-point matrix. Matrix C as the third two-dimensional floating-point matrix (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix (Fig. 10 and [0083]: The updated resultant floating-point matrix is stored back to where Matrix C is stored in the 2D data buffer 416). It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of the Reference Application with the teachings of Subbareddy to have used the inner product matrix located be accumulated with the floating-point product results, then have the accumulated result be stored in the 2D data buffer. An accumulation step at the end of the matrix multiplication process is part of a common process in areas such as AI and machine learning. Therefore, by adding the step as part of the multiplication process rather than having a separate instruction to perform the accumulation part helps reduce the number of instructions performed, which improves the computing system performance. Regarding claim 7 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 6, wherein the third two-dimensional floating-point matrix is stored in the storage for the destination two-dimensional floating-point matrix (Reference Application, claim 21; Subbareddy, Fig. 10 and [0083]: In the current combination, the updated resultant floating-point matrix is stored back in the 2D data buffer) . Regarding claim 8 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 1, wherein the apparatus does not include a two-dimensional grid of floating-point processing elements (Reference Application, claim 21; Subbareddy, Fig. 10 and [0083]: In the current combination, the array of processing elements do not perform floating-point operations and the processing core does not comprise of floating-point processing elements. Therefore, the apparatus does not include a two-dimensional grid of floating-point processing elements). Regarding claims 9 and 13-16 , the claims recite a method similar to the apparatus of claims 1 and 5-7, respectively . Therefore, the claims are rejected on the same premises. Regarding claim 17 , the Reference Application teaches an apparatus (Claim 21: deep neural network accelerator) comprising: a two-dimensional grid of fixed-point processing elements (Claim 21: An array of processing elements) , and floating-point support circuitry coupled to the two-dimensional grid of fixed-point processing elements (Claim 21: One or more first digital circuits and one or more second digital circuits as the floating-point support circuitry) ; and determine, by the floating-point support circuitry, an extreme exponent for each row of the first two-dimensional floating-point matrix and for each column of the second two-dimensional floating-point matrix (Claim 21: The one or more first digital circuits retrieve the first extreme exponent of a row and the second extreme exponent of a column, which would indicate that the circuitry would have determined the extreme exponent for each row of a first floating-point matrix and each column of a second floating-point matrix) , generate, by the floating-point support circuitry, a first fixed-point matrix from the first two-dimensional floating-point matrix and a second fixed-point matrix from the second two-dimensional floating-point matrix (Claim 21: see “perform” step) , and generate, by the two-dimensional grid of fixed-point processing elements, corresponding fixed-point results by a multiplication of fixed-point elements of the first fixed-point matrix by corresponding fixed-point elements of the second fixed-point matrix (Claim 21: The array of processing elements would generate fixed-point results of the multiplication of the first fixed-point matrix and second fixed-point matrix) , scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents to generate scaled fixed-point results, and generate, by the floating-point support circuitry, a resultant floating-point matrix from the scaled fixed-point results (Claim 21: The one or more second digital circuits uses the first extreme exponents and second extreme exponents to generate a scaled fixed-point results, which creates the resultant floating-point matrix) . The Reference Application does not teach that the apparatus comprises storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the floating-point support circuitry and controller circuitry to control the two-dimensional grid of fixed-point processing elements, and that apparatus is to store the resultant floating-point matrix into the destination two-dimensional floating-point matrix . Subbareddy teaches storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the FMA computation grid (Fig. 10 and [0083]: 2D data buffer 416 coupled to the FMA computation grid 420 stores the input matrices (Matrix A and B) and the destination matrix (Matrix C). The matrices may be floating point if the instruction is recognized to use floating-point data elements, such as TDPBF16PS (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)), controller circuitry to control the FMA computation grid (Fig. 10 and [0083]: The TMUL control circuitry 417 sends operations to be performed in the FMA computation grid), and that the FMA computation grid is to store the resultant floating-point matrix into the destination two-dimensional floating-point matrix (Fig. 10 and [0083]: After an operation, such as multiplying matrices A and B together, the result is updated in matrix C and re-stored in the 2D data buffer) . It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of the Reference Application with the teachings of Subbareddy to have control circuitry control the array of processing elements and have stored the matrix operands in a buffer coupled with the array of processing elements and to have stored the result of performing matrix multiplication in the same buffer. Having control circuitry be coupled to the array of processing elements allows one of ordinary skill to have control on the operations to be performed in the array of processing elements, which may be appreciated. One of ordinary skill would recognize that by using a buffer to have data be transferred between two or more components, the component sending the data can work on other tasks without waiting for the component receiving the data to accept it, resulting in an increase in performance. Regarding claim 21 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 17, wherein the controller circuitry is to cause the floating-point support circuitry to determine the extreme exponent for each row of the first two-dimensional floating-point matrix before the first two-dimensional floating-point matrix is loaded into the storage and the extreme exponent for each column of the second two-dimensional floating-point matrix before the second two-dimensional floating-point matrix is loaded into the storage (Reference Application, claim 21; Subbareddy, Fig. 10 and [0083]: In the current combination, the matrices are first loaded into the 2D data buffer 416 before they are then loaded into the array of processing elements, in which the extreme exponents are then fetched from memory to then perform the conversion of floating-point matrices to fixed-point matrices. In other words, they are calculated prior to loading the floating-point matrices) . The Reference Application, in view of Subbareddy, does not teach to determine the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage . However, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of the Reference Application, in view of Subbareddy, to have determined the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage. Given the components of the Reference Application and Subbareddy, one of ordinary skill would have recognized that to have the extreme exponents be determined as they are loaded into the storage, they would move the components which calculates the extreme exponents to be located alongside the storage unit of Subbareddy. Hence, rearrangement of parts, i.e., rearranging the components to be placed alongside the storage unit, is deemed a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(C)). Regarding claim 22 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 17, wherein the storage is also for a third two-dimensional floating-point matrix (Subbareddy, Fig. 10 and [0083]: The 2D data buffer 416 stores matrix C, where matrix C corresponds to the product of matrix A and B. Matrix C as the third two-dimensional floating-point matrix) . The Reference Application, in view of Subbareddy, does not teach that the controller circuitry is to cause the floating-point support circuitry to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix, wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix . Subbareddy also teaches to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix (Fig. 10 and [0083]: When executing the instruction TDPBF16PS, the matrix multiplication result of matrices A and B and Matrix C are added together, creating an updated resultant floating-point matrix. The matrix multiplication result as the resultant floating-point matrix. Matrix C as the third two-dimensional floating-point matrix (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix (Fig. 10 and [0083]: The updated resultant floating-point matrix is stored back to where Matrix C is stored in the 2D data buffer 416). It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of the Reference Application with the teachings of Subbareddy to have used the inner product matrix located be accumulated with the floating-point product results, then have the accumulated result be stored in the 2D data buffer. An accumulation step at the end of the matrix multiplication process is part of a common process in areas such as AI and machine learning. Therefore, by adding the step as part of the multiplication process rather than having a separate instruction to perform the accumulation part helps reduce the number of instructions performed, which improves the computing system performance. Regarding claim 23 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 22, wherein the third two-dimensional floating-point matrix is stored in the storage for the destination two-dimensional floating-point matrix (Reference Application, claim 21; Subbareddy, Fig. 10 and [0083]: In the current combination, the updated resultant floating-point matrix is stored back in the 2D data buffer) . Regarding claim 24 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 17, wherein the apparatus does not include a two-dimensional grid of floating-point processing elements (Reference Application, claim 21; Subbareddy, Fig. 10 and [0083]: In the current combination, the array of processing elements do not perform floating-point operations and the processing core does not comprise of floating-point processing elements. Therefore, the apparatus does not include a two-dimensional grid of floating-point processing elements) . 08-37 AIA Claim s 2-4, 10-12, and 18-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 21 of copending Application No. 17/929,749 (hereinafter Reference Application) in view of Subbareddy et al. (US 20210326135 A1) and Wu et al. (US 20230367548 A1). Regarding claim 2 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 1 . The Reference Application, in view of Subbareddy, does not teach that the opcode further indicates the matrix operations accelerator circuit is to: partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks, generate, by the two-dimensional grid of fixed-point processing elements, the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix . Wu teaches to partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks (Fig. 5 and [0077-0082]: The input vectors (identified as a third and fourth input vector) are first processed normally through the data extraction module 510 (same as data extraction module 210), converting the data elements into fixed-point, before they are partitioned into a plurality of smaller vectors (identified as a plurality of first and second vectors) by the data extraction module. The plurality of smaller vectors as the plurality of chunks comprising of the first fixed-point matrix and second fixed-point matrix) , generate, by the two-dimensional grid of fixed-point processing elements, the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix (Figs. 5 and 7, [0077-0082]: The plurality of smaller vectors are then sent to the multiplication module 520 such that a multiplication of chunks of the first fixed-point matrix and chunks of the second fixed-point matrix are generated, all occurring within the matrix multiplication apparatus) . It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of the Reference Application, in view of Subbareddy, with the teachings of Wu to have partitioned each row vector and column vector into smaller vectors and perform multiplication on the smaller vectors. By reducing the size of the vectors into smaller chunks, one of ordinary skill could reduce the size of the components which perform the multiplication of the vectors. The reduction in component size reduces the power consumption and heat produced by the components, which may be preferred by one of ordinary skill. Regarding claim 3 , the Reference Application, in view of Subbareddy and Wu, teaches the apparatus of claim 2, wherein the opcode further indicates the matrix operations accelerator circuit is to scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents and a chunk offset to generate the scaled fixed-point results (Claim 21: In the current combination, the fixed-point results are to be scaled by the extreme exponents calculated by the components of the DNN accelerator). The Reference Application, in view of Subbareddy and Wu, does not teach that the scaled fixed-point results are generated according to the extreme exponents and a chunk offset . Wu also teaches to generate the scaled fixed-point results according to the extreme exponents and a chunk offset ([0062-0077]: The fixed-point results are shifted by a specific amount (i.e., a chunk offset) and then uses the extreme exponent (denoted as ab.e.max) to calculate the scaled fixed-point result, which is then interpreted to be floating point value as a result). It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of the Reference Application, in view of Subbareddy, with the teachings of Wu to have generated the scaled fixed-point result according to the extreme exponents and chunk offset. One of ordinary skill would recognize that by shifting a large value, precision loss of data can be avoided (see [0066]), which may be appreciated. Regarding claim 4 , the Reference Application, in view of Subbareddy and Wu, teaches the apparatus of claim 2, wherein the opcode further indicates the matrix operations accelerator circuit is to partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into at least three chunks (Wu, Fig. 5 and [0077-0082]: The third and fourth vectors are divided at least once. Therefore, creating at least two first vectors and two second vectors, resulting in a total amount of four smaller vectors (i.e., chunks)) . Regarding claims 10-12 , the claims recite a method similar to the apparatus of claims 2-4, respectively . Therefore, the claims are rejected on the same premises. Regarding claim 18 , the Reference Application, in view of Subbareddy, teaches the apparatus of claim 17. The Reference Application, in view of Subbareddy, does not teach that the controller circuitry is to cause the two-dimensional grid of fixed-point processing elements and the floating-point support circuitry to: partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks, generate, by the two-dimensional grid of fixed-point processing elements, the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix . Wu teaches to partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks (Fig. 5 and [0077-0082]: The input vectors (identified as a third and fourth input vector) are first processed normally through the data extraction module 510 (same as data extraction module 210), converting the data elements into fixed-point, before they are partitioned into a plurality of smaller vectors (identified as a plurality of first and second vectors) by the data extraction module. The plurality of smaller vectors as the plurality of chunks comprising of the first fixed-point matrix and second fixed-point matrix) , generate, by the two-dimensional grid of fixed-point processing elements, the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix (Figs. 5 and 7, [0077-0082]: The plurality of smaller vectors are then sent to the multiplication module 520 such that a multiplication of chunks of the first fixed-point matrix and chunks of the second fixed-point matrix are generated, all occurring within the matrix multiplication apparatus) . It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of the Reference Application, in view of Subbareddy, with the teachings of Wu to have partitioned each row vector and column vector into smaller vectors and perform multiplication on the smaller vectors. By reducing the size of the vectors into smaller chunks, one of ordinary skill could reduce the size of the components which perform the multiplication of the vectors. The reduction in component size reduces the power consumption and heat produced by the components, which may be preferred by one of ordinary skill. Regarding claim 19 , the Reference Application, in view of Subbareddy and Wu, teaches the apparatus of claim 18, wherein the controller circuitry is to cause the floating-point support circuitry to scale the corresponding fixed-point results according to the extreme exponents and a chunk offset to generate the scaled fixed-point results (Claim 21: In the current combination, the fixed-point results are to be scaled by the extreme exponents calculated by the components of the DNN accelerator) . The Reference Application, in view of Subbareddy and Wu, does not teach that the scaled fixed-point results are generated according to the extreme exponents and a chunk offset . Wu also teaches to generate the scaled fixed-point results according to the extreme exponents and a chunk offset ([0062-0077]: The fixed-point results are shifted by a specific amount (i.e., a chunk offset) and then uses the extreme exponent (denoted as ab.e.max) to calculate the scaled fixed-point result, which is then interpreted to be floating point value as a result). It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of the Reference Application, in view of Subbareddy, with the teachings of Wu to have generated the scaled fixed-point result according to the extreme exponents and chunk offset. One of ordinary skill would recognize that by shifting a large value, precision loss of data can be avoided (see [0066]), which may be appreciated. Regarding claim 20 , the Reference Application , in view of Subbareddy and Wu, teaches the apparatus of claim 18, wherein the controller circuitry is to cause the floating-point support circuitry to partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into at least three chunks (Wu, Fig. 5 and [0077-0082]: The third and fourth vectors are divided at least once. Therefore, creating at least two first vectors and two second vectors, resulting in a total amount of four smaller vectors (i.e., chunks)) . This is a provisional nonstatutory double patenting rejection. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Step 1 : Claims 1, 9, and 17 recite an apparatus, method, and an apparatus, respectively. Therefore, claims 1, 9, and 17 are directed to a process, machine, manufacture, or composition of matter. Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “determine… an extreme exponent for each row of the first two-dimensional floating-point matrix and for each column of the second two-dimensional floating-point matrix”, “generate… a first fixed-point matrix from the first two-dimensional floating-point matrix and a second fixed-point matrix from the second two-dimensional floating-point matrix”, “generate… corresponding fixed-point results by a multiplication of fixed-point elements of the first fixed-point matrix by corresponding fixed-point elements of the second fixed-point matrix”, “scale… the corresponding fixed-point results according to the extreme exponents to generate scaled fixed-point results”, and “generate… a resultant floating-point matrix from the scaled fixed-point results”. Such limitations cover mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations and mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). Accordingly, the claim recites an abstract idea. Under Prong Two of Step 2A , this judicial exception is not integrated into a practical application. The elements “a matrix operations accelerator circuit”, “a two-dimensional grid of fixed-point processing elements”, “floating-point support circuitry”, “storage for a first, a second, and a destination two-dimensional floating-point matrices”, “a hardware processor core”, “a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field that identifies the first two-dimensional floating-point matrix, a second field that identifies the second two-dimensional floating-point matrix, and an opcode”. Such elements amount to no more than mere instructions to apply the exception using generic computer elements and/or elements recited at a high level (MPEP 2106.05(f)). Additionally, the claim recites “store the resultant floating-point matrix into the destination two-dimensional floating-point matrix”, which is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory). Thus, the elements fail to integrate the judicial exception into a practical application. Under Step 2B , the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously, with respect to Step 2A Prong Two, the additional elements in the claim amount to no more than mere instructions to apply the exception (see MPEP 2106.05(f)) and the additional element of data gathering is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). Accordingly, this claim is not patent-eligible under 35 U.S.C. 101. Regarding claim 2 , the claim recites “partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks” and “generate… the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix”. Such limitations further cover mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations and/or mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claim 3 , the claim recites “scale… the corresponding fixed-point results according to the extreme exponents and a chunk offset to generate the scaled fixed-point results”. Such limitation further covers mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations and mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claim 4 , the claim recites “partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into at least three chunks”. Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claim 5 , the claim recites “determine… the extreme exponent for each row of the first two-dimensional floating-point matrix… and the extreme exponent for each column of the second two-dimensional floating-point matrix”. Such limitation further covers mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations and mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim additionally recites “the first two-dimensional floating-point matrix is loaded into the storage” and “the second two-dimensional floating-point matrix is loaded into the storage”. The additional elements are considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claim 6 , the claim recites “accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix”. Such limitation further covers mathematical concepts such as mathematical relationships, mathematical formulas/equations, or mathematical calculations and mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The element “the single instruction includes a third field that identifies a third two-dimensional floating-point matrix” is recited at a high level of generality, which amounts to no more than mere instructions to apply the exception (MPEP 2106.05(f)). The element “the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix” is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claim 7 , the claim recites “the third two-dimensional floating-point matrix is stored in the storage for the destination two-dimensional floating-point matrix”, which is considered to be an insignificant step of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claim 8 , the claim recites “the apparatus does not include a two-dimensional grid of floating-point processing elements”. The element is recited at a high level of generality, which amounts to no more than mere instructions to apply the exception (MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claims 9-16 , the claims recite a method similar to the apparatus of claims 1-8, respectively . Therefore, the claims are rejected on the same premises. Regarding claims 17 , the claim is mostly rejected for the same reasons as claim 1. The claim additionally recites the element “controller circuitry”. The element is recited at a high level of generality, i.e., generic computer components, which amounts to no more than mere instructions to apply the exception (MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible. Regarding claims 18-24 , the claims recite an apparatus similar to the apparatus of claims 2-8, respectively . Therefore, the claims are rejected on the same premises. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim (s) 17-20 and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu et al. (US 20230367548 A1) . Regarding claim 17 , Wu teaches an apparatus (Fig. 10 and [0104-0106]: The electronic device 1000 as the apparatus) comprising: a two-dimensional grid of fixed-point processing elements (Figs. 2, 7, and 10, [0037-0038, 0084-0086, 0104-0106]: The computing unit 1001 within electronic device 1000 comprises of a two dimensional grid of vector multiplication apparatuses, which performs fixed-point operations. Therefore, the vector multiplication apparatuses are fixed-point processing elements) ; floating-point support circuitry coupled to the two-dimensional grid of fixed-point processing elements (Fig. 2 and [0038-0031, 0053. 0057-0073]: The data extraction module 210, inverse fixed point conversion module 260, shift module 240, and the exponent comparison module 230 as the floating-point support circuitry, having functions corresponding to the conversion of floating point to fixed point and vice versa, whereas the exponent comparison module aids in the conversions) ; storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the floating-point support circuitry (Figs. 6 and 9, [0083, 0095-0096]: The operation apparatus 900 is to be coupled with the matrix multiplication apparatus such that it’s able to perform the method in Fig. 6 for the matrix multiplication apparatus. The first matrix and second matrix are stored in the fourth obtaining unit 910 and the inner product matrix is stored in the fifth obtaining unit 920) ; and controller circuitry to cause the two-dimensional grid of fixed-point processing elements (Figs. 7 and 10, [0084-0085, 0106]: The computing unit 1001 may be a controller implemented with the matrix multiplication apparatus and to perform an inner product of matrices) and the floating-point support circuitry to: determine, by the floating-point support circuitry, an extreme exponent for each row of the first two-dimensional floating-point matrix and for each column of the second two-dimensional floating-point matrix (Fig. 2 and [0008, 0044, 0053, 0057, 0067]: The data extraction module 210 extracts the exponents of a first and second vector. Where the first vector (i.e., vector A) may be a row vector of a first matrix (i.e., matrix A) and the second vector (i.e., vector B) may be a column vector of a second matrix (i.e., matrix B). The exponent comparison module then adds the exponents for each corresponding vector element (see [0057] for formula) to create a vector of the summation of exponents and identifies the maximum exponent value from the vector of the summation of exponents (identified as ab.e.max in the specification). The maximum exponent value as the extreme exponent of a corresponding row vector of a first matrix and column vector of a second matrix) , generate, by the floating-point support circuitry, a first fixed-point matrix from the first two-dimensional floating-point matrix and a second fixed-point matrix from the second two-dimensional floating-point matrix (Fig. 2 and [0008, 0044, 0053, 0057, 0067]: The data extraction module 210 extracts the exponents of a first and second vector. Where the first vector (i.e., vector A) may be a row vector of a first matrix (i.e., matrix A) and the second vector (i.e., vector B) may be a column vector of a second matrix (i.e., matrix B). The exponent comparison module then adds the exponents for each corresponding vector element (see [0057] for formula) to create a vector of the summation of exponents and identifies the maximum exponent value from the vector of the summation of exponents (identified as ab.e.max in the specification). The maximum exponent value as the extreme exponent of a corresponding row vector of a first matrix and column vector of a second matrix) , generate, by the two-dimensional grid of fixed-point processing elements, corresponding fixed-point results by a multiplication of fixed-point elements of the first fixed-point matrix by corresponding fixed-point elements of the second fixed-point matrix (Figs. 2 and 7, [0052-0073]: Each vector multiplication apparatus performs fixed point multiplication of the converted row vector and column vector (i.e., the fixed point elements) from the data extraction module 210 using the fixed point multiplication module 220, which results in an output vector of the multiplication result (identified as vector M in the specification). The output vector is then shifted before the products are then added into a singular fixed-point product result. The matrix fixed-point product result, when generated by all vector multiplication apparatuses, as the fixed-point results) , scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents to generate scaled fixed-point results (Figs. 2 and 7, [0074-0076]: The maximum exponent value is used in an equation to generate an exponent data value. Then, the product of the exponent data value and the fixed-point product result is calculated using the inverse fixed point conversion module 260 to generate a scaled fixed-point product result) , generate, by the floating-point support circuitry, a resultant floating-point matrix from the scaled fixed-point results (Figs. 2 and 7, [0075-0076]: Each inverse fixed point conversion module 260 within each vector multiplication apparatus generates a floating-point inner-product calculation result, which would generate a floating-point inner-product result matrix. The inner-product result matrix as the resultant floating-point matrix) , and store the resultant floating-point matrix into the destination two-dimensional floating-point matrix (Figs. 6 and 9, [0083, 0096]: The inner-product matrix result is to be stored in the fifth obtaining unit 920) . Regarding claim 18 , Wu teaches the apparatus of claim 17, wherein the controller circuitry is to cause the two-dimensional grid of fixed-point processing elements and the floating-point support circuitry to: partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks (Fig. 5 and [0077-0082]: The input vectors (identified as a third and fourth input vector) are first processed normally through the data extraction module 510 (same as data extraction module 210), converting the data elements into fixed-point, before they are partitioned into a plurality of smaller vectors (identified as a plurality of first and second vectors) by the data extraction module. The plurality of smaller vectors as the plurality of chunks comprising of the first fixed-point matrix and second fixed-point matrix) , generate, by the two-dimensional grid of fixed-point processing elements, the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix (Figs. 5 and 7, [0077-0082]: The plurality of smaller vectors are then sent to the multiplication module 520 such that a multiplication of chunks of the first fixed-point matrix and chunks of the second fixed-point matrix are generated, all occurring within the matrix multiplication apparatus) . Regarding claim 19 , Wu teaches the apparatus of claim 18, wherein the controller circuitry is to cause the floating-point support circuitry to scale the corresponding fixed-point results according to the extreme exponents and a chunk offset to generate the scaled fixed-point results (Figs. 2 and 4, [0063-0077, 0080-0081]: The fixed-point results that are output by the fixed point multiplication module 220 are shifted by a specific amount (i.e., a chunk offset), added together, and then converts the data into floating-point using the maximum exponent value, which generates the scaled fixed-point results) . Regarding claim 20 , Wu teaches the apparatus of claim 18, wherein the controller circuitry is to cause the floating-point support circuitry to partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into at least three chunks (Fig. 5 and [0077-0082]: The third and fourth vectors are divided at least once. Therefore, creating at least two first vectors and two second vectors, resulting in a total amount of four smaller vectors (i.e., chunks)) . Regarding claim 24 , Wu teaches the apparatus of claim 17, wherein the apparatus does not include a two-dimensional grid of floating-point processing elements (Figs. 2 and 7; Subbareddy Fig. 10: The matrix multiplication apparatus does not comprise of floating-point processing elements and neither does the processing core comprise of floating-point processing elements) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-16 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230367548 A1) in view of Subbareddy et al. (US 20210326135 A1) . "Intel Architecture instruction Set Extensions and Future Features Programming Reference" is cited as extrinsic evidence to explain the details of the TDPBF16PS instruction. Regarding claim 1 , Wu teaches an apparatus (Fig. 7: Matrix multiplication apparatus) comprising: a matrix operations accelerator circuit (Fig. 7 and [0084]: Matrix multiplication apparatus accelerates the performance of matrix operations. Therefore, it’s a matrix operations accelerator circuit) comprising: a two-dimensional grid of fixed-point processing elements (Figs. 2 and 7, [0037-0038, 0084-0086]: The apparatus comprises of a two dimensional grid of vector multiplication apparatuses, which performs fixed-point operations. Therefore, the vector multiplication apparatuses are fixed-point processing elements) , floating-point support circuitry coupled to the two-dimensional grid of fixed-point processing elements (Fig. 2 and [0038-0031, 0053. 0057-0073]: The data extraction module 210, inverse fixed point conversion module 260, shift module 240, and the exponent comparison module 230 as the floating-point support circuitry, having functions corresponding to the conversion of floating point to fixed point and vice versa, whereas the exponent comparison module aids in the conversions) , and storage for a first, a second, and a destination two-dimensional floating-point matrices coupled to the floating-point support circuitry (Figs. 6 and 9, [0083, 0095-0096]: The operation apparatus 900 is to be coupled with the matrix multiplication apparatus such that it’s able to perform the method in Fig. 6 for the matrix multiplication apparatus. The first matrix and second matrix are stored in the fourth obtaining unit 910 and the inner product matrix is stored in the fifth obtaining unit 920) ; and the matrix operations accelerator circuit is to: determine, by the floating-point support circuitry, an extreme exponent for each row of the first two-dimensional floating-point matrix and for each column of the second two-dimensional floating-point matrix (Fig. 2 and [0008, 0044, 0053, 0057, 0067]: The data extraction module 210 extracts the exponents of a first and second vector. Where the first vector (i.e., vector A) may be a row vector of a first matrix (i.e., matrix A) and the second vector (i.e., vector B) may be a column vector of a second matrix (i.e., matrix B). The exponent comparison module then adds the exponents for each corresponding vector element (see [0057] for formula) to create a vector of the summation of exponents and identifies the maximum exponent value from the vector of the summation of exponents (identified as ab.e.max in the specification). The maximum exponent value as the extreme exponent of a corresponding row vector of a first matrix and column vector of a second matrix) , generate, by the floating-point support circuitry, a first fixed-point matrix from the first two-dimensional floating-point matrix and a second fixed-point matrix from the second two-dimensional floating-point matrix (Figs. 2 and 7, [0040-0042]: The data extraction module 210 processes each floating point vector element into fixed point data. This process occurs with every vector multiplication apparatus. Therefore, the resulting vectors together would create a first fixed-point matrix and a second fixed-point matrix from the input matrices A and B) , generate, by the two-dimensional grid of fixed-point processing elements, corresponding fixed-point results by a multiplication of fixed-point elements of the first fixed-point matrix by corresponding fixed-point elements of the second fixed-point matrix (Figs. 2 and 7, [0052-0073]: Each vector multiplication apparatus performs fixed point multiplication of the converted row vector and column vector (i.e., the fixed point elements) from the data extraction module 210 using the fixed point multiplication module 220, which results in an output vector of the multiplication result (identified as vector M in the specification). The output vector is then shifted before the products are then added into a singular fixed-point product result. The matrix fixed-point product result, when generated by all vector multiplication apparatuses, as the fixed-point results) , scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents to generate scaled fixed-point results (Figs. 2 and 7, [0074-0076]: The maximum exponent value is used in an equation to generate an exponent data value. Then, the product of the exponent data value and the fixed-point product result is calculated using the inverse fixed point conversion module 260 to generate a scaled fixed-point product result) , generate, by the floating-point support circuitry, a resultant floating-point matrix from the scaled fixed-point results (Figs. 2 and 7, [0075-0076]: Each inverse fixed point conversion module 260 within each vector multiplication apparatus generates a floating-point inner-product calculation result, which would generate a floating-point inner-product result matrix. The inner-product result matrix as the resultant floating-point matrix) , and store the resultant floating-point matrix into the destination two-dimensional floating-point matrix (Figs. 6 and 9, [0083, 0096]: The inner-product matrix result is to be stored in the fifth obtaining unit 920) . Wu does not teach that the apparatus further comprises a hardware processor core coupled to the matrix operations accelerator circuit and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field that identifies the first two-dimensional floating-point matrix, a second field that identifies the second two-dimensional floating-point matrix, and an opcode . Subbareddy teaches a hardware processor core coupled to the matrix operations accelerator circuit (Fig. 10 and [0081-0082]: out-of-order core 402 coupled to a TMUL matrix multiplication unit 207. The core 402 as the hardware processor core and the TMUL matrix multiplication unit as the matrix operations accelerator circuit) and comprising a decoder circuit to decode a single instruction into a decoded single instruction (Figs. 2B and 10, [0029, 0033, 0081-0083]: The core 402 may refer to processor core 52, which would indicate that core 402 includes a decoder circuit to decode instructions. Since the processor core can support AMX instructions, one of these instructions may be a tile matrix multiply instruction, such as TDPBF16PS (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17), which are to be performed by the TMUL matrix multiplication unit 207 through a matrix multiply command output by the core 402) , the single instruction including a first field that identifies the first two-dimensional floating-point matrix (The TDPBF16PS includes a field for a first operand, tmm2, which is a matrix comprising of floating point elements (BF16) (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , a second field that identifies the second two-dimensional floating-point matrix (The TDPBF16PS includes a field for a second operand, tmm3, which is a matrix comprising of floating point elements (BF16) (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , and an opcode (VEX.128.F3.0F38.W0 5C 11:rrr:bbb as the opcode for the TDPBF16PS instruction (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)). It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Wu with the teachings of Subbareddy to have a processor be coupled to an accelerator to handle instruction processing and command the matrix multiplication apparatus of Wu to perform fixed-point matrix multiplication. Separating the instruction processing pipeline with the matrix execution pipeline decreases the overhead of the processor core, which improve the performance of the processing system. Regarding claim 2 , Wu, in view of Subbareddy, teaches the apparatus of claim 1, wherein the opcode further indicates the matrix operations accelerator circuit is to: partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into a plurality of chunks (Wu, Fig. 5 and [0077-0082]: In the current combination, the input vectors (identified as a third and fourth input vector) are first processed normally through the data extraction module 510 (same as data extraction module 210), converting the data elements into fixed-point, before they are partitioned into a plurality of smaller vectors (identified as a plurality of first and second vectors) by the data extraction module. The plurality of smaller vectors as the plurality of chunks comprising of the first fixed-point matrix and second fixed-point matrix) , generate, by the two-dimensional grid of fixed-point processing elements, the corresponding fixed-point results by a multiplication of chunks of the first fixed-point matrix by chunks of the second fixed-point matrix (Wu, Figs. 5 and 7, [0077-0082]: The plurality of smaller vectors are then sent to the multiplication module 520 such that a multiplication of chunks of the first fixed-point matrix and chunks of the second fixed-point matrix are generated, all occurring within the matrix multiplication apparatus) . Regarding claim 3 , Wu, in view of Subbareddy, teaches the apparatus of claim 2, wherein the opcode further indicates the matrix operations accelerator circuit is to scale, by the floating-point support circuitry, the corresponding fixed-point results according to the extreme exponents and a chunk offset to generate the scaled fixed-point results (Figs. 2 and 4, [0063-0077, 0080-0081]: The fixed-point results that are output by the fixed point multiplication module 220 are shifted by a specific amount (i.e., a chunk offset), added together, and then converts the data into floating-point using the maximum exponent value, which generates the scaled fixed-point results) . Regarding claim 4 , Wu, in view of Subbareddy, teaches the apparatus of claim 2, wherein the opcode further indicates the matrix operations accelerator circuit is to partition each element of the first fixed-point matrix and each element of the second fixed-point matrix into at least three chunks (Wu, Fig. 5 and [0077-0082]: In the current combination, the third and fourth vectors are divided at least once. Therefore, creating at least two first vectors and two second vectors, resulting in a total amount of four smaller vectors (i.e., chunks)) . Regarding claim 5 , Wu, in view of Subbareddy, teaches the apparatus of claim 1, wherein the opcode further indicates the matrix operations accelerator circuit is to determine, by the floating-point support circuitry, the extreme exponent for each row of the first two-dimensional floating-point matrix after the first two-dimensional floating-point matrix is loaded into the storage and the extreme exponent for each column of the second two-dimensional floating-point matrix after the second two-dimensional floating-point matrix is loaded into the storage (Wu, Figs. 2, 6, and 9, [0008, 0044, 0053, 0057, 0067, 0083]: The data extraction module 210 extracts the exponents of a first and second vector after they are obtained by the fourth obtaining unit 910) . Wu, in view of Subbareddy, does not teach to determine the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage . However, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of Wu, in view of Subbareddy, to have determined the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage. Given the circuitry of Wu, one of ordinary skill would have recognized that to have the extreme exponents be determined as they are loaded into the storage, they would move the components which calculates the extreme exponents to be located alongside the fourth obtaining unit of Wu. Hence, rearrangement of parts, i.e., rearranging the components to be placed alongside the fourth obtaining unit, is deemed a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(C)). Regarding claim 6 , Wu, in view of Subbareddy, teaches the apparatus of claim 1, wherein the single instruction includes a third field that identifies a third two-dimensional floating-point matrix (The TDPBF16PS includes a field for a third operand, tmm1, which is a matrix comprising of floating point elements (BF16) (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) . Wu, in view of Subbareddy, does not teach that the opcode further indicates the matrix operations accelerator circuit is to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix, wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix . Note that the instruction TDPBF16PS includes an additional field, tmm1, to use as part of an accumulation step at the end of the matrix multiplication process (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17). Subbareddy also teaches to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix (Fig. 10 and [0083]: When executing the instruction TDPBF16PS, the matrix multiplication result of matrices A and B and Matrix C are added together, creating an updated resultant floating-point matrix. The matrix multiplication result as the resultant floating-point matrix. Matrix C as the third two-dimensional floating-point matrix (see “Intel Architecture Instruction Set Extensions and Future Features Programming Reference”, page 3-17)) , wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix (Fig. 10 and [0083]: The updated resultant floating-point matrix is stored back to where Matrix C is stored in the 2D data buffer 416). It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of Wu with the teachings of Subbareddy to have used the inner product matrix located within the fifth obtaining unit of Wu and accumulated it with the floating-point product results, then have the accumulated result be stored in the fifth obtaining unit. An accumulation step at the end of the matrix multiplication process is part of a common process in areas such as AI and machine learning. Therefore, by adding the step as part of the multiplication process rather than having a separate instruction to perform the accumulation part helps reduce the number of instructions performed, which improves the computing system performance. Regarding claims 7 , Wu, in view of Subbareddy, teaches the apparatus of claim 6, wherein the third two-dimensional floating-point matrix is stored in the storage for the destination two-dimensional floating-point matrix (In the current combination, the updated resultant floating-point matrix is stored back in the fifth obtaining unit) . Regarding claim 8 , Wu, in view of Subbareddy, teaches the apparatus of claim 1, wherein the apparatus does not include a two-dimensional grid of floating-point processing elements (Wu, Figs. 2 and 7; Subbareddy Fig. 10: In the current combination, the matrix multiplication apparatus does not comprise of floating-point processing elements and neither does the processing core comprise of floating-point processing elements) . Regarding claims 9-16 , the claims recite a method similar to the apparatus of claims 1-8, respectively . Therefore, the claims are rejected on the same premises. Regarding claim 22 , Wu teaches the apparatus of claim 17, wherein the storage is also for a third two-dimensional floating-point matrix (Figs. 6 and 9, [0083, 0095-0096]: The inner product matrix is stored in the fifth obtaining unit 920. The inner product matrix as the third two-dimensional floating-point matrix) . Wu does not teach that the controller circuitry is to cause the floating-point support circuitry to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix, wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix . Subbareddy teaches to, before the store of the resultant floating-point matrix into the destination two-dimensional floating-point matrix, accumulate each element of the third two-dimensional floating-point matrix with a corresponding element of the resultant floating-point matrix to generate an updated resultant floating-point matrix (Fig. 10 and [0083]: When executing a multiply-accumulate operation, the matrix multiplication result of matrices A and B and the data of Matrix C are added together, creating an updated resultant floating-point matrix. The matrix multiplication result as the resultant floating-point matrix. Matrix C as the third two-dimensional floating-point matrix) , wherein the store is of the updated resultant floating-point matrix into the destination two-dimensional floating-point matrix (Fig. 10 and [0083]: The updated resultant floating-point matrix is stored back to where Matrix C is stored in the 2D data buffer 416). It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Wu with the teachings of Subbareddy to have used the inner product matrix located within the fifth obtaining unit of Wu and accumulated it with the floating-point product results, then have the accumulated result be stored in the fifth obtaining unit. An accumulation step at the end of the matrix multiplication process is part of a common process in areas such as AI and machine learning. Therefore, by adding the step as part of the multiplication process rather than having a separate instruction to perform the accumulation part helps reduce the number of instructions performed, which improves the computing system performance. Regarding claim 23 , Wu, in view of Subbareddy, teaches the apparatus of claim 22, wherein the third two-dimensional floating-point matrix is stored in the storage for the destination two-dimensional floating-point matrix (In the current combination, the updated resultant floating-point matrix is stored back to the fifth obtaining unit) . 07-21-aia AIA Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230367548 A1) . Regarding claim 21 , Wu teaches the apparatus of claim 17, wherein the controller circuitry is to cause the floating-point support circuitry to determine the extreme exponent for each row of the first two-dimensional floating-point matrix after the first two-dimensional floating-point matrix is loaded into the storage and the extreme exponent for each column of the second two-dimensional floating-point matrix after the second two-dimensional floating-point matrix is loaded into the storage (Figs. 2, 6, and 9, [0008, 0044, 0053, 0057, 0067, 0083]: The data extraction module 210 extracts the exponents of a first and second vector after they are obtained by the fourth obtaining unit 910) . Wu does not teach to determine the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage . However, it would have been obvious to one of ordinary skill in the art before the effective filing date to have modified the teachings of Wu to have determined the extreme exponent of the first two-dimensional floating-point matrix and second two-dimensional floating-point matrix as the matrices are loaded into the storage. Given the circuitry of Wu, one of ordinary skill would have recognized that to have the extreme exponents be determined as they are loaded into the storage, they would move the components which calculates the extreme exponents to be located alongside the fourth obtaining unit of Wu. Hence, rearrangement of parts, i.e., rearranging the components to be placed alongside the fourth obtaining unit, is deemed a routine expedient, not a patentable distinction (MPEP 2144.04(VI)(C)) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230334117 A1: Ferrere teaches a method to calculate dot product. US 20230244442 A1: Lee et al. teaches a multiplication and accumulate operations performed on data converted between fixed-point and floating-point. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.A./Examiner, Art Unit 2183 /JYOTI MEHTA/ Supervisory Patent Examiner, Art Unit 2183 Application/Control Number: 18/149,045 Page 2 Art Unit: 2183 Application/Control Number: 18/149,045 Page 3 Art Unit: 2183 Application/Control Number: 18/149,045 Page 4 Art Unit: 2183 Application/Control Number: 18/149,045 Page 5 Art Unit: 2183 Application/Control Number: 18/149,045 Page 6 Art Unit: 2183 Application/Control Number: 18/149,045 Page 7 Art Unit: 2183 Application/Control Number: 18/149,045 Page 8 Art Unit: 2183 Application/Control Number: 18/149,045 Page 9 Art Unit: 2183 Application/Control Number: 18/149,045 Page 10 Art Unit: 2183 Application/Control Number: 18/149,045 Page 11 Art Unit: 2183 Application/Control Number: 18/149,045 Page 12 Art Unit: 2183 Application/Control Number: 18/149,045 Page 13 Art Unit: 2183 Application/Control Number: 18/149,045 Page 14 Art Unit: 2183 Application/Control Number: 18/149,045 Page 15 Art Unit: 2183 Application/Control Number: 18/149,045 Page 16 Art Unit: 2183 Application/Control Number: 18/149,045 Page 17 Art Unit: 2183 Application/Control Number: 18/149,045 Page 18 Art Unit: 2183 Application/Control Number: 18/149,045 Page 19 Art Unit: 2183 Application/Control Number: 18/149,045 Page 20 Art Unit: 2183 Application/Control Number: 18/149,045 Page 21 Art Unit: 2183 Application/Control Number: 18/149,045 Page 22 Art Unit: 2183 Application/Control Number: 18/149,045 Page 23 Art Unit: 2183 Application/Control Number: 18/149,045 Page 24 Art Unit: 2183 Application/Control Number: 18/149,045 Page 25 Art Unit: 2183 Application/Control Number: 18/149,045 Page 26 Art Unit: 2183 Application/Control Number: 18/149,045 Page 27 Art Unit: 2183 Application/Control Number: 18/149,045 Page 28 Art Unit: 2183 Application/Control Number: 18/149,045 Page 29 Art Unit: 2183 Application/Control Number: 18/149,045 Page 30 Art Unit: 2183 Application/Control Number: 18/149,045 Page 31 Art Unit: 2183 Application/Control Number: 18/149,045 Page 32 Art Unit: 2183 Application/Control Number: 18/149,045 Page 33 Art Unit: 2183 Application/Control Number: 18/149,045 Page 34 Art Unit: 2183 Application/Control Number: 18/149,045 Page 35 Art Unit: 2183 Application/Control Number: 18/149,045 Page 36 Art Unit: 2183 Application/Control Number: 18/149,045 Page 37 Art Unit: 2183 Application/Control Number: 18/149,045 Page 38 Art Unit: 2183 Application/Control Number: 18/149,045 Page 39 Art Unit: 2183 Application/Control Number: 18/149,045 Page 40 Art Unit: 2183 Application/Control Number: 18/149,045 Page 41 Art Unit: 2183 Application/Control Number: 18/149,045 Page 42 Art Unit: 2183 Application/Control Number: 18/149,045 Page 43 Art Unit: 2183 Application/Control Number: 18/149,045 Page 44 Art Unit: 2183 Application/Control Number: 18/149,045 Page 45 Art Unit: 2183 Application/Control Number: 18/149,045 Page 46 Art Unit: 2183 Application/Control Number: 18/149,045 Page 47 Art Unit: 2183 Application/Control Number: 18/149,045 Page 48 Art Unit: 2183 Application/Control Number: 18/149,045 Page 49 Art Unit: 2183 Application/Control Number: 18/149,045 Page 50 Art Unit: 2183 Application/Control Number: 18/149,045 Page 51 Art Unit: 2183 Application/Control Number: 18/149,045 Page 52 Art Unit: 2183 Application/Control Number: 18/149,045 Page 53 Art Unit: 2183 Application/Control Number: 18/149,045 Page 54 Art Unit: 2183 Application/Control Number: 18/149,045 Page 55 Art Unit: 2183 Application/Control Number: 18/149,045 Page 56 Art Unit: 2183 Application/Control Number: 18/149,045 Page 57 Art Unit: 2183 Application/Control Number: 18/149,045 Page 58 Art Unit: 2183 Application/Control Number: 18/149,045 Page 59 Art Unit: 2183
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