Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment to claims 1, 2, 5 and 18 submitted on March 2, 2026 is acknowledged and has since been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dewey (US 20200105751 A1).
Regarding Claim 1, Dewey teaches a semiconductor device (see Fig. 2a) comprising:
a lower pattern (211) extending in a first direction (horizontal direction as shown in Fig. 2a);
a gate electrode (201 and 203) on the lower pattern and extending in a second direction (see [0017] which describes a conventional gate-all-around configuration, wherein the gate electrode extends perpendicular to the channel regions);
a lower channel pattern (205) on the lower pattern and comprising at least one lower sheet pattern (shown Fig. 2a, see also [0018] describing the channels as nanoribbons); and
an upper channel pattern (202) on the lower channel pattern and comprising at least one upper sheet pattern (shown Fig. 2a), wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction (vertical direction shown Fig. 2a), the gate electrode comprises a lower gate electrode (203) through which the lower sheet pattern passes (shown Fig. 2a) and an upper gate electrode (201) through which the upper sheet pattern passes (shown Figs. 2a and 5a), the lower gate electrode comprises a lower conductive liner layer (an outermost work function layer, see also [0031]) defining a lower liner trench (see described in [0031], wherein an “outer work function layer and/or barrier layer” would be interpreted as layers in which the outermost layer lines the lower gate trenches during nanosheet FET processing, thus defining a “lower liner trench”) and a lower filling layer (a central metal plug portion, see also [0031]) filling the lower liner trench (as described in [0031]); and
a bottom surface (bottommost surface of upper gate electrode 201) of the upper gate electrode is entirely higher than an upper surface of the lower gate electrode (shown Fig. 2a).
Regarding Claim 2, Dewey teaches the semiconductor device of claim 1, wherein the upper gate electrode comprises an upper conductive liner layer (an outermost work function layer, see also [0031]) defining an upper liner trench (see described in [0031]) and an upper conductive filling layer (a central metal plug portion, see also [0031]) filling the upper liner trench; and
a bottom surface of the upper gate electrode is defined by the upper conductive liner layer (wherein an outermost work function layer would define a bottom surface of the upper gate electrode as drawn to Fig. 2a).
Regarding Claim 3, Dewey teaches the semiconductor device of claim 1, wherein the gate electrode further comprises an insertion pattern (interpreted as an intermediate work function layer described in [0031]) extending along the upper surface of the lower gate electrode, and
the insertion pattern has one of a conductive material or an insulating material (see [0031] which describes conductive work function layers or insulating barrier layers).
Regarding Claim 4, Dewey teaches the semiconductor device of claim 1, further comprising:
a dummy sheet pattern (207) between the lower channel pattern and the upper channel pattern, wherein the dummy sheet pattern includes an insulating material (see [0028]).
Claim 5 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rachmady (US 20230073078 A1).
Regarding Claim 5, Rachmady teaches a semiconductor device (see Fig. 10) comprising:
a first lower pattern (left “lower devices” in Fig. 1a, including channel regions 101a and lower source region 109) extending in a first direction (extending along the x-dimension, see also [0029]);
a second lower pattern (right “lower devices” in Fig. 1a, including channel regions 101a and lower drain region 110) extending in the first direction;
a first gate electrode (116 and 122) on the first lower pattern and extending in a second direction (y-dimension, extending perpendicular to the semiconductor bodies, see also cross-sectional view of Fig. 3a);
a second gate electrode (118 and 124) on the second lower pattern and extending in the second direction;
a first lower channel pattern (101a, corresponding to the left “lower devices) on the first lower pattern and comprising at least one first lower sheet pattern (a bottommost nanosheet channel 101a, shown Fig. 1a);
a first upper channel pattern (channel regions 101a on left “upper devices” shown Fig. 1a) on the first lower channel pattern and comprising at least one first upper sheet pattern (a bottommost nanosheet channel of the upper channel pattern);
a first dummy sheet pattern (101c, see also Fig. 3a, [0042] and [0046] which describes a native oxide 101c being formed between the lower devices and upper devices) between the first lower channel pattern and the first upper channel pattern (shown Fig. 3a);
a second lower channel pattern (channel regions 101a on right “lower devices” shown Fig. 1a) on the second lower pattern and comprising at least one second lower sheet pattern (bottommost nanosheet channel 101a of the right “lower devices”);
a second upper channel pattern (channel regions 101a on right “upper devices” shown Fig. 1a) on the second lower channel pattern and comprising at least one second upper sheet pattern (bottommost nanosheet channel of right “upper devices”);
a second dummy sheet pattern (101c) between the second lower channel pattern and the second upper channel pattern (shown Fig. 3a see also [0042] which cites that “an insulator layer 101c may also be substituted for the mid-layer 101b”);
a first gate insulating layer (a gate dielectric “shown with thick bolded lines”) between the first lower sheet pattern and the first gate electrode and between the first upper sheet pattern and the first gate electrode (shown Fig. 1a); and
a second gate insulating layer (a gate dielectric “shown with thick bolded lines”) between the second lower sheet pattern and the second gate electrode and between the second upper sheet pattern and the second gate electrode (shown Fig. 1a),
wherein the first gate electrode comprises a first lower gate electrode (116) through which the first lower sheet pattern passes (shown Fig. 1a), a first upper gate electrode (122) through which the first upper sheet pattern passes (shown Fig. 1a), and a first insertion pattern (121) between the first lower gate electrode and the first upper gate electrode (shown Fig. 1a),
the second gate electrode comprises a second lower gate electrode (118)through which the second lower sheet pattern passes (shown Fig. 1a), a second upper gate electrode (124) through which the second upper sheet pattern passes (shown Fig. 1a), and a second insertion pattern (121) between the second lower gate electrode and the second upper gate electrode (shown Fig. 1a),
the first insertion pattern is between an upper surface of the first lower channel pattern and a bottom surface of the first upper channel pattern (shown Fig. 1a),
the second insertion pattern is between an upper surface of the second lower channel pattern and a bottom surface of the second upper channel pattern (shown Fig. 1a), and
the first insertion pattern includes a same material as the second insertion pattern (see [0030] which describes isolation structure 121 as “silicon oxycarbide”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6-7, 9, 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady (US 20230073078 A1) in further view of Chen (US 20190318967 A1).
Regarding Claim 6, Rachmady teaches the semiconductor device of claim 5, wherein the first gate insulating layer includes a same material as the second gate insulating layer (see [0033] which describes that upper and lower gate structures may be materially the same), the first gate insulating layer surrounding the first lower sheet pattern and the second gate insulating layer surrounding the second lower sheet pattern includes a lower doping material (see [0032] which describes that the gate dielectrics “may include concentration grading (increasing or decreasing) of one or more materials therein”).
However, Rachmady does not explicitly teach the first gate insulating layer having a first lower doping material and the second gate insulating layer having a second lower doping materially different than the first lower doping material.
Chen teaches a semiconductor device (shown Fig. 2) comprising a plurality of transistor devices (310, 320 and 330, corresponding to different device regions, see also Fig. 9), wherein each gate dielectric may have varying levels of dopant species to tune threshold voltages of each corresponding transistor (see also [0012] and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to accommodate different doping materials within different gate insulating layers to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 7, Rachmady as modified by Chen teaches the semiconductor device of claim 6. Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032] wherein the upper gate electrode may match the configuration of the lower gate electrode).
Rachmady does not explicitly teach the first upper conductive liner layer having a material different from that of the second upper conductive liner layer.
However, Chen further suggests implementing different materials as work-function tuning layers to tune threshold voltages of respective transistor devices (see Chen: [0012] and [0053]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to implement different material work-function tuning layers (i.e., conductive liner layers) to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 9, Rachmady teaches the semiconductor device of claim 5, wherein the first gate insulating layer surrounding the first upper sheet pattern and the second gate insulating layer surrounding the second upper sheet pattern includes a doping material (see [0032] which describes that the gate dielectrics “may include concentration grading (increasing or decreasing) of one or more materials therein”).
However, Rachmady does not explicitly teach the first gate insulating layer having a first upper doping material and the second gate insulating layer having a second upper doping material different than the first upper doping material.
Chen teaches a semiconductor device (shown Fig. 2) comprising a plurality of transistor devices (310, 320 and 330, corresponding to different device regions, see also Fig. 9), wherein each gate dielectric may have varying levels of dopant species to tune threshold voltages of each corresponding transistor (see also [0012] and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to accommodate different doping materials within different gate insulating layers to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 14, Rachmady teaches the semiconductor device of Claim 5. Rachmady further teaches that the first lower gate electrode comprises a first lower conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first lower sheet pattern, the second lower gate electrode comprises a second lower conductive liner layer surrounding the second lower sheet pattern (see [0032]).
Rachmady does not explicitly teach the first lower conductive liner layer having a material different from that of the second lower conductive liner layer.
However, Chen further suggests implementing different materials as work-function tuning layers to tune threshold voltages of respective transistor devices (see Chen: [0012] and [0053]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to implement different material work-function tuning layers (i.e., conductive liner layers) to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 15, Rachmady as modified by Chen teaches the semiconductor device of claim 14, Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]).
Chen further suggests implementing different materials as work-function tuning layers to tune threshold voltages of respective transistor devices (see Chen: [0012] and [0053]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to implement different material work-function tuning layers (i.e., conductive liner layers) to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 17, Rachmady as modified by Chen teaches the semiconductor device of claim 14. Rachmady further teaches that the first gate insulating layer surrounding the first upper sheet pattern and the second gate insulating layer surrounding the second upper sheet pattern includes a doping material (see [0032] which describes that the gate dielectrics “may include concentration grading (increasing or decreasing) of one or more materials therein”).
Chen further teaches a semiconductor device (shown Fig. 2) comprising a plurality of transistor devices (310, 320 and 330, corresponding to different device regions, see also Fig. 9), wherein each gate dielectric may have varying levels of dopant species to tune threshold voltages of each corresponding transistor (see also [0012] and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to accommodate different doping materials within different gate insulating layers to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady (US 20230073078 A1) in further view of Tewg (Influence of a 5 Å Tantalum Nitride Interface Layer on Dielectric Properties of Zirconium-Doped Tantalum Oxide High-k Films, 2005) and Chen (US 20190318967 A1).
Regarding Claim 18, Rachmady teaches a semiconductor device (see Fig. 10) comprising:
a first lower pattern (left “lower devices” in Fig. 1a, including channel regions 101a and lower source region 109) extending in a first direction (extending along the x-dimension, see also [0029]);
a second lower pattern (right “lower devices” in Fig. 1a, including channel regions 101a and lower drain region 110) extending in the first direction;
a first gate electrode (116 and 122) on the first lower pattern and extending in a second direction (y-dimension, extending perpendicular to the semiconductor bodies, see also cross-sectional view of Fig. 3a);
a second gate electrode (118 and 124) on the second lower pattern and extending in the second direction;
a first lower channel pattern (101a, corresponding to the left “lower devices) on the first lower pattern and comprising at least one first lower sheet pattern (a bottommost nanosheet channel 101a, shown Fig. 1a);
a first upper channel pattern (channel regions 101a on left “upper devices” shown Fig. 1a) on the first lower channel pattern and comprising at least one first upper sheet pattern (a bottommost nanosheet channel of the upper channel pattern);
a second lower channel pattern (channel regions 101a on right “lower devices” shown Fig. 1a) on the second lower pattern and comprising at least one second lower sheet pattern (bottommost nanosheet channel 101a of the right “lower devices”);
a second upper channel pattern (channel regions 101a on right “upper devices” shown Fig. 1a) on the second lower channel pattern and comprising at least one second upper sheet pattern (bottommost nanosheet channel of right “upper devices”);
a first gate insulating layer (a gate dielectric “shown with thick bolded lines”) between the first lower sheet pattern and the first gate electrode and between the first upper sheet pattern and the first gate electrode (shown Fig. 1a); and
a second gate insulating layer (a gate dielectric “shown with thick bolded lines”) between the second lower sheet pattern and the second gate electrode and between the second upper sheet pattern and the second gate electrode (shown Fig. 1a),
wherein the first gate electrode comprises a first lower gate electrode (116) through which the first lower sheet pattern passes (shown Fig. 1a), a first upper gate electrode (122) through which the first upper sheet pattern passes (shown Fig. 1a), and a first insertion pattern (121) between the first lower gate electrode and the first upper gate electrode (shown Fig. 1a),
the second gate electrode comprises a second lower gate electrode (118)through which the second lower sheet pattern passes (shown Fig. 1a), a second upper gate electrode (124) through which the second upper sheet pattern passes (shown Fig. 1a),
the first lower gate electrode comprises a first lower conductive liner layer defining a first lower liner trench and a first lower filling layer filling the first lower liner trench (see [0032] which describes a plurality of outer work function layers or barrier layers implemented with a central metal plug portion, wherein the plug portion would be interpreted as a filling layer within a portion of a workfunction/barrier layer which lines a wall of the gate trench during processing),
the second lower gate electrode comprises a second lower conductive liner layer defining a second lower liner trench and a second lower filling layer filling the second lower liner trench (formed similarly to the first lower conductive liner layer and first lower filling layer),
an entire bottom surface of the first upper gate electrode is between an upper surface of the first lower channel pattern and a bottom surface of the first upper channel pattern (shown Fig. 1a),
an entire bottom surface of the second upper gate electrode is between an upper surface of the second lower channel pattern and a bottom surface of the second upper channel pattern (shown Fig. 1a),
the first lower conductive liner layer includes a same material as the second lower conductive liner layer (see [0032-0033]),
the first gate insulating layer includes a same material as the second gate insulating layer (see [0032-0033]), the first gate insulating layer surrounding the first lower sheet pattern includes a first lower doping material (see [0032] which describes that the gate dielectrics may “include concentration grading (increasing or decreasing) of one or more materials therein”),
the first insertion pattern is in contact with the first lower gate electrode and the first upper gate electrode (shown Fig. 1a) and “may include any number of dielectrics that can be selectively deposited” (see [0030]).
However, Rachmady does not explicitly teach the first insertion pattern including a conductive material.
Tewg teaches a high-k dielectric (a TaOx film, see “Abstract”) wherein dielectric properties of a metal-oxide-semiconductor may be improved by including a conductive material (i.e., a Hf or Zr dopant, which show “improvement of both interface and bulk properties” as well as an increased “amorphous-to-crystalline transition temperature”).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the dielectric isolation layer of Rachmady to include a conductive material (i.e., a Hf or Zr dopant) as this would advantageously improve interface and bulk material properties of the isolation material and improve dielectric characteristics between the two gate electrodes of Rachmady.
Rachmady as modified by Tewg does not explicitly teach the second gate insulating layer surrounding the second lower sheet pattern including a second lower doping material different from the first lower doping material.
Chen teaches a semiconductor device (shown Fig. 2) comprising a plurality of transistor devices (310, 320 and 330, corresponding to different device regions, see also Fig. 9), wherein each gate dielectric may have varying levels of dopant species to tune threshold voltages of each corresponding transistor (see also [0012] and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to accommodate different doping materials within different gate insulating layers to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 19, Rachmady as modified by Tewg and Chen teaches the semiconductor device of claim 18.
Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]).
Rachmady does not explicitly teach the first upper conductive liner layer having a material different from that of the second upper conductive liner layer.
However, Chen further suggests implementing different materials as work-function tuning layers to tune threshold voltages of respective transistor devices (see Chen: [0012] and [0053]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to implement different material work-function tuning layers (i.e., conductive liner layers) to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Claim(s) 8, 10-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rachmady (US 20230073078 A1) in further view of Chen (US 20190318967 A1) and Zhang (US 10700064 B1).
Regarding Claim 8, Rachmady as modified by Chen teaches the semiconductor device of claim 6. Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]), the first upper conductive liner layer includes a same material as the second upper conductive liner layer (see [0032] and [0033]).
Chen further suggests implementing different methods to tune threshold voltages of respective transistor devices via modifying the gate dielectric layers (see Chen: [0012] and [0053]).
Rachmady and Chen do not explicitly teach that a thickness of the first upper conductive liner layer is different from a thickness of the second upper conductive liner layer.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Zhang shows that thickness of a gate dielectric layer is a result-effective variable because it reveals that varying thickness of the gate dielectric layer further tunes an effective threshold voltage (see also Zhang: Col. 1, Ln. 50-52).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of each gate dielectric layer to further optimize a threshold voltage of each transistor on the semiconductor device as applied to Rachmady and Chen. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Regarding Claim 10, Rachmady teaches the device of claim 5. Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]), the first upper conductive liner layer includes a same material as the second upper conductive liner layer (see [0032] and [0033]).
Chen further suggests implementing different methods to tune threshold voltages of respective transistor devices via modifying the gate dielectric layers (see Chen: [0012] and [0053]).
Rachmady and Chen do not explicitly teach that a thickness of the first upper conductive liner layer is different from a thickness of the second upper conductive liner layer.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Zhang shows that thickness of a gate dielectric layer is a result-effective variable because it reveals that varying thickness of the gate dielectric layer further tunes an effective threshold voltage (see also Zhang: Col. 1, Ln. 50-52).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of each gate dielectric layer to further optimize a threshold voltage of each transistor on the semiconductor device as applied to Rachmady. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Regarding Claim 11, Rachmady as modified by Chen and Zhang teaches the semiconductor device of claim 10.
Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]).
Chen further suggests implementing different materials as work-function tuning layers to tune threshold voltages of respective transistor devices (see Chen: [0012] and [0053]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to implement different material work-function tuning layers (i.e., conductive liner layers) to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 12, Rachmady as modified by Chen and Zhang teaches semiconductor device of claim 10, wherein the first upper gate electrode comprises a first upper conductive liner layer surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern, the first upper conductive liner layer includes a same material as the second upper conductive liner layer.
As applied by Zhang in claim 10, it would further be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to optimize a thickness of the first upper conductive liner layer and a thickness of the second upper conductive liner layer such that a thickness of the first upper conductive liner layer is different than a thickness of the second upper conductive liner layer as this would further enable tuning of the effective threshold voltage of different transistor devices on the semiconductor device.
Regarding Claim 13, Rachmady as modified by Chen and Zhang teaches the semiconductor device of claim 10.
Rachmady further teaches that the first gate insulating layer surrounding the first upper sheet pattern and the second gate insulating layer surrounding the second upper sheet pattern includes a doping material (see [0032] which teaches a concentration grading of one or more materials therein).
Chen further teaches a semiconductor device (shown Fig. 2) comprising a plurality of transistor devices (310, 320 and 330, corresponding to different device regions, see also Fig. 9), wherein each gate dielectric may have varying levels of dopant species to tune threshold voltages of each corresponding transistor (see also [0012] and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to configure the device of Rachmady to accommodate different doping materials within different gate insulating layers to aid in tuning the effective threshold voltage of different transistors within the semiconductor device without adversely impacting spacing between gates (see also Chen: [0012]).
Regarding Claim 16, Rachmady as modified by Chen teaches the semiconductor device of Claim 14. Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]), the first upper conductive liner layer includes a same material as the second upper conductive liner layer (see [0032] and [0033]).
Chen further suggests implementing different methods to tune threshold voltages of respective transistor devices via modifying the gate dielectric layers (see Chen: [0012] and [0053]).
Rachmady and Chen do not explicitly teach that a thickness of the first upper conductive liner layer is different from a thickness of the second upper conductive liner layer.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Zhang shows that thickness of a gate dielectric layer is a result-effective variable because it reveals that varying thickness of the gate dielectric layer further tunes an effective threshold voltage (see also Zhang: Col. 1, Ln. 50-52).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of each gate dielectric layer to further optimize a threshold voltage of each transistor on the semiconductor device as applied to Rachmady and Chen. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady (US 20230073078 A1) in view of Tewg (Influence of a 5 Å Tantalum Nitride Interface Layer on Dielectric Properties of Zirconium-Doped Tantalum Oxide High-k Films, 2005) and Chen (US 20190318967 A1) and further in view of Zhang (US 10700064 B1).
Regarding Claim 20, Rachmady as modified by Tewg and Chen teaches the device of Claim 18. Rachmady further teaches that the first upper gate electrode comprises a first upper conductive liner layer (see [0032] which describes a plurality of outer work function layers implemented with a central metal plug portion) surrounding the first upper sheet pattern, the second upper gate electrode comprises a second upper conductive liner layer surrounding the second upper sheet pattern (see [0032]), the first upper conductive liner layer includes a same material as the second upper conductive liner layer (see [0032] and [0033]).
Chen further suggests implementing different methods to tune threshold voltages of respective transistor devices via modifying the gate dielectric layers (see Chen: [0012] and [0053]).
Rachmady and Chen do not explicitly teach that a thickness of the first upper conductive liner layer is different from a thickness of the second upper conductive liner layer.
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Zhang shows that thickness of a gate dielectric layer is a result-effective variable because it reveals that varying thickness of the gate dielectric layer further tunes an effective threshold voltage (see also Zhang: Col. 1, Ln. 50-52).
A person having ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal thickness of each gate dielectric layer to further optimize a threshold voltage of each transistor on the semiconductor device as applied to Rachmady and Chen. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Response to Arguments
Applicant's arguments filed March 2, 2026 regarding claim 1 have been fully considered but they are not persuasive.
Applicant argues that the an outermost work function layer and central metal plug portion fails to disclose “any positional relationship between the ‘central metal plug portion’ and the ‘outermost work function layer,’ much less that Dewey’s ‘outermost work function layer’ defines a trench or ‘central metal plug portion’ fills such a trench. Examiner respectfully disagrees, and notes that an “outer work function layer and/or barrier layer” would be interpreted as layers in which the outermost layer lines the lower gate trenches during nanosheet FET processing (see also processing steps of Rachmady, US 2023007308 A1) thus defining a “lower liner trench”) and a lower filling layer (a central metal plug portion, see also [0031]) filling the lower liner trench (as described in [0031], wherein a “metal plug” would fill the remaining opening to form the final gate structure)
Applicant’s arguments with respect to claim(s) 5 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.B./ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights