Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 14, 2026 has been entered.
Response to Amendment
The amendments to claims 1, 5 and 18 submitted on July 14, 2026 are acknowledged and have since been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lilak (US 20230090092 A1).
Regarding Claim 1, Lilak teaches a semiconductor device (shown Fig. 12) comprising:
a lower pattern (a “first semiconductor body”, see [0008]) extending in a first direction (horizontal direction shown in Fig. 12);
a gate electrode (112 and 113) on the lower pattern and extending in a second direction (horizontal direction of Fig. 1f, perpendicular to the first direction);
a lower channel pattern (100) on the lower pattern and comprising a plurality of lower sheet patterns pattern (shown Fig. 12); and
an upper channel pattern (101) on the lower channel pattern and comprising at least one upper sheet pattern,
wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction (vertical direction, shown Fig. 12),
the gate electrode comprises a lower gate electrode (112) through which at least one lower sheet pattern of the plurality of lower sheet patterns passes (see Figs. 1f and 12) and an upper gate electrode (113) through which the upper sheet pattern passes (see Figs. 1f and 12),
the lower gate electrode comprises a lower conductive liner layer (116, shown Fig. 1f) defining a lower liner trench (shown Fig. 7a) and a lower filling layer (112, shown Fig. 7a) filling the lower liner trench, wherein the lower conductive liner layer is disposed in a space between adjacent lower sheet patterns of the plurality of lower sheet patterns (shown Fig. 1f), and the lower filling layer is not disposed in the space between the adjacent lower sheet patterns (shown Fig. 1f), and
a bottom surface of the upper gate electrode is entirely higher than an upper surface of the lower gate electrode (shown Figs. 1f and 12).
Regarding Claim 2, Lilak teaches the semiconductor device of claim 1, wherein the upper gate electrode comprises an upper conductive liner layer (117) defining an upper liner trench (shown Fig. 10) and an upper conductive filling layer (113) filling the upper liner trench; and
a bottom surface of the upper gate electrode is defined by the upper conductive liner layer (shown Fig.1f).
Regarding Claim 4, Lilak teaches the semiconductor device of claim 1, further comprising:
a dummy sheet pattern (119) between the lower channel pattern and the upper channel pattern, wherein the dummy sheet pattern includes an insulating material (see [0020]).
Allowable Subject Matter
Claims 5-20 are allowed.
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 3, Lilak teaches the semiconductor device of claim 1, wherein an insulation material (119) is present between the upper gate electrode and lower gate electrode but does not explicitly teach wherein the gate electrode further comprises an insertion pattern extending along the upper surface of the lower gate electrode, and
the insertion pattern has one of a conductive material or an insulating material.
Bae (US 20220059533 A1) teaches a semiconductor device wherein a gate structure comprises two laterally adjacent gates (120, 220) further comprising an insertion pattern (123, 223) to control a work function and prevent diffusion different work-function layers (see Bae: [0093]).
The prior art does not explicitly teach or suggest in any combination a gate electrode comprising an insertion pattern between an upper gate electrode and lower gate electrode without teaching away from limitations of claim 1.
As such, claim 3 would be patentable if rewritten in independent form to include all limitations of base claim 1.
Regarding Claims 5 and 18, Rachmady (US 0230073078 A1) being the most relevant prior art of record teaches a semiconductor device (see Fig. 10) comprising:
a first lower pattern (left “lower devices” in Fig. 1a, including channel regions 101a and lower source region 109) extending in a first direction (extending along the x-dimension, see also [0029]);
a second lower pattern (right “lower devices” in Fig. 1a, including channel regions 101a and lower drain region 110) extending in the first direction;
a first gate electrode (116 and 122) on the first lower pattern and extending in a second direction (y-dimension, extending perpendicular to the semiconductor bodies, see also cross-sectional view of Fig. 3a);
a second gate electrode (118 and 124) on the second lower pattern and extending in the second direction;
a first lower channel pattern (101a, corresponding to the left “lower devices) on the first lower pattern and comprising at least one first lower sheet pattern (a bottommost nanosheet channel 101a, shown Fig. 1a);
a first upper channel pattern (channel regions 101a on left “upper devices” shown Fig. 1a) on the first lower channel pattern and comprising at least one first upper sheet pattern (a bottommost nanosheet channel of the upper channel pattern);
a second lower channel pattern (channel regions 101a on right “lower devices” shown Fig. 1a) on the second lower pattern and comprising at least one second lower sheet pattern (bottommost nanosheet channel 101a of the right “lower devices”);
a second upper channel pattern (channel regions 101a on right “upper devices” shown Fig. 1a) on the second lower channel pattern and comprising at least one second upper sheet pattern (bottommost nanosheet channel of right “upper devices”);
a first gate insulating layer (a gate dielectric “shown with thick bolded lines”) between the first lower sheet pattern and the first gate electrode and between the first upper sheet pattern and the first gate electrode (shown Fig. 1a); and
a second gate insulating layer (a gate dielectric “shown with thick bolded lines”) between the second lower sheet pattern and the second gate electrode and between the second upper sheet pattern and the second gate electrode (shown Fig. 1a),
wherein the first gate electrode comprises a first lower gate electrode (116) through which the first lower sheet pattern passes (shown Fig. 1a), a first upper gate electrode (122) through which the first upper sheet pattern passes (shown Fig. 1a),
the second gate electrode comprises a second lower gate electrode (118)through which the second lower sheet pattern passes (shown Fig. 1a), a second upper gate electrode (124) through which the second upper sheet pattern passes (shown Fig. 1a),
the first lower gate electrode comprises a first lower conductive liner layer defining a first lower liner trench and a first lower filling layer filling the first lower liner trench (see [0032] which describes a plurality of outer work function layers or barrier layers implemented with a central metal plug portion, wherein the plug portion would be interpreted as a filling layer within a portion of a workfunction/barrier layer which lines a wall of the gate trench during processing),
the second lower gate electrode comprises a second lower conductive liner layer defining a second lower liner trench and a second lower filling layer filling the second lower liner trench (formed similarly to the first lower conductive liner layer and first lower filling layer),
an entire bottom surface of the first upper gate electrode is between an upper surface of the first lower channel pattern and a bottom surface of the first upper channel pattern (shown Fig. 1a),
an entire bottom surface of the second upper gate electrode is between an upper surface of the second lower channel pattern and a bottom surface of the second upper channel pattern (shown Fig. 1a),
the first lower conductive liner layer includes a same material as the second lower conductive liner layer (see [0032-0033]),
the first gate insulating layer includes a same material as the second gate insulating layer (see [0032-0033]), the first gate insulating layer surrounding the first lower sheet pattern includes a first lower doping material (see [0032] which describes that the gate dielectrics may “include concentration grading (increasing or decreasing) of one or more materials therein”).
Rachmady further teaches isolation structures (121) between upper gate electrodes and lower gate electrodes (shown Fig. 1a).
However, Rachmady does not explicitly teach the dummy sheet patterns passing through respective first and second gate electrodes as cited in claim 5 or the first gate electrode comprising a first insertion pattern including a conductive material or the second gate electrode comprising a second insertion pattern between the second lower gate electrode and second upper gate electrode wherein the first insertion pattern electrically connects the first lower gate electrode to the first upper gate electrode.
Bae (US 20220059533 A1) teaches a semiconductor device wherein a gate structure comprises two laterally adjacent gates (120, 220) further comprising an insertion pattern (123, 223) to control a work function and prevent diffusion different work-function layers (see Bae: [0093]).
The prior art does not explicitly teach or suggest in any combination a gate electrode comprising an insertion pattern between an upper gate electrode and lower gate electrode or dummy sheet patterns disposed to pass through the first gate electrode and second gate electrode without teaching away from other structural limitations described in claims 5 and 18.
As such, claims 5 and 18 are deemed patentable over the prior art. Claims 6-17 and 19-20 are further deemed patentable as they require all limitations of claims 5 and 18 respectively.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.P.B./ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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