Office Action Predictor
Last updated: April 15, 2026
Application No. 18/149,700

METHODS FOR FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A DIPOLE LAYER

Final Rejection §103
Filed
Jan 04, 2023
Examiner
ROLLAND, ALEX A
Art Unit
1759
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Asm Ip Holding B.V.
OA Round
2 (Final)
46%
Grant Probability
Moderate
3-4
OA Rounds
3y 9m
To Grant
60%
With Interview

Examiner Intelligence

Grants 46% of resolved cases
46%
Career Allow Rate
271 granted / 585 resolved
-18.7% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
53 currently pending
Career history
638
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
61.3%
+21.3% vs TC avg
§102
12.3%
-27.7% vs TC avg
§112
24.1%
-15.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 585 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/25/25. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 6, 8-9, 11-15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2017/0179252) in view of Guha (US 2009/0302370). Claims 1, 4, 12: Tang teaches a method for manufacturing a transistor [0003] comprising a substrate [0019], gate dielectric layer [0020], dipole layer [0021], and gate electrode [0023]. The dipole layer is lanthanum nitride [0021] and is deposited by ALD from a lanthanum precursor and hydrazine [0028]. Tang does not teach gallium nitride as the dipole layer. However, Guha teaches a method for manufacturing a transistor comprising a substrate, high-k dielectric layer, dipole layer, and gate electrode (abstract). The dipole layer is used to tune the transistor by way of voltage shift [0024] and can be selected from several oxides and nitrides (Table 1; [0030]). Table 1 includes lanthanum and gallium and the nitride versions are expected to behave similar to the listed oxides (Id.). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to practice the method of Tang and substitute the lanthanum nitride dipole layer with a gallium nitride dipole layer (i.e., substituting the lanthanum precursor for a gallium precursor). Guha teaches both materials are known for use as a dipole layer and the material is chosen based on the desired voltage shift. Claim 6: Tang teaches the ALD process is at elevated temperature [0028]. Claims 8-9, 15: Tang teaches the thickness of the dipole layer modulates the threshold voltage of the transistor to a predetermined value such as 1-6 Ang [0021]. Guha teaches of 0.3 to 2 nm [0024]. The voltage shift per thickness of gallium nitride is assumed to be an inherent property. Claim 11: Tang teaches the gate dielectric is silica or a high-k material [0027]. Claims 13-14: Guha teaches the dipole layer includes any one or more of the metal oxides (and nitrides) listed in Table 1 [0029]. This renders obvious depositing an initial gallium oxide followed by a gallium nitride layer. Claim 20: For the purposes of searching for and applying prior art under 35 U.S.C. 102 and 103, absent a clear indication in the specification or claims of what the basic and novel characteristics actually are, "consisting essentially of" will be construed as equivalent to comprising. See, e.g., PPG, 156 F.3d at 1355, 48 USPQ2d at 1355. MPEP 2111.03. Claim(s) 2-5, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2017/0179252) in view of Guha (US 2009/0302370) in view of Clark (US 2008/0242077). Previously cited prior art is discussed above but does not teach the precursors used. It is noted that Tang teaches the gate electrode is any suitable metal, metal alloy, or metal-containing material [0029] and Guha teaches the gate electrode is TiN [0025] (relevant for claim 10). However, Clark teaches a method of ALD [0019] wherein the precursors include gallane (GaH3) or triple ligand group III precursors where the ligands are alkyl group or halides such as iodine [0083], alkyl hydrazine [0085], and halide metal precursors are generally known [0063; 0082]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to practice the method of Tang/Guha using the precursors disclosed by Clark. Clark establishes the precursors are known for use in an ALD processes. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2017/0179252) in view of Guha (US 2009/0302370) in view of Zhang (US 2020/0373300). Previously cited prior art is discussed above but does not teach a gate all around transistor. However, Zhang teaches gate all around transistors [0001] including a dipole layer [0005] and being an alternative transistor structure [0030]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to practice the method of Tang/Guha on a gate all around transistor because Zhang teaches the inclusion of a dipole layer and substitution with other transistor structures. Response to Arguments Applicant's arguments filed 11/10/25 have been fully considered but they are not persuasive. Applicant argues that GaN is not insulating. The examiner disagrees. Guha states the dipole layer is an insulating material, such as a metal oxide or metal nitride selected from those listed in Table 1. The materials listed in the Table 1 are semiconducting materials, which are technically defined as insulators with a band gap of less than 3 eV. In the specific case of Ga2O3 and GaN, these materials have a large band gap >3 eV and that puts them into the category of insulators. This is the reason Guha refers to them as such. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEX A ROLLAND whose telephone number is (571)270-5355. The examiner can normally be reached M-F 10-6:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Curtis Mayes can be reached at 5712721234. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEX A ROLLAND/Primary Examiner, Art Unit 1759
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Prosecution Timeline

Jan 04, 2023
Application Filed
Aug 06, 2025
Non-Final Rejection — §103
Nov 10, 2025
Response Filed
Jan 27, 2026
Final Rejection — §103
Mar 30, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
46%
Grant Probability
60%
With Interview (+13.4%)
3y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 585 resolved cases by this examiner. Grant probability derived from career allow rate.

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