DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (i.e., claims 1-8) in the reply filed on 5/4/26 is acknowledged. Claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventions, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7, and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. No. 2022/0171910 to Shen et al. (“Shen”).
As to independent claim 1, a cell library that is stored in a non-transitory computer-readable storage medium (¶ 0003, 0014, 0025, 0026, 0060, 0066, 0067. Shen teaches EDA cell libraries and an augmented library database generated from standard cell characterization data, and Shen teaches such EDA data structures are stored on non-transitory computer-readable storage medium.), wherein the cell library is configured to store: first delay information of a standard cell according to a threshold voltage of a transistor included in the standard cell (¶ 0026, 0027, 0031, 0032, 0057. Shen teaches augmented library databases stores delay/timing sensitivity information for standard cell delay based on physical device parameters, including transistor threshold voltage shift.); and second delay information of the standard cell according to mobility of the transistor included in the standard cell (¶ 0026, 0027, 0032, 0033. Shen’s augmented library database stores delay/timing sensitivity information for standard cell delay based on physical device parameters, including a transistor mobility degradation parameter.).
As to claim 2, the cell library of claim 1, wherein the first delay information includes an amount of change in a first delay of the standard cell according to an amount of change in the threshold voltage of the transistor included in the standard cell, and wherein the second delay information includes a change in a second delay of the standard cell according to a change in the mobility of the transistor included in the standard cell (¶ 0026, 0027, 0032, 0033, 0041. Shen stores delay/timing sensitivity data for standard cell delay in augmented library databases, and that sensitivity data corresponds to changes in physical parameters including transitory threshold-voltage shift and transistor mobility degradation parameter.).
As to claim 4, the cell library of claim 1, wherein the transistor is a first transistor included in the standard cell, wherein the standard cell further includes a second transistor, wherein the first delay information includes: delay information of the standard cell according to the threshold voltage of the first transistor; and delay information of the standard cell according to a threshold voltage of the second transistor, and wherein the second delay information includes: delay information of the standard cell according to the mobility of the first transistor; and delay information of the standard cell according to mobility of the second transistor (¶ 0017, 0026, 0027, 0031-0033, 0046, 0057. Shen teaches a standard cell includes transistors and the timing model uses physical device, e.g., transistor, parameters. Thus, the transistor recited in claim 1 is taught as a transistor included in a standard cell. This transistor may be considered the claims “first transistor”. Shen teaches the standard cell includes a second transistor because Shen defines a cell as a set of transistors and teaches the physical parameter coverage for different device types, including PMOS and NMOS. Shen’s augmented library databases stores standard cell delay/timing sensitivity information according to threshold voltage parameters, and Shen teach such physical parameters may be provided for different transistor device types, including PMOS and NMOS. Shen’s augmented library databases stores standard cell delay/timing sensitivity information according to mobility-related transistor parameters, and Shen teaches such physical parameters may be provided for different transistor device types, including PMOS and NMOS.).
As to claim 7, the cell library of claim 1, wherein the cell library is further configured to store third delay information with respect to a specific environment of the standard cell (¶ 0024, 0026, 0032. Shen teaches nominal standard cell delay information with respect to specific characterization environments, including cell input slew and load capacitance, and further teaches simulation at different process corners such as TT and SS.).
As to claim 8, the cell library of claim 1, wherein the standard cell is a first standard cell and the transistor is a first transistor, and wherein the cell library is further configured to store: delay information of a second standard cell according to a threshold voltage of a second transistor included in the second standard cell; and delay information of the second standard cell according to mobility of the second transistor included in the second standard cell (¶ 0017, 0025, 0026, 0027, 0032, 0033, 0035, 0057. Shen discloses standard cell library data for cells, and defines a cell as including a set of transistors. Shen’s augmented library database is generated from characterization data for standard cells plural, covers multiple cell types such as INV, ND2, and NR2, and stores timing sensitivity data according to threshold voltage physical-parameter changes. Shen’s augmented library database stores timing sensitivity data for standard cell delay according to physical parameter changes, including a mobility degradation parameter, and Shen teaches that the library covers multiple standard cell types.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of US Pub. No. 2023/0110560 to Ding et al. (“Ding”).
Shen teaches all the limitations of claim 1 from which claim 3 depends. Shen, however, does not teach the limitations of claim 3.
Ding teaches a standard cell and expressly identifies a transistor at the boundary of the cell (¶ 0024), transistor performance depends on proximity to the cell boundary (¶ 0026), LDE impact depends on where transistors are located relative to the standard cell boundary (¶ 0027), cell boundary conditions are determined for a cell in an IC layout (¶ 0034), cells are selected from a library during physical implementation of an IC (¶ 0050), defines the cell as including transistors and other components (¶ 0050), describes the IC design/fabrication process (¶ 0044), and Ding teaches LLE/LDE impact on a standard cell being modeled through timing/library data and based on boundary conditions, and Ding teaches a unified framework that avoids separate ad hoc modeling for each LLE technology type (¶ 0003, 0006, 0007, 0021, 0027, 0035, 0043). In view of Shen’s stored delay information according to threshold voltage and mobility, the combined teachings render obvious defining or accounting for the LLE of the standard cell using the first and second delay information independently of a particular type of LLE.
It would have been obvious to a PHOSITA to combine Shen and Deng because both references are directed to improving EDA timing analysis and standard cell library modeling. The combination provides improved timing accuracy for standard cells affected by neighboring cell layout effects while reducing library characterization overhead and avoiding ad hoc LLE modeling for each technology node.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of US Patent No. 7,653,885 to Nandy et al. (“Nandy”).
Shen teaches all the limitations of claim 1 from which claim 5 depends. Shen, however, does not teach the limitations of claim 5.
Nandy teaches a cell library stores/uses power dissipation/static power/leakage information for cells and that such power information is related to threshold voltage categories such as high Vt, standard Vt, and low Vt (3:29-39, 5:37-42, 5:54-6:5).
It would have been obvious to a PHOSITA to include power information according to transistor threshold voltage in Shen’s physical parameter away cell library because Nandy teaches threshold voltage is related to cell power dissipation/leakage and that cell libraries use power dissipation values to select and optimize cells. The modification would predictably extend Shen’s Vth aware timing library to include Vth aware power information for conventional power optimization.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of US Patent No. 5,838,947 to Sarin et al. (“Sarin”).
Shen teaches all the limitations of claim 1 from which claim 6 depends. Shen, however, does not teach the limitations of claim 6.
Sarin teaches storing cell power information in a power object library file and teaches cell power behavior is affected by carrier mobility saturation (2:13-18, 55-60, 3:3-9, 20-27, 15:13-19).
It would have been obvious to a PHOSITA to include power information according to transistor mobility in Shen’s physical parameter aware library because Shen already identifies mobility/mobility degradation as a relevant transistor physical parameter, and Sarin teach that cell power behavior is affected by carrier mobility saturation and that cell level power information is stored in a library. The combination would predictably allow Shen’s mobility aware library framework to support power analysis in addition to timing analysis.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851
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