DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 11/24/2025 has been entered.
Claim Objections
Claim 1 is objected to because of the following informalities: In Line 7, the Claim should be amended to recite: “set a mode of operation of the circuit…”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu et al. (US 2023/0417828 A1, Filed June 23, 2022, herein Yu).
Regarding Claim 1, Yu teaches:
An integrated circuit (IC) (IC Package 205 that contains an IC [0029]; see Fig 2) comprising:
a pin (pin 250 [0029]; see Fig 2); and
detect a resistor (Resistance Detector 230 [0034]; see Fig 2) and a capacitor (Capacitance Detector 240 [0034]; see Fig 2) coupled to the pin (pin 250 [0034]; see Fig 2);
responsive to the detection, generate a first measurement of a resistance of the resistor and a second measurement of a capacitance of the capacitor (In Step 704, the resistance detector 230 detects a resistance and the capacitance detector 240 detects a capacitance that are connected to the pin 250 [0069].; see Fig 7); and
set a mode of operation of circuit responsive to the first and second measurements (The external components introduce additional variables for consideration when designing a circuit. The detection, determination and/or measurement of component parameters enables automatic configuration of the IC Package - "set a mode of operation" [0030]).
Regarding Claim 21, Yu teaches:
the circuit includes circuitry configurable to provide the first and second measurements in digital representations (Resistance Detector 230 has ADC 518 to determine resistance Rp - "first measurement in digital representation" [0061]. Capacitance Detector 240 has ADC 610 to calculate the capacitance Cl - "second measurement in digital representation" [0067].; see Fig 5,6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Wang et al. (CN 210111588 U, Pub Feb 21, 2020, herein Wang).
Yu does not teach the limitations.
However, Wang teaches:
the circuit is part of a power converter circuit (IC 4955 is a PWM circuit that converts a power supply voltage to a lower modulated voltage. Pin RC of IC4955 is connected to an RC circuit that determines the Off time of the PWM signal [p.6].; see Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Yu in view of Wang by having the circuit is part of a power converter circuit because it is applying a known technique to a known device ready for improvement to yield the predictable result of using a PWM circuit to convert power with high energy efficiency and reduced heat generation.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen (CN 111965431 A, Pub Nov 20 2020) and further in view of Landauer et al. (US 2020/0082238 A1, Pub Mar 12 2020, herein Landauer).
Yu teaches:
An integrated circuit (IC) (IC Package 205 that contains an IC [0029]; see Fig 2) comprising:
a pin (pin 250 [0029]; see Fig 2);
a circuit coupled to the pin (Detection circuitry 210 and switch network 215 [0034]; see Fig 2), the circuit including:
a resistance determination circuit coupled to the pin (Resistance Detector 230 [0034]; see Fig 2);
a capacitance determination circuit coupled to the pin (Capacitance Detector 240 [0034]; see Fig 2); and
a mode circuit having inputs coupled to outputs of the resistance determination circuit and the capacitance determination circuit (The external components introduce additional variables for consideration when designing a circuit. The detection, determination and/or measurement of component parameters enables automatic configuration of the IC Package [0030]. The circuit within the IC that takes in the resistance and capacitance values to automatically configure the IC Package is the "mode circuit".).
Yu does not teach:
a resistance determination circuit including a first current mirror and a first counter
However, Chen teaches:
a resistance determination circuit including a first current mirror and a first counter (Comparison and control circuit 100 determines the resistance of Rx using current mirror 104 and counting circuit 112 [p.7].; see Fig 2);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Yu in view of Chen by having a resistance determination circuit including a first current mirror and a first counter because such a circuit eliminates the problem of measurement precision reduction caused by drift or delay with a simplified circuit and measure the resistance as taught by Chen [p.5].
Yu and Chen do not teach:
a capacitance determination circuit including a second current mirror and a second counter
However, Landauer teaches:
a capacitance determination circuit including a second current mirror and a second counter (Circuit 200 determines capacitance CDUT and has current mirror 202 and a counter within digital logic 210 [0040-0042].; see Fig 2A); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Yu and Chen in view of Landauer by having a capacitance determination circuit including a second current mirror and a second counter because such a circuit is able to monitor the voltage-crossing signals and calculate the capacitance as taught by Landauer [0043].
Allowable Subject Matter
Claims 17-20 are allowed.
Regarding Claim 17, the prior art of record fails to teach or suggest, singly or in combination an integrated circuit comprising:
“a configurable resistor having a terminal coupled to the second terminal of the second current mirror and to the second input of the second OP AMP, and having a control input coupled to the counter output of the first counter“ in combination with the other limitations of the Claim.
Claims 18-20 are allowed as depending on Claim 17.
Claims 2-9 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the prior art of record fails to teach or suggest, singly or in combination an integrated circuit comprising:
“a first switch having first and second terminals, the first terminal coupled to the first terminal of the current mirror, and the second terminal coupled to the pin;
a second switch having first and second terminals, the first terminal coupled to the terminal of the current source circuit, the second terminal coupled to the pin” in combination with the other limitations of the Claim.
Claims 3-9 are objected to as depending on objected Claim 2.
Regarding Claim 11, the prior art of record fails to teach or suggest, singly or in combination an integrated circuit comprising:
“a first switch having first and second terminals, the first terminal coupled to the terminal of the current source circuit, the second terminal coupled to the pin;
a second switch having first and second terminals, the first terminal coupled to the terminal of the second current mirror, the second terminal coupled to the pin” in combination with the other limitations of the Claim.
Claims 12-16 are objected to as depending on objected Claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAHUL MAINI whose telephone number is (571)270-1099. The examiner can normally be reached M-Th, 9am-4pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.M/Examiner, Art Unit 2858 02/18/2026
/ALESA ALLGOOD/Primary Examiner, Art Unit 2858