DETAILED ACTION
Supplemental Reply
The supplemental reply filed on 06/08/2026 was entered.
Response to Arguments
Applicant’s arguments with respect to claims 1, 21 and 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Melanson et al. (US 9,521,712 B1, Pub Dec 13, 2016, herein Melanson) in view of Linear Technology (Datasheet for LTC3649; Pub 2015; Linear Technology; Rev B).
Regarding Claim 1, Melanson teaches:
An integrated circuit (IC) (IC 402, [8:27-9:55], Fig 4), comprising:
a configuration circuit (IDAC 404, Voltage ADC 406 & Controller 408, [8:30-33], Fig 4) coupled to the mode pin (IC pin 410, [8:39], Fig 4) and configurable to:
detect (obtaining resistance and capacitance measurements via a single pin of the IC [8:27-30]) a resistor (resistor R1 412) and a capacitor (capacitor C1 414) coupled to the mode pin (410);
responsive to the detection, generate a first measurement of a resistance of the resistor (The resistance of resistor R1 412 is estimated by applying first current input signal Ir1 using IDAC 404, and then using a comparator (not shown) referenced to a voltage Vref1 and using equation R1 = Vref1/Ir1 [8:49-60].; see Fig 4 and also Figure 2) and
a second measurement of a capacitance of the capacitor (The capacitance of capacitor C1 414 is measured by determining the amount of time Tref required to charge capacitor C1 414 to 63% of Vref1 using the voltage ADC 406 and, and then dividing Tref by the R1 value determined in the resistance measurement [8:66-9:25].; see Fig 4-5); and
set a mode of operation (The IC may be configured to sense multiple external components using a single pin and use the multiple measurements to set multiple control parameters of the controller [2:3-6].) of the integrated circuit (402) responsive to the first (measurement of resistance of resistor 412 R1) and second measurements (measurement of capacitance of capacitor C1 414).
The Examiner is interpreting "set a mode of operation of the integrated circuit" in light of [0029] of the Instant Specification. [0029] states "Logic circuitry… may configure one or more parameters about the operation of the IC based on both the... digital codes." Thus, a mode of operation is a parameter about the operation of the IC.
Melanson does not teach:
a switch node pin;
a mode pin that is different than the switch node pin; and
However, Linear Technology teaches:
The Examiner is combining Melanson in view of Linear Technology by using the IDAC 404, Voltage ADC 406 and Controller 408 and unshown comparator of Figure 4 of Melanson in the IC shown in Figure 2 of Linear Technology. Specifically, the aforementioned parts of Melanson would be used at Linear Technology's ISET Pin to determine the resistance RSET and capacitance CSET of the Buck Regulator of Figure 2. RSET and CSET are used to determine the soft start time parameter tss of the IC as taught on pp. 11-12.
a switch node pin (pin SW, Fig 2, see pp. 7 & 15);
a mode pin (pin ISET, Fig 2, see pp. 7 & 15) that is different than the switch node pin (pin SW);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Melanson in view of Linear Technology by having a switch node pin and a mode pin that is different than the switch node pin because it is applying a known technique to a known device ready for improvement to yield the predictable result of ensuring that both the resistance and capacitance fall within the range specified in the datasheet. The time constant that is the product of the resistance and capacitance by itself does not convey the individual resistance and capacitance values, so knowing those two values definitively yields the abovementioned advantage. By knowing the resistance and capacitance separately, it is possible to tell whether the resistor or capacitor has failed or both.
Regarding Claim 21, Melanson teaches:
the circuit includes circuitry configurable to provide the first (Controller 408 records R1 by using the comparator to determine the first digital current value provided by IDAC 404 that causes the comparator to change its state. Thus, R1 is a digital value within controller 408 [5:26-47].; see Fig 2 & 4) and second measurements (Voltage analog-to-digital converter 406 provides a digital value to controller 408 that the voltage on pin 410 has reached 63% of Vref1. Controller 408 records time Tref digitally at which the voltage on pin 410 has reached 63%. Then Tref and previously determined R1, which is digitally stored in 408 are used to calculate a digital value of C1 [8:66-9:25].; see Fig 4) in digital representation.
Regarding Claim 22, Melanson does not teach the limitations.
However, Linear Technology teaches:
The Examiner is combining Melanson in view of Linear Technology in the same way as in Claim 1.
the circuit is part of a power converter circuit (LTC3649 is a buck converter; see Title).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Melanson in view of Linear Technology by having the circuit is part of a power converter circuit because it is applying a known technique to a known device ready for improvement to yield the predictable result of ensuring that both the resistance and capacitance fall within the range specified in the datasheet. The time constant that is the product of the resistance and capacitance by itself does not convey the individual resistance and capacitance values, so knowing those two values definitively yields the abovementioned advantage. By knowing the resistance and capacitance separately, it is possible to tell whether the resistor or capacitor has failed or both.
Regarding Claim 23, Melanson teaches:
determining a resistance value (The resistance of resistor R1 412 is estimated by applying first current input signal Ir1 using IDAC 404, and then using a comparator (not shown) referenced to a voltage Vref1 and using equation R1 = Vref1/Ir1 [8:49-60].; see Fig 4 and also Figure 2) for a resistor (resistor R1 412 [8:36]) coupled to the mode pin (IC pin 410 [8:39]);
determining a capacitance value (The capacitance of capacitor C1 414 is measured by determining the amount of time Tref required to charge capacitor C1 414 to 63% of Vref1 using the voltage ADC 406 and, and then dividing Tref by the R1 value determined in the resistance measurement [8:66-9:25].; see Fig 4-5) for a capacitor (capacitor C1 414) coupled to the mode pin (410) and coupled in parallel with the resistor (412);
configure a parameter (The IC may be configured to sense multiple external components using a single pin and use the multiple measurements to set multiple control parameters of the controller [2:3-6])... based on the resistance value (R1) and the capacitance value (C1);
Melanson does not teach:
A method in a switching voltage regulator having a switch node pin and a mode pin, the method comprising:
provide a signal for an inductor coupled to the switch node pin.
configure a parameter of the switching voltage regulator based on the resistance value and the capacitance value; and
However, Linear Technology teaches:
The Examiner is combining Melanson in view of Linear Technology by using the IDAC 404, Voltage ADC 406 and Controller 408 and unshown comparator of Figure 4 of Melanson in the IC shown in Figure 2 of Linear Technology. Specifically, the aforementioned parts of Melanson would be used at Linear Technology's ISET Pin to determine the resistance RSET and capacitance CSET of the Buck Regulator of Figure 2. RSET and CSET are used to determine the soft start time parameter tss of the IC as taught on pp. 11-12.
A method in a switching voltage regulator (Figure 2, Buck regulator) having a switch node pin (pin SW, Fig 2, see pp. 7 & 15) and a mode pin (pin ISET, Fig 2, see pp. 7 & 15), the method comprising:
configure (see explanation above of the combination of Melanson in view of Linear Technology) a parameter (tss, pp.11-12) of the switching voltage regulator (Buck Regulator, Fig 2) based on the resistance value (RSET, pp.11-12) and the capacitance value (CSET, pp.11-12); and
provide a signal (See the Functional diagram on p.8 to see how a signal is provided to pin SW.) for an inductor (L 1.5uH, Fig 2) coupled to the switch node pin (pin SW, Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Melanson in view of Linear Technology by having a method in a switching voltage regulator having a switch node pin and a mode pin, the method comprising: provide a signal for an inductor coupled to the switch node pin. configure a parameter of the switching voltage regulator based on the resistance value and the capacitance value because it is applying a known technique to a known device ready for improvement to yield the predictable result of ensuring that both the resistance and capacitance fall within the range specified in the datasheet. The time constant that is the product of the resistance and capacitance by itself does not convey the individual resistance and capacitance values, so knowing those two values definitively yields the abovementioned advantage. By knowing the resistance and capacitance separately, it is possible to tell whether the resistor or capacitor has failed or both.
Regarding Claim 24, Melanson teaches:
A system (Fig 4) comprising:
a resistor (resistor R1 412, [8:27-39]) having a terminal (non-grounded terminal of resistor R1 412);
a capacitor (capacitor C1 414, [8:27-39]) having a terminal (non-grounded terminal of capacitor C1 414);
an integrated circuit (IC 402, [8:27-39]) having a mode pin (IC pin 410, [8:27-39]) coupled to the terminal of the resistor and to the terminal of the capacitor (the non-grounded terminals of 412 & 414 are both connected to the same node that is connected to pin 410),
the IC (402) including a configuration circuit (IDAC 404, Voltage ADC 406 & Controller 408, [8:30-33], Fig 4) coupled to the mode pin (410) and configurable to:
determine a resistance value of the resistor (The resistance of resistor R1 412 is estimated by applying first current input signal Ir1 using IDAC 404, and then using a comparator (not shown) referenced to a voltage Vref1 and using equation R1 = Vref1/Ir1 [8:49-60].; see Fig 4 and also Figure 2);
determine a capacitance value of the capacitor (The capacitance of capacitor C1 414 is measured by determining the amount of time Tref required to charge capacitor C1 414 to 63% of Vref1 using the voltage ADC 406 and, and then dividing Tref by the R1 value determined in the resistance measurement [8:66-9:25].; see Fig 4-5); and
set a parameter (The IC may be configured to sense multiple external components using a single pin and use the multiple measurements to set multiple control parameters of the controller [2:3-6].) of the IC (402) based on the resistance (measurement of resistance of resistor 412 R1) and capacitance values (measurement of capacitance of capacitor C1 414).
Melanson does not teach:
a switching regulator including:
an inductor having a terminal; and
an integrated circuit (IC) having a switch node pin configurable to provide an output signal to the terminal of the inductor responsive to an input signal
However, Linear Technology teaches:
The Examiner is combining Melanson in view of Linear Technology by using the IDAC 404, Voltage ADC 406 and Controller 408 and unshown comparator of Figure 4 of Melanson in the IC shown in Figure 2 of Linear Technology. Specifically, the aforementioned parts of Melanson would be used at Linear Technology's ISET Pin to determine the resistance RSET and capacitance CSET of the Buck Regulator of Figure 2. RSET and CSET are used to determine the soft start time parameter tss of the IC as taught on pp. 11-12.
a switching regulator (Figure 2, Buck regulator) including:
an inductor (L 1.5uH, Fig 2) having a terminal (left side of L, Fig 2); and
an integrated circuit (IC) (LTC3649, Fig 2) having a switch node pin (pin SW, Fig 2, see pp. 7 & 15) configurable to provide an output signal (signal provided at pin SW) to the terminal (left side of L, Fig 2) of the inductor responsive to an input signal (VIN 24V, Fig 2) Please also see the functional diagram on p.8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Melanson in view of Linear Technology by having a switching regulator including: an inductor having a terminal; and an integrated circuit (IC) having a switch node pin configurable to provide an output signal to the terminal of the inductor responsive to an input signal because it is applying a known technique to a known device ready for improvement to yield the predictable result of ensuring that both the resistance and capacitance fall within the range specified in the datasheet. The time constant that is the product of the resistance and capacitance by itself does not convey the individual resistance and capacitance values, so knowing those two values definitively yields the abovementioned advantage. By knowing the resistance and capacitance separately, it is possible to tell whether the resistor or capacitor has failed or both.
Regarding Claim 25, Melanson teaches:
the resistor (412) and capacitor (414) are coupled in parallel.
Allowable Subject Matter
Regarding Claim 10, Melanson teaches a single IDAC and a controller. While Melanson does not teach a current mirror in the IDAC, IDACs are conventionally known as having current mirrors. Furthermore, in order to measure the resistance Melanson suggests that the controller increments and counts the level of current required to make the comparator switch states. Melanson then sets the IDAC to output a current that is equal to that aforementioned level of current and then the controller counts the amount of time for the voltage across the capacitor to reach a certain voltage level.
Melanson does not teach multiple current mirrors and multiple counters, and does not teach the output of a first counter that is used to measure resistance being the input of a second counter that is used to measure capacitance.
Claims 10-16 are allowed.
Regarding Claim 10, the prior art of record fails to teach or suggest, singly or in combination an integrated circuit comprising:
“a capacitance determination circuit coupled to the pin and including a second current mirror coupled to a second counter that has an output, the second current mirror having a first terminal coupled to the output of the first counter” in combination with the other limitations of the Claim.
Claims 11-16 are allowed as depending on allowed Claim 10.
Claims 17-20 are allowed.
Regarding Claim 17, the prior art of record fails to teach or suggest, singly or in combination an integrated circuit comprising:
“a configurable resistor having a terminal coupled to the second terminal of the second current mirror and to the second input of the second OP AMP, and having a control input coupled to the counter output of the first counter“ in combination with the other limitations of the Claim.
Claims 18-20 are allowed as depending on Claim 17.
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the prior art of record fails to teach or suggest, singly or in combination an integrated circuit comprising:
“a first switch having first and second terminals, the first terminal coupled to the first terminal of the current mirror, and the second terminal coupled to the pin;
a second switch having first and second terminals, the first terminal coupled to the terminal of the current source circuit, the second terminal coupled to the pin” in combination with the other limitations of the Claim.
Claims 3-9 are objected to as depending on objected Claim 2.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.M/Examiner, Art Unit 2858 07/13/2026
/A.A/Primary Examiner, Art Unit 2858
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