Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to Applicant’s amendments filed 25th November 2025. Claims 15-27 were previously pending. Claims 15, 26 and 27 have been amended according to Applicant’s amendments.
No claims have been added or cancelled. Accordingly, claims 15-27 remain pending and are under consideration.
Response to Arguments
Applicant’s arguments, see remarks pages 7-9, filed 25th November 2025, with respect to the rejection of claims 15-27 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Balasubramanian, Schreter, and Chandrashekaraiah (US 2023/0315295 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15-27 are rejected under 35 U.S.C. 103 as being unpatentable over Balasubramanian et al (US 2010/0332646 A1, hereinafter Balasubramanian) in view of Schreter (US 2005/0097258 A1, hereinafter Schreter), further in view of Chandrashekaraiah (US 2023/0315295 A1, hereinafter Chandrashekaraiah).
Regarding claims 15, 26, and 27, taking claim 15 as exemplary, Balasubramanian discloses a computer-implemented method for managing memory areas of a memory unit in a processing unit (See Balasubramanian, [0019], disclosing enhancing system performance of applications and storage subsystems and [0020] disclosing server system 102 including storage subsystems 104A-N and storage management client), the method comprising the following steps:
determining, upon occurrence of a predefined event, a memory configuration profile according to which individual processes are each allowed to access individual memory areas of the memory unit (See Balasubramanian, Fig. 5 and [0025], generating performance profiles for a set of combinations of the applications and the storage subsystems, where the predefined event is the determination of a deployment in the storage network environment and/or [0023], disclosing the polling of performance data based on a set scanning frequency set by a user, or in other words, expiration of a predefined time interval);
configuring the memory unit according to the determined memory configuration profile in such a way that the individual processes are each allowed to access the individual memory areas of the memory unit (See Balasubramanian, [0026] and [0027], disclosing using the performance profiles to configure parameters of the application and the storage subsystem to be substantially similar to the desired performance criteria);
analyzing a performance of the processing unit while the individual processes are being executed in the processing unit and are accessing the individual memory areas according to the determined memory configuration profile (See Balasubramanian, [0023], disclosing performance data collector engine collects performance data associated with the applications and the storage subsystems); and
providing a result of the analysis which describes the performance of the processing unit as a function of the determined memory configuration profile (See Balasubramanian, [0025], disclosing generating performance profiles for a set of combinations of the applications and the storage subsystems and [0026] providing recommendations on a type or model of a storage subsystem best suited for a give application based on the performance profiles).
Balasubramanian does not disclose individual processes are each allowed to access respective individual memory areas. However, Schreter discloses individual processes are each allowed to access respective individual memory areas (See Schreter, Fig. 1 and [0031]-[0034], disclosing threads having respective assigned memory stack portions and accessing its associated stack for reading and/or writing thread private data).
Balasubramanian and Schreter are analogous art directed to improved memory management techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the performance profile monitoring of Balasubramanian with the individual private memory areas of Schreter as memory system performance and privacy can be improved by greatly simplifying the determination of processes and management of process private data by reducing overhead needed for process determination (See Schreter, [0020]).
Neither Balasubramanian and Schreter disclose wherein each respective memory area in question is assigned to a respective process in such a way that each process is allowed exclusive access to a respective one of the memory areas, wherein an assignment of each respective memory area to the respective process is controlled by a quality of service (QoS) requirement of the respective process.
However, Chandrashekaraiah discloses wherein each respective memory area in question is assigned to a respective process in such a way that each process is allowed exclusive access to a respective one of the memory areas (See Chandrashekaraiah. [0044], disclosing designated private memory partitions for use by each host), wherein an assignment of each respective memory area to the respective process is controlled by a quality of service (QoS) requirement of the respective process (See Chandrashekaraiah, [0042], disclosing a QoS processor negotiating a configuration policy with each host, including requested QoS metrics from one or more hosts and [0044] disclosing the designation of memory partitions for use by each host based on the QoS, or in other words, controlled by the QoS).
Balasubramanian, Schreter, and Chandrashekaraiah are analogous art directed to improved memory management and control techniques. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the performance profile based memory system of Balasubramanian and Schreter with the QoS based memory partitions of Chandrashekaraiah as memory system performance can be increased by providing predictable system level QoS used to control the storage services provided by the storage device to ensure applications are prioritized in receiving the QoS commitment (See Chandrashekaraiah [0014]).
Regarding claim 16, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Balasubramanian further discloses wherein the determining of the memory configuration profile is carried out as a function of: process information that describes a relevance of the individual processes to be executed on the processing unit, and/or an access profile that describes accesses of the memory unit by the individual processes to be executed on the processing unit (See Balasubramanian, [0027] and [0028] disclosing performance criteria may include a performance level for a combination of the application and a storage subsystem, which could include link speed, number of channels, desired IO access/seek time/latency and a loading capability of the combination used for generating parameters and applying a performance profile best matching the configuration parameters which meet the performance criteria) .
Regarding claim 17, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Balasubramanian further discloses wherein the occurrence of the predefined event includes: receiving a request for executing one or multiple processes, and/or ending the execution of one or multiple of the individual processes, and/or expiration of a predefined time interval and/or occurrence of a predefined criterion relating to the performance (See Balasubramanian, [0023], disclosing the polling of performance data based on a set scanning frequency set by a user, or in other words, expiration of a predefined time interval).
Regarding claim 18, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Balasubramanian further discloses wherein the analyzing of the performance of the processing unit includes: determining performance properties that describe a performance of the execution of the individual processes and/or a performance of operation of the overall processing unit, and comparing the determined performance properties to predefined performance conditions that describe a predefined performance for the execution of the individual processes and/or a predefined performance for the operation of the overall processing unit (See Balasubramanian, [0029], disclosing performance monitor module 118 monitors the set of combination of the applications and the storage subsystems and compares extracted performance data with threshold values and [0034], disclosing performance counters including CPU utilization, cache utilization, used/available bandwidth).
Regarding claim 19, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 18 hereinabove. Balasubramanian further discloses providing the result of the analysis for taking it into account for determining the memory configuration profile upon a next occurrence of the predefined event, and/or redetermining, upon a next occurrence of the predefined event, the memory configuration profile as a function of a most recently determined memory configuration profile and as a function of the provided result of the analysis (See Balasubramanian, [0031], disclosing analysis of the extracted performance data and [0039] and using a self-learn functionality to generate new templates/profiles to meet the desired performance criteria when an application and/or storage subsystem are configured in the storage network).
Regarding claim 20, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 19 hereinabove. Balasubramanian further discloses wherein the redetermining of the memory configuration profile includes: using the most recently determined memory configuration profile when as the result of the analysis, it is determined that the performance properties match the predefined performance conditions, and/or adapting the most recently determined memory configuration profile when as the result of the analysis it is determined that the performance properties deviate from the predefined performance conditions (See Balasubramanian, [0026] disclosing recommending a matching combination of application and storage subsystem and [0029], disclosing monitoring extracted performance data in real time and comparing with threshold values, or in other words, redetermining the profile using the most recent memory configuration profile, and triggering an alarm in the event performance threshold values are not met and [0039] and using a self-learn functionality to generate new templates/profiles to meet the desired performance criteria when an application and/or storage subsystem are configured in the storage network, or in other words, adapt the memory configuration profile).
Regarding claim 21, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Balasubramanian further discloses wherein the performance of the processing unit relates to: a response time of the individual processes, and/or errors when accessing data of the individual processes (See Balasubramanian, Fig. 3 and [0035]-[0036], disclosing application level performance counters including IO access/seek time/latency).
Regarding claim 22, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Schreter further discloses wherein at least one partition index value is associated with each of the individual processes to be executed in the processing unit, and the determining of the memory configuration profile includes: associating each partition index value with the individual memory areas of the memory unit to assign the individual memory areas in a process of the individual processes which the same partition index value is associated (See Schreter, Fig.1, [0031], disclosing individual threads having assigned individual stacks, and [0034], disclosing each thread and associated stack having thread ID and identical to the index i of the stack to which the thread Ti is assigned).
Regarding claim 23, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Schreter further discloses wherein the determining of the memory configuration profile includes: associating at least one partition index value with each of the individual processes, associating a partition index value with each of the individual memory areas of the memory unit in order to assign each of the individual memory areas to a particular process of the individual processes with which the same partition index value is associated (See Schreter, Fig.1, [0031], disclosing individual threads having assigned individual stacks, and [0034], disclosing each thread and associated stack having thread ID and identical to the index i of the stack to which the thread Ti is assigned ).
Regarding claim 24, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Schreter further discloses wherein a partition index value is associated with certain of the individual processes to be executed in the processing unit, and the determining of the memory configuration profile includes: associating at least one partition index value to each of the individual memory areas of the memory unit to assign each of the individual memory areas to a particular process of the individual processes with which the same partition index value is associated, and/or directly assigning individual memory areas to particular processes of the individual processes with which no partition index value is associated (See Schreter, Fig.1, [0031], disclosing individual threads having assigned individual stacks, and [0034], disclosing each thread and associated stack having thread ID and identical to the index i of the stack to which the thread Ti is assigned).
Regarding claim 25, Balasubramanian in view of Schreter, further in view of Chandrashekaraiah disclosed the method as recited in claim 15 hereinabove. Schreter further discloses wherein the determining of the memory configuration profile is carried out as a function of: partition information that describes an association of each of the individual processes to be executed in the processing unit with a partition index value (See Schreter, Figs 1 and 3 and [0031] and [0041], disclosing different memory configuration profiles that are based on the association between individual threads and individual stacks using an index value i or j).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.H.K/Examiner, Art Unit 2137 /RYAN BERTRAM/Primary Examiner, Art Unit 2137