DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 9, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because (a) in Figure 3, reference character 302, “analyze by using” should be “analyze, by using”, “recording number” should be “recording a number”, and “comprising of” should be “comprising”; (b) in Figure 3, reference character 304, “determine by using” should be “determine, by using”; (c) in Figure 3, reference character 306, “field programmable gated array” should be “field-programmable gate array”; (d) in Figure 3, reference character 308, “deploy by” should be “deploy, by”, “a one or more” (three instances) should be “one or more”, and “CPU, GPU” should be CPU or GPU”; and (e) certain text in Figures 5A and 7A-B is too small to be read without significant zooming, see 37 CFR § 1.84(p)(3). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. However, given the abundance of grammatical errors in the abstract, drawings, and claims, Examiner recommends that Applicant copy-edit the specification and resubmit it.
The abstract of the disclosure is objected to because (a) it begins with the implied phrase “[t]his disclosure relates generally to”; (b) “to method” should be “to a method”; (c) “on FPGA” should be “on an FPGA”; (d) “sets but on systems” should be “sets, but on systems”; (e) “and important to model” should be “and it is important to model”; (f) “a session based” should be “session-based”; and (g) “at least one of a heterogeneous hardware” should be “at least one heterogeneous hardware unit”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The use of the terms XILINX (paragraphs 85 and 88), ALVEO (paragraphs 43 and 85), and INTEL (paragraph 87), which are trade names or marks used in commerce, has been noted in this application. The terms should be accompanied by the generic terminology; furthermore, the terms should be capitalized wherever they appear or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the terms.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) is permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Objections
Claims 1-20 are objected to for being replete with grammatical informalities. Examiner has attached a marked-up copy of the claims indicating where errors have occurred. To the extent that the markings are not self-explanatory and are not corrected, Examiner will enumerate the remaining objections in a subsequent Office Action. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The terms “optimal” in claims 1, 9-13, and 20; “high” in claim 11, “low” in claim 12; “large” in claims 4 and 16; and “safe” in claims 7 and 18 are relative terms which render the claims indefinite. The terms “optimal,” “high,” “low,” “large,” and “safe” are not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. None of the five terms is defined by either the claims or the specification, and Examiner is unaware of any commonly accepted definition of any of the terms in the art.
Claims 4 and 16 recite the limitations "the normalized graph" and “the normalized adjacency matrix”. There is insufficient antecedent basis for these limitations in the claims. Examiner recommends that these claims be amended to depend on claims 3 and 15, respectively (with the dependency of claim 15 being fixed as suggested below).
Claims 6 and 17 recite the limitation "the set of alias input". There is insufficient antecedent basis for this limitation in the claims. Examiner recommends that these claims be amended to depend on claims 2 and 14, respectively.
Claims 6 and 17 additionally recite the limitation "the vector addition". There is insufficient antecedent basis for this limitation in the claims.
Claims 7 and 18 recite “estimating the latency of the attention layer based on latency paths with its corresponding safe margin latency”. (Emphasis added.) It is unclear to what “its” refers.
Claim 15 recites the limitations "the data preprocessing block" and “the HBM”. There is insufficient antecedent basis for these limitations in the claim. Examiner recommends that this claim be amended to depend on claim 14. For purposes of examination, Examiner will construe this and all other claims as though they had the suggested dependencies.
All claims dependent on a claim rejected hereunder are also rejected for being dependent on a rejected base claim.1
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 9, 11-13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., “Session-Based Recommendation with Graph Neural Networks,” in 33.01 Proc. AAAI Conf. Artificial Intelligence 346-53 (2019) (“Wu”) in view of Venieris et al., “Latency-Driven Design for FPGA-based Convolutional Neural Networks,” in 27th Int’l Conf. Field Programmable Logic and Applications (2017) (“Venieris”) and further in view of Iyer et al. (WO 2022139879) (“Iyer”) and Zhao et al. (US 20220237682) (“Zhao”).
Regarding claim 1, Wu discloses “[a] processor implemented method to estimate performance of session[-]based recommendation (SBR) model layers …, comprising:
analyzing, via one or more hardware processors, a session[-]based recommendation (SBR) model sectioned into a set of layers comprising a graph creation layer, a graph neural network (GNN) layer, a[n] … embedding layer, an attention layer, and a scoring layer (Wu Fig. 1 and sec. 3, subsection entitled “Generating Session Embeddings” show that a session-based recommendation with graph neural networks (SR-GNN) method includes modeling all session sequences as session graphs [graph creation layer], obtaining resulting node vectors through a graph neural network [GNN layer], representing each session as the combination of the global preference and the current interests of this session using an attention net [attention layer], computing a hybrid embedding by taking a linear transformation over the concatenation of the local and global embedding vectors [linear transformation = embedding layer], and predicting the probability of each item that will appear to be the next-click one for each session using a softmax layer [scoring layer]; sec. 4 in general discloses analyzing the model and comparing it with baseline methods), and recording … a maximum session length and one or more model parameters comprising … one or more weights and one or more biases (Wu sec. 3, subsection entitled “Learning Item Embeddings on Session Graphs” discloses update functions for nodes of the graph, including
a
s
,
i
t
which depends both on a weight matrix H and a bias vector b; sec. 4, subsection entitled “Analysis on Session Sequence Lengths” discloses that the model was analyzed on both short and long session lengths, with “short” session lengths being less than or equal to 5 [i.e., 5 is the maximum “short” session length]); … [and]
estimating, via the one or more hardware processors, a performance of each layer of the SBR model (Wu sec. 4 in general discloses analyzing the model and comparing it with baseline methods; see mapping to immediately following limitations for further explanation) …,
wherein a graph creation profile estimator estimates the performance of the graph creation layer,
wherein a graph neural network (GNN) profile estimator estimates the performance of the graph neural network (GNN) layer,
wherein a[n] … embedding layer profile estimator estimates the performance of the … embedding layer,
wherein an attention layer profile estimator estimates the performance of the attention layer, and
wherein a scoring layer profile estimator estimates the performance of the scoring layer (Wu Fig. 1 and sec. 3, subsection entitled “Generating Session Embeddings” show that a session-based recommendation with graph neural networks (SR-GNN) method includes modeling all session sequences as session graphs [graph creation layer], obtaining resulting node vectors through a graph neural network [GNN layer], representing each session as the combination of the global preference and the current interests of this session using an attention net [attention layer], computing a hybrid embedding by taking a linear transformation over the concatenation of the local and global embedding vectors [linear transformation = embedding layer], and predicting the probability of each item that will appear to be the next-click one for each session using a softmax layer [scoring layer]; sec. 4 in general discloses analyzing the model and comparing it with baseline methods [note that the subsystem that compares the performance with baseline methods may be regarded as all five estimators, as the evaluation of the system implies the evaluation of all five parts of the system]) ….”
Wu appears not to disclose explicitly the further limitations of the claim. However, Venieris discloses a “method to estimate performance of … model layers on [an] FPGA, comprising: …
recording [a] number of hidden units in each layer (Venieris Fig. 2 shows layer sizes of 16, 64, and 256 for the three convolutional layers of the network tested [these numbers being recorded]) …; …
determining, via the one or more hardware processors, a network bandwidth required to process each layer of the … model based on dimensions of each layer and a corresponding batch size (primary factor that constrains the feasible space of design points on a particular FPGA-based platform is the limited resources; resource vector captures the available FPGA resources and the characteristics of the off-chip memory, where one entry is the measured off-chip memory bandwidth – Venieris, sec. II(G); see also Fig. 2 (showing the dimensions of each convolutional layer [i.e., the system considers these dimensions when calculating the available bandwidth]), sec. IV(C), subsection entitled “AlexNet Case Study” (disclosing that latency estimation takes into consideration the limited off-chip memory bandwidth and is measured with a batch size of 1 [i.e., the necessary bandwidth is a function of the batch size]));
estimating … a performance … on [the] field[-]programmable gate[] array (FPGA) at a predefined frequency by creating a layer profile comprising a throughput and a latency in one or more batches (Venieris sec. IV(C) discloses in general an analysis of using a latency-driven methodology to process neural networks on FPGAs and comparing it to throughput-driven optimization; low-latency design on the AlexNet case study resulted in a 73.54x latency improvement while achieving 82.05% of the high-throughput design’s throughput, with the latency measured with a batch size of 1 [this combination of statistics = layer profile for the layers of the network; since there is only one analysis, predefined frequency = once]), … and
deploying, via the one or more hardware processors, an optimal layer on at least one of … one or more central processing units (CPUs), … one or more graphics processing units (GPUs) and the FPGA based on (i) the estimated performance of each layer profile on the FPGA (in a latency-driven methodology for mapping of inference tasks of ConvNets on FPGAs, the optimization framework explicitly aims for the generation of low-latency ConvNet designs [i.e., the deployed layers are optimized for low latency and deployed on an FPGA; note that since the latency is part of the layer profile, this deployment is based on the performance of the layer profile] – Venieris, sec. I, last paragraph) ….”
Venieris and the instant application both relate to machine learning acceleration and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Wu to deploy the layer on an FPGA based on its estimated performance, as disclosed by Venieris, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would optimize the system, thereby saving time, processing resources, power, or another quantity that is sought to be optimized. See Venieris, sec. I, last paragraph.
Neither Wu nor Venieris appears to disclose explicitly the further limitations of the claim. However, Iyer discloses “deploying … [a] layer … based on … (ii) an execution time of each layer on the CPUs, and the GPUs, and (iii) … one or more options selected by a user (different workload graphs can achieve workload objectives with comparable performance; example graph configurations may include different layer structure arrangements; a graph configuration for a target computational device [e.g., CPU and GPU, see below] is known as a path; first and second paths may accomplish the workload objective with substantially different performance in terms of latency [execution time]; options may be selected including target hardware device preferences (e.g., CPU, GPU, FPGA, etc.) and optimization parameter preferences [options selected by a user] – Iyer, paragraph 220).”
Iyer and the instant application both relate to deployment of machine learning in hardware and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu and Venieris to deploy a layer based on an execution time and user-selected options, as disclosed by Iyer, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the user and/or the system to select the architecture that executes the algorithm most efficiently, thereby saving processing and computing costs. See Iyer, paragraph 220.
Neither Wu, Venieris, nor Iyer appears to disclose explicitly the further limitations of the claim. However, Zhao discloses a “position embedding layer (recommendation network includes an embedding layer that may include positional embeddings to embed the item ID into a low-dimensional space – Zhao, paragraph 75) ….”
Zhao and the instant application both relate to machine learning-based recommender systems and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu, Venieris, and Iyer to include a positional embedding layer, as disclosed by Zhao, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the model to identify with which portion of the input it is dealing. See Zhao, paragraph 89.
Claim 20 is a non-transitory computer-readable medium claim corresponding to processor claim 1 and is rejected for the same reasons as given in the rejection of that claim. Similarly, claim 13 is a system claim corresponding to processor claim 1 and is rejected for the same reasons as given in the rejection of that claim, except insofar as claim 13 additionally recites the following limitations, taught by Iyer: “a memory storing instructions (Iyer Fig. D2, volatile memory D214 storing instructions D232);
one or more communication interfaces (Iyer Fig. D2, bus connecting memory D214 with processor circuitry D212); and
one or more hardware processors coupled to the memory via the one or more communication interfaces[], wherein the one or more hardware processors are configured by the instructions (Iyer Fig. D2, processor circuitry D212 storing instructions D232 and connected to memory D214 via bus) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu, Venieris, and Zhao to store the instructions in a memory and execute them on a computer, as disclosed by Iyer, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system to be run on general-purpose hardware, thereby eliminating the expense of using specialized hardware. See Iyer, paragraphs 136-37.
Regarding claim 9, the rejection of claim 1 is incorporated. Venieris further discloses that “a first option … for deployment of the optimal layer is determined based on a throughput (Venieris sec. IV(C) compares using latency-driven methodologies for executing AlexNet [comprising layers] with throughput-driven optimization [i.e., the optimization of some methods is for throughput]) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu and Zhao to optimize the execution of the layers based on a throughput, as disclosed by Venieris, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow more computation to be performed per unit time, thereby enhancing the efficiency of the system. See Venieris, sec. IV(C).
Neither Wu, Zhao, nor Venieris appears to disclose explicitly the further limitations of the claim. However, Iyer discloses that “a first option selected by the user for deployment of the optimal layer is determined based on a … select[ion] by the user to identify an optimal hardware between the CPUs, the GPUs, and the FPGA (in executing a CNN with various layers using paths that may have substantially different [e.g., optimized] performance, knobs including target hardware device preferences (e.g., CPU, GPU, FPGA, etc.), optimization parameter preferences, etc. may be selected by a user – Iyer, paragraph 220).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu, Zhao, and Venieris to allow a user to make selections that will cause the optimal hardware to be deployed, as disclosed by Iyer, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the system to select the architecture that executes the algorithm most efficiently, thereby saving processing and computing costs. See Iyer, paragraph 220.
Regarding claim 11, the rejection of claim 1 is incorporated. Venieris further discloses that “a third option … for deployment of the optimal layer is determined based on a budget constraint with high throughput (Venieris sec. IV(C) compares using latency-driven methodologies for executing AlexNet [comprising layers] with throughput-driven optimization [i.e., the optimization of some methods is for high throughput] subject to the limitations of the FPGA that executes the algorithms [budget constraint]) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu and Zhao to deploy the layers to optimize for high throughput subject to a budget constraint, as disclosed by Venieris, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow more computation to be performed per unit time, thereby enhancing the efficiency of the system. See Venieris, sec. IV(C).
Neither Wu, Zhao, nor Venieris appears to disclose explicitly the further limitations of the claim. However, Iyer discloses that “a third option [is] selected by the user (knobs [options] including target hardware device preferences, optimization parameter preferences, etc. may be selected by a user – Iyer, paragraph 220) …, and identifying one or more hops between the CPUs, the GPUs, and the FPGA (example improvements develop workload optimizations for heterogeneous environments (e.g., a first edge platform with a CPU, a second edge platform with a GPU, a third edge platform with a combination of CPU and FPGA, etc.) [i.e., the heterogeneous architecture has communication/hops between the various pieces of hardware] – Iyer, paragraph 215).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu, Zhao, and Venieris to hop among heterogeneous architectures, as disclosed by Iyer, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow for greater flexibility to use the most appropriate architecture for a given task. See Iyer, paragraph 215.
Regarding claim 12, the rejection of claim 1 is incorporated. Venieris further discloses that “a fourth option … for deployment of the optimal layer is determined based on the budget constraint with low latency (Venieris sec. IV(C) compares using latency-driven methodologies for executing AlexNet [comprising layers] with throughput-driven optimization [i.e., the optimization of some methods is for low latency] subject to the limitations of the FPGA that executes the algorithms [budget constraint]) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu and Zhao to deploy the layers to optimize for low latency subject to a budget constraint, as disclosed by Venieris, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would save computational time, thereby enhancing the efficiency of the system. See Venieris, sec. IV(C).
Neither Wu, Zhao, nor Venieris appears to disclose explicitly the further limitations of the claim. However, Iyer discloses that “a fourth option [is] selected by the user (knobs [options] including target hardware device preferences, optimization parameter preferences, etc. may be selected by a user – Iyer, paragraph 220) …, and identifying one or more hops between the CPUs, the GPUs, and the FPGA (example improvements develop workload optimizations for heterogeneous environments (e.g., a first edge platform with a CPU, a second edge platform with a GPU, a third edge platform with a combination of CPU and FPGA, etc.) [i.e., the heterogeneous architecture has communication/hops between the various pieces of hardware] – Iyer, paragraph 215).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Wu, Zhao, and Venieris to hop among heterogeneous architectures, as disclosed by Iyer, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow for greater flexibility to use the most appropriate architecture for a given task. See Iyer, paragraph 215.
Allowable Subject Matter
Claims 2-8, 10, and 14-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Krishnan et al., “Performance Model and Profile Guided Design of a High-Performance Session-Based Recommendation Engine,” in Proc. 2022 ACM/SPEC on Int’l Conf. on Performance Engineering 133-44 (2022) (disclosing substantially the claimed invention).2
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C VAUGHN whose telephone number is (571)272-4849. The examiner can normally be reached M-R 7:00a-5:00p ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar, can be reached at 571-272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN C VAUGHN/ Primary Examiner, Art Unit 2125
1 While Examiner has endeavored to be as complete as possible, due to the large number of indefiniteness issues, Examiner recommends that Applicant review the entire claim set to ensure that no further indefinite claim language is present.
2 This reference stems from a conference that ran from April 9-13, 2022, which overlaps the priority date of April 11, 2022 of the instant application. Though the reference potentially qualifies as prior art because it names co-author Sana Iqbal, who is not listed as an inventor in the instant application, see MPEP § 2153.01(a), it is not being applied as prior art because it is unclear whether the date the reference was first publicly disclosed was before or after the priority date. That is, it is not clear whether the reference was first presented at the beginning or at the end of the conference.
Prosecution Insights