DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 Apr 2025 has been entered.
Claim Objections
Claim 23 is objected to because of the following informalities:
Claim 23: the limitation “its channel” should be changed to “the channel” to make it more clear that the channel resistance of the second transistor is being modified in order to set the first voltage.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-6, 9, 18, & 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bîzîitu (US 20160154415 A1).
Regarding Claim 1, Bîzîitu discloses an apparatus (100, Fig 2), comprising: an amplifier (LP OTA, Fig 2) having an amplifier output (output of LP OTA, Fig 2), a first transistor (M105, Fig 2) coupled between a voltage supply terminal (VDD, Fig 2) and an output terminal (source of M105 connected to bottom right output of 110, Fig 2), the first transistor having a first control terminal (gate of M105, Fig 2) coupled to the amplifier output (gate of M105 driven by LP OTA, Fig 2), and a second transistor (M103, Fig 2) coupled between the first control terminal and the output terminal (M103 connected between the gate of M105 and bottom right output of 110, Fig 2), the second transistor having a second control terminal coupled to the amplifier output (gate of M103 connected to the output of LP OTA, Fig 2).
Regarding Claim 3, Bîzîitu discloses an apparatus according to Claim 1, and further discloses wherein the output terminal is coupled to a boot capacitor terminal or an output voltage terminal (source of M105 connected to bottom right output of 110 which is connected to ground voltage of 106, Fig 2).
Regarding Claim 5, Bîzîitu discloses an apparatus according to Claim 1, and further discloses further comprising a switch coupled between the first transistor and the output terminal (M104 is connected between M105 and bottom right output of 110, Fig 2).
Regarding Claim 6, Bîzîitu discloses an apparatus according to Claim 1, and further discloses wherein the second transistor is configurable to set a first voltage at the first control terminal (the voltage at the gate of M105, Fig 2) responsive to a second voltage at the amplifier output (the voltage at the gate of M105 is responsive to the voltage at the output of the amplifier, Fig 2) and a third voltage at the output terminal (the voltage at the gate of M105 is responsive to the voltage connected to the bottom right output of 110, Fig 2).
Regarding Claim 9, Bîzîitu discloses an apparatus according to Claim 1, and further discloses wherein the amplifier and the first and second transistors are part of a buck converter circuit or a low dropout (LDO) voltage regulator circuit (100 is an LDO regulator system that includes M105, M103 and LP OTA, Fig 2, [0062]).
Regarding Claim 18, Bîzîitu discloses an apparatus (100, Fig 2), comprising: an amplifier (LP OTA, Fig 2) having an amplifier output (output of LP OTA, Fig 2) and a reference input (VBg is a voltage reference input to LP OTA, Fig 2, [0064]); a first transistor (M105, Fig 2) coupled between a first terminal (VDD, Fig 2) and a second terminal (source of M105 connected to ground, Fig 2), the first transistor having a first control terminal (gate of M105, Fig 2) coupled to the amplifier output (gate of M105 driven by LP OTA, Fig 2); and a second transistor (M103, Fig 2) coupled between the first control terminal and the second terminal (M103 connected between the gate of M105 and ground, Fig 2), the second transistor having a second control terminal coupled to the amplifier output (gate of M103 connected to the output of LP OTA, Fig 2), wherein the first and second transistors are configurable to have different threshold voltages (M103 & M105 have different sizes and therefore different threshold voltages, Fig 2, [0065]).
Regarding Claim 21, Bîzîitu discloses an apparatus according to Claim 18, and further discloses apparatus of claim 18, wherein: the first and second transistors are field effect transistors (FETs) (M105 and M103 may be MOSFETs, Fig 2, [0066]); the first transistor is a depletion mode or native transistor (Fig 2 shows M105 depicted with a depletion-mode nMOSFET symbol, Fig 2) having its drain coupled to the first terminal (drain of M105 is coupled to VDD, Fig 2) and its source coupled to the second terminal (source of M105 connected to ground, Fig 2), and its gate is the first control terminal coupled to the amplifier output (gate of M105 driven by LP OTA, Fig 2); and the second transistor has its drain coupled to the gate of the first transistor (M103's drain is coupled to the gate of M105, Fig 2) and its source coupled to the second terminal (source of M103 connected to source of M105 and ground, Fig 2), and its gate is the second control terminal coupled to the amplifier output (gate of M103 connected to the output of LP OTA, Fig 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bîzîitu (US 20160154415 A1) in view of Johal (US 8674672 B1).
Regarding Claim 4, Bîzîitu teaches all of the limitations of Claim 1.
Bîzîitu does not teach wherein the amplifier is part of a source follower.
Johal teaches a conventional feedback circuit for use in a regulated power supply (see Fig 3), including wherein the amplifier is part of a source follower ("Both of transistors 304 and 305 are configured as source followers of the source signal." where 304 and 305 are connected to the output of amplifier 302, Fig 3, Col 3[42-43]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the feedback circuit in Bîzîitu, as taught by Johal, as it provides the advantage of low output impedance for stable voltage regulation.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bîzîitu (US 20160154415 A1) in view of Barrow (US 20080231249 A1).
Regarding Claim 10, Bîzîitu teaches a wherein the amplifier and the first and second transistors are part of a packaged integrated circuit (LP OTA, M105, and M103 are part of the amplifier stage 110 that is on the chip, Fig 2, [0074]).
Bîzîitu does not teach wherein the output terminal is a pin or pad of the packaged integrated circuit.
Barrow teaches a conventional integrated circuit (see Fig 1), including wherein the output terminal is a pin or pad of the packaged integrated circuit (output pin 20 of IC 10 connected to the amplifier 12 through the source of transistor 16, Fig 1, [0005]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the integrated circuit in Bîzîitu, as taught by Barrow, as it provides the advantage of a connection point to interface with other components.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Bîzîitu (US 20160154415 A1) in view of Zhu (US 20220385179 A1).
Regarding Claim 20, Bîzîitu teaches all of the limitations of Claim 18.
Bîzîitu does not teach wherein the second terminal is coupled to a boot capacitor terminal or a power output.
Zhu teaches a conventional current limitation circuit for use in a switched capacitor converter (see Figs 1-2), including wherein the second terminal is coupled to a boot capacitor terminal or a power output (the source of N3 is connected to output 204 of Fig 2 which can power one of the power MOSFETS 102a-d from Fig 1 and/or bootstrap capacitor 104, Fig 1-2, [0050]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current limitation circuit in Bîzîitu, as taught by Zhu, as it provides the advantage of generating a higher supply voltage for a power MOSFET ([0048] of Zhu).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Bîzîitu (US 20160154415 A1) in view of Perez (US 20040239304 A1).
Regarding Claim 22, Bîzîitu teaches wherein the first and second transistors are n-channel field effect transistors (NFETs) ("Transistors M103-M110 may be medium or high voltage compliant N-type MOSFETS.", [0066]).
Bîzîitu does not teach a size ratio of the first transistor to the second transistor is 1000:1 or higher.
Perez teaches a conventional LDO (see Fig 3), including a size ratio of the first transistor to the second transistor is 1000:1 or higher ("the ratio between the size of transistors 318 and 316 is 1000:1", Fig 3, Col 3, second paragraph).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the LDO in Bîzîitu, as taught by Perez, as it provides the advantage of precisely sensing current while minimizing power loss.
Allowable Subject Matter
Claims 2, 7-8, 19, & 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, Bîzîitu (US 20160154415 A1) teaches the apparatus according to Claim 1.
Bîzîitu does not teach "further comprising: one or more resistors coupled between the first control terminal of the first transistor and the second control terminal of the second transistor."
Prior art Zhu (US 20220385179 A1), Ohoka (US 20070108949 A1), Inn (US 6275395 B1), Johal (US 8674672 B1), and Barrow (US 20080231249 A1) are considered to be the closest prior art.
Zhu teaches a resistor between transistors N3 and N2, but not between the control terminals of those transistors.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “further comprising: one or more resistors coupled between the first control terminal of the first transistor and the second control terminal of the second transistor."
Regarding Claim 7, Bîzîitu (US 20160154415 A1) teaches the apparatus according to Claim 1, and further teaches wherein: the first and second transistors are field effect transistors (FETs) (M105 and M103 may be MOSFETs, Fig 2, [0066]); the first transistor is a depletion mode or native transistor (Fig 2 shows M105 drawn with a depletion-mode nMOSFET symbol, Fig 2) having its drain coupled to the voltage supply terminal (drain of M105 is connected to VDD, Fig 2) and its source coupled to the output terminal (source of M105 is connected to bottom right output of 110, Fig 2), and its gate is the first control terminal (gate of M105, Fig 2); and the second transistor has its drain coupled to the gate of the first transistor (drain of M103 connected to the gate of M105, Fig 2) and its source coupled to the output terminal (source of M103 connected to the bottom right output of 110, Fig 2), and its gate is the second control terminal (gate of M103, Fig 2).
Bîzîitu does not teach "the second transistor is smaller than the first transistor".
Prior art Zhu (US 20220385179 A1), Ohoka (US 20070108949 A1), Inn (US 6275395 B1), Johal (US 8674672 B1), and Barrow (US 20080231249 A1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “the second transistor is smaller than the first transistor".
Regarding Claim 8, Bîzîitu (US 20160154415 A1) teaches the apparatus according to Claim 1, and further teaches wherein: the first and second transistors are field effect transistors (FETs) (M105 and M103 may be MOSFETs, Fig 2, [0066]); the first transistor has a drain coupled to the voltage supply terminal (drain of M105 is connected to VDD, Fig 2) and a source coupled to the output terminal (source of M105 is connected to bottom right output of 110, Fig 2), and its gate is the first control terminal (gate of M105, Fig 2); and the second transistor has a source coupled to the output terminal (source of M103 connected to the bottom right output of 110, Fig 2), and a gate is the second control terminal (gate of M103, Fig 2).
Bîzîitu does not teach "a body terminal coupled to a reference terminal".
Prior art Zhu (US 20220385179 A1), Ohoka (US 20070108949 A1), Inn (US 6275395 B1), Johal (US 8674672 B1), and Barrow (US 20080231249 A1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “a body terminal coupled to a reference terminal".
Regarding Claim 19, Bîzîitu (US 20160154415 A1) teaches the apparatus according to Claim 18.
Bîzîitu does not teach "comprising at least one of: a first resistor coupled between the first control terminal of the first transistor and the second control terminal of the second transistor; or a second resistor coupled between the second control terminal of the second transistor and the amplifier output."
Prior art Zhu (US 20220385179 A1), Ohoka (US 20070108949 A1), Inn (US 6275395 B1), Johal (US 8674672 B1), and Barrow (US 20080231249 A1) are considered to be the closest prior art.
Zhu teaches a first resistor (R1 is coupled between N2 and N3, but not between the gate terminals of N2 and N3 or between the gate of N2 and output 204, Fig 2).
However, none of the prior art, taken singly or in combination, teach or fairly suggest “comprising at least one of: a first resistor coupled between the first control terminal of the first transistor and the second control terminal of the second transistor; or a second resistor coupled between the second control terminal of the second transistor and the amplifier output. "
Regarding Claim 23, Bîzîitu (US 20160154415 A1) teaches the apparatus according to Claim 6.
Bîzîitu does not teach "wherein the second transistor is configurable to set the first voltage by setting its channel resistance of the second transistor responsive to a difference between the second and third voltages."
Prior art Zhu (US 20220385179 A1), Ohoka (US 20070108949 A1), Inn (US 6275395 B1), Johal (US 8674672 B1), and Barrow (US 20080231249 A1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “wherein the second transistor is configurable to set the first voltage by setting its channel resistance of the second transistor responsive to a difference between the second and third voltages."
Claims 11-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 11, Bîzîitu (US 20160154415 A1) teaches apparatus, comprising: an amplifier (LP OTA, Fig 2) having an amplifier output (output of LP OTA, Fig 2) and a voltage reference input (VBg is a voltage reference input to LP OTA, Fig 2, [0064]); a first transistor (M105, Fig 2) coupled between a voltage supply terminal (VDD, Fig 2) and an output terminal (source of M105 connected to ground, Fig 2), the first transistor having a first control terminal (gate of M105, Fig 2) coupled to the amplifier output (gate of M105 driven by LP OTA, Fig 2); a second transistor (M103, Fig 2) coupled between the first transistor and the output terminal (M103 connected between M105 and ground, Fig 2), the second transistor having a second control terminal coupled to the amplifier output (gate of M103 connected to the output of LP OTA, Fig 2); and a third transistor (M104, Fig 2) coupled between the second transistor and the output terminal (M104 coupled to M103 and ground, Fig 2), the third transistor having a third control terminal (gate of M104, Fig 2), the third control terminal coupled to the amplifier output (gate of M104 connected to the output of LP OTA, Fig 2).
Bîzîitu does not teach "the third transistor having a body terminal, and the body terminal coupled to a reference terminal."
Prior art Zhu (US 20220385179 A1), Ohoka (US 20070108949 A1), Inn (US 6275395 B1), Johal (US 8674672 B1), and Barrow (US 20080231249 A1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “the third transistor having a body terminal, and the body terminal coupled to a reference terminal."
Claims 12-17 are allowable, as they depend on allowable Claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 3/19/2026