DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, 5, 6, 9, 18, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 7-8, 16-17, and 21-23 are objected to because of the following informalities:
Claim 7-8, 16, and 21: multiples recitations of the limitation “a source” and/or “its source” and/or “the source” make it unclear as to which “source” is being referred.
Claim 7-8, 16, and 21: multiples recitations of the limitation “a drain” and/or “its drain” and/or “the drain” make it unclear as to which “drain” is being referred.
Claim 7-8, 16, and 21-23: multiples recitations of the limitation “a gate” and/or “its gate” and/or “the gate” make it unclear as to which “gate” is being referred.
Claim 22 is objected to on the basis of its dependency on Claim 21.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ivanov (US 20190107857 A1).
Regarding Claims 1 and 4, Ivanov discloses an apparatus (100, Fig 1), comprising: an amplifier having an amplifier output (105 has output 118, Fig 1), a first transistor coupled between a voltage supply terminal and an output terminal (M1 coupled to AFDD and coupled to Vout through D1, Fig 1), the first transistor having a first control terminal coupled to the amplifier output (M1 has gate 104 connected to 118, Fig 1) and a second transistor coupled between the first control terminal and the output terminal (M2 connected between gate 104 and connected to Vout through 110, Fig 1), the second transistor having a second control terminal coupled to the amplifier output (109 connected to 118, Fig 1).
Regarding Claim 3, Ivanov discloses an apparatus according to Claim 1, and further discloses wherein the output terminal is coupled to a boot capacitor terminal or an output voltage terminal (112 connected to Vout, Fig 1).
Regarding Claim 5, Ivanov discloses an apparatus according to Claim 1, and further discloses further comprising a switch coupled between the first transistor and the output terminal (D1 connected between M1 and 112, Fig 1).
Regarding Claim 9, Ivanov discloses an apparatus according to Claim 1, and further discloses wherein the amplifier and the first and second transistors are part of a buck converter circuit or a low dropout (LDO) voltage regulator circuit (Fig 1 is an LDO, [0007]).
Claim 11 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen (US 20230009027 A1).
Regarding Claim 11, Chen discloses an apparatus, comprising: an amplifier having an amplifier output and a voltage reference input (210 has output Vpass and input Vref, Fig 3); a first transistor coupled between a voltage supply terminal and an output terminal (T5 is connected between VDDPST2 and VDDPST1, Fig 3), the first transistor having a first control terminal coupled to the amplifier output (T5 gate connected to Vpass, Fig 3);
a second transistor coupled between the first transistor and the output terminal (T6 connected between gate of T5 and VDDPST1, Fig 3), the second transistor having a second control terminal coupled to the amplifier output (T6 control terminal connected to Vpass, Fig 3); and a third transistor coupled between the second transistor and the output terminal (T4 connected between T6 gate and VDDPST1, Fig 3), the third transistor having a third control terminal and a body terminal(T4 has gate and body terminals, Fig 3) , the third control terminal coupled to the amplifier output (T4 gate connected to Vpass, Fig 3), and the body terminal coupled to a reference terminal (T4 connected to ground reference terminal through 220, Fig 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanov (US 20190107857 A1) in view of Asuri (US 9608569 B2).
Regarding Claim 2, Ivanov discloses all of the limitations of claim 1.
Ivanov does not disclose one or more resistors coupled between the first control terminal of the first transistor and the second control terminal of the second transistor.
Asuri teaches a conventional gate-coupling resistor (see Fig 4) including one or more resistors coupled between the first control terminal of the first transistor and the second control terminal of the second transistor (R1 is connected to the gates of 406 and 408, which are both driven by amplifier 404, Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the gate-coupling resistor in Ivanov, as taught by Asuri, as it provides the advantage of limiting cross-coupling and current flow between the gates of transistors sharing a common control signal.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ivanov (US 20190107857 A1) in view of Barrow (US 20080231249 A1).
Regarding Claim 10, Ivanov discloses wherein the amplifier and the first and second transistors are part of a packaged integrated circuit (LP OTA, M105, and M103 are part of the amplifier stage 110 that is on the chip, Fig 2, [0074]).
Ivanov does not disclose wherein the output terminal is a pin or pad of the packaged integrated circuit.
Barrow teaches a conventional integrated circuit (see Fig 1), including wherein the output terminal is a pin or pad of the packaged integrated circuit (output pin 20 of IC 10 connected to the amplifier 12 through the source of transistor 16, Fig 1, [0005]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the integrated circuit in Ivanov, as taught by Barrow, as it provides the advantage of providing a connection point to interface with other components.
Claim 18, 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (US 20220385179 A1) in view of Guan (US 20220376494 A1).
Regarding Claim 18, Zhu discloses an apparatus (200, Fig 2), comprising: an amplifier (212, Fig 2) having an amplifier output and a reference input (212 has output 218 and VREF input, Fig 2); a first transistor (N3, Fig 2) coupled between a first terminal (VPOS, Fig 2) and a second terminal (VNEG, Fig 2), the first transistor having a first control terminal coupled to the amplifier output (gate of N3 connected to 218, Fig 2); and a second transistor (N2, Fig 2) coupled between the first control terminal and the second terminal (N2 connected between gate of N3 and VNEG, Fig 2), the second transistor having a second control terminal coupled to the amplifier output (N2 gate connected to 218, Fig 2),
Zhu doesn't disclose wherein the first and second transistors are configurable to have different threshold voltages.
Guan teaches a conventional protection circuit for use with a power transistor (see Fig 1) including wherein the first and second transistors are configurable to have different threshold voltages (M4 and 110 may have different threshold voltages, Fig 1, [0031]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the protection circuit in Zhu, as taught by Guan, as it provides the advantage of design flexibility ([0044] of Guan).
Regarding Claim 20, the combination of Zhu and Guan discloses all of the limitations of Claim 18, and further discloses wherein the second terminal is coupled to a boot capacitor terminal or a power output (the source of N3 is connected to VNEG of Fig 2 which is also connected to one of the power MOSFETS 102d from Fig 1 and bootstrap capacitor 104, Fig 1-2, [0050] of Zhu).
Regarding Claim 21, the combination of Zhu and Guan discloses all of the limitations of Claim 18, and further discloses wherein: the first and second transistors are field effect transistors (FETs) (N3/221 and N2/219 are FETs, [0054]); the first transistor is a depletion mode or native transistor (transistor 110 may be a normally-on/depletion-mode transistor, [0033] of Guan) having its drain coupled to the first terminal and its source coupled to the second terminal (N3's drain connected to VPOS, Fig 2 of Zhu), and its gate is the first control terminal coupled to the amplifier output (N3's gate connected to 212, Fig 2 of Zhu); and the second transistor has its drain coupled to the gate of the first transistor and its source coupled to the second terminal (N2's drain connected to gate of N3 and N2's source is connected to VNEG, Fig 2 of Zhu), and its gate is the second control terminal coupled to the amplifier output (N2's gate connected to212, Fig 2 of Zhu).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu (US 20220385179 A1) in view of Guan (US 20220376494 A1) and further in view of Perez (US 20040239304 A1).
Regarding Claim 22, Zhu discloses wherein the first and second transistors are n-channel field effect transistors (NFETs) ("n-channel FETs N2 219 and N3 221", [0054] of Zhu).
Zhu does not disclose a size ratio of the first transistor to the second transistor is 1000:1 or higher.
Perez teaches a conventional LDO (see Fig 3), including a size ratio of the first transistor to the second transistor is 1000:1 or higher ("the ratio between the size of transistors 318 and 316 is 1000:1", Fig 3, Col 3, second paragraph).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the LDO in Zhu, as taught by Perez, as it provides the advantage of precisely sensing current while minimizing power loss.
Allowable Subject Matter
Claims 6, 12-15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7-8, 16-17, & 23 would be allowable if rewritten to overcome the Claim Objections set forth in this Office action and written to include all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/ Primary Examiner, Art Unit 2838 9/03/2026
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