DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-22 are rejected under 35 U.S.C. 103 as being unpatentable over Desoli (US 2018/0,189,229) in view of Kodukula (US 11/107,181).
Referring to claims 1, 10 and 14, Desoli discloses a device (fig. 3, device 100) comprising:
an integrated circuit package (fig. 3, SoC 110) to enclose:
a sensor (fig. 4, sensor interface 408b/408c);
a memory (fig. 3, RAM 126);
a controller directly connected to both of the memory and the sensor (fig. 4, DMA 406); and
a deep learning accelerator (fig. 3, CAF 400 and DSP 138; para.0134) having:
a memory interface (fig. 3, bus 166) directly connecting the memory to the deep learning accelerator;
a control unit (fig. 3, memory control 174); and
one processing unit (fig. 4, convolution accelerator CA 600; fig. 6A) to execute instructions (fig. 6A, MAC units 620) having matrix operands (fig. 6A, data stream 606/604/602);
wherein the deep learning accelerator is to:
perform computations of an artificial neural network (fig. 1A, convolutional neural network) to generate an output (fig. 1A, CNN output) of the artificial neural network responsive to an input (fig. 1A, input image) from the sensor; and
communicate, via a host interface (fig. 3, AXI 132), the output to a host system (fig. 3, CPU 128; para.0134, host application).
Kodukula discloses
a sensor (fig. 2A, microlenses 36) formed on a substrate (fig. 2A, sensor element 14) of the integrated circuit package (fig. 2A, package 20);
the memory (fig. 2A, memory 24) and the deep learning accelerator (fig. 2A, vision processing unit 22) are formed on separate integrated circuit dies and connected by through-silicon vias TSVs (fig. 2A, TSV 34) without going through the substrate.
Desoli and Kodukula are analogous art because they are from the same field of endeavor in integrated circuit applications. At the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Desoli and Kodukula before him or her to modify the SoC 100 of Desoli to include the stacked chips with integrated on-chip sensor (fig. 2A) of Kodukula, thereafter the deep learning SoC device has stacked circuit chips within single integrated circuit package using TSVs (Kodukula, fig. 2). The suggestion and/or motivation for doing so would be obtaining the advantage of improved system size and performance advantage (1:64-2:11) as suggested by Kodukula. Therefore, it would have been obvious to combine Desoli with Kodukula to obtain the invention as specified in the application claims.
As to claims 2 and 15, Desoli discloses the device of claim 1, wherein the memory is to store: first data (para.0145, weight) representative of weights of the artificial neural network; and second data representative of instructions (para.0145, activations) executable by the deep learning accelerator to implement the computations of the artificial neural network.
As to claims 3, 11 and 16, Desoli discloses the device of claim 2, wherein the sensor is to write, into the memory, third data (para.0147, camera sensor data) representative of the input to the artificial neural network, and the control unit is to perform the computations of the artificial neural network using the first data and the second data in response to third data being written into the memory (para.0147, DCNN operations).
As to claims 4-6 and 17, Desoli discloses the device of claim 3, wherein the host interface is on a memory/peripheral/serial communication bus (fig. 3, AXI serial bus 132).
As to claims 7 and 18, Desoli discloses the device of claim 6, comprising a set of connectors to be connected to a printed circuit board, a cable, or a receptacle (fig. 3, low speed peripheral 130).
As to claims 8, 12 and 19, Desoli discloses the device of claim 3, wherein the integrated circuit package is with an opening (fig. 4, sensor interface 408b/408c) for the sensor to receive stimuli (fig. 4, image data).
As to claims 9, 13 and 20, Kodukula discloses the device of claim 3, wherein the sensor includes a light sensor (2:28, image sensor).
As to claim 21, Desoli discloses the device of claim 1, wherein the deep learning accelerator is to perform parallel vector (para.0283, vector) or matrix calculations (fig.1A, convolution operation).
As to claim 22, Desoli discloses the device of claim 1, wherein the controller is directly connected to the host interface (figs. 3-4, DMA 406 to bus 166 and AXI 132).
Response to Arguments
Applicant’s arguments have been fully considered, but they are not deemed to be persuasive.
Applicant argues that the cited prior art does not disclose “a controller directly connected to both the memory and the sensor” as amended in independent claims 1, 10 and 14 (pp.2-3).
Desoli discloses DMA 406 directly connect sensors 408 to memory 126. The DMA 406 also connects to host interface AXI 132 via bus 166. Although applicant described the claim limitation with fig. 6 where controller 107 sits between sensor 102 and RAM 105, the limitation can also be described and/or interpreted with fig. 7 where the DLA sits between sensor 102 and RAM 105. For example, the DLA is also the claimed controller.
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in three months from the mailing date of this action. In the event a first reply is filled within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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