Prosecution Insights
Last updated: October 25, 2026
Application No. 18/152,072

SYSTEM-ON-A-CHIP (SOC) INTEGRATION OF RESISTIVE RANDOM-ACCESS MEMORY DEVICES WITH VARYING SWITCHING CHARACTERISTICS

Non-Final OA §103
Filed
Jan 09, 2023
Examiner
PRENTY, MARK V
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
TetraMem Inc.
OA Round
2 (Non-Final)
91%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
676 granted / 740 resolved
+23.4% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
9 currently pending
Career history
746
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
29.3%
-10.7% vs TC avg
§102
39.4%
-0.6% vs TC avg
§112
21.3%
-18.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 740 resolved cases

Office Action

§103
This Office Action is in response to the response filed on August 27, 2026. Claims 1, 4, 5, 7-9 and 11 are rejected under 35 U.S.C. 103 as being obvious over Jiang (newly cited United States Patent 12,507,601) together with Yang (already of record United States Patent 11,387,412). As to independent claim 1, Jiang discloses an apparatus (see the entire patent, including the Fig. 4 disclosure), comprising: a first interconnect layer fabricated on a substrate, wherein the first interconnect layer comprises a plurality of metallic interconnects 102; a first resistive random-access memory (RRAM) device 119 (either one of the illustrated pair), comprising: a first bottom electrode 106 fabricated on a first metallic interconnect 102 of the first interconnect layer; a first top electrode 114; and a first filament-forming layer 110 fabricated between the first bottom electrode and the first top electrode, wherein the first filament-forming layer 110 (Figs. 3A-3B) comprises a first switching oxide (column 4, lines 18-24); and a second RRAM device 119 (the other one of the illustrated pair), comprising: a second bottom electrode 106 fabricated on a second metallic interconnect 102 of the first interconnect layer; a second top electrode 114; and a second filament-forming layer 110 (Figs. 3A-3B) fabricated between the second bottom electrode and the second top electrode, wherein the second filament-forming layer 110 comprises a second switching oxide (column 4, lines 18-24). The difference between claim 1 and Jiang is claim 1’s first and second filament-forming layers 110 comprise different switching oxides (Jiang’s first and second filament-forming layers 110 comprise the same switching oxide). Yang teaches that a RRAM’s two metal oxide switching layers may have identical or different compositions, depending on design considerations (see the sentence bridging columns 5 and 6). It would have been obvious to one skilled in the art to form Jiang’s switching oxide layers 110 of different compositions instead of the same composition, because Yang teaches that a RRAM’s two metal oxide switching layers may have identical or different compositions, depending on design considerations. Claim 1 is thus rejected under 35 U.S.C. 103 as being obvious over Jiang together with Yang. As to dependent claim 4, Wu’s first metallic interconnect is connected to a first transistor, and wherein the second metallic interconnect of the first interconnect layer is connected to a second transistor (see the Fig. 5A disclosure). As to dependent claim 5, Wu’s first switching oxide comprises at least one of HfOx, TaOₓ, TiOx, NbOx, ZrOₓ, or SiO2 (column 4, lines 18-24). As to dependent claim 7, the obvious Jiang/Yang device’s first filament-forming layer does not include the second switching oxide (see the above rejection of claim 1). As to dependent claim 8, Jiang’s device further comprises a second interconnect layer, wherein a first metallic interconnect 120 of the second interconnect layer is fabricated on the first top electrode 114, and wherein a second metallic interconnect 120 of the second interconnect layer is fabricated on the second top electrode 114. As to dependent claim 9, Wu’s first top electrode 114 is connected to a first bitline 542 of a first crossbar circuit, and wherein the second top electrode 114 is connected to a second bitline 542 of a second crossbar circuit (see the Fig. 5A disclosure). As to dependent claim 11, Wu’s first bottom electrode 106 and second bottom electrode 106 comprise the same metallic materials (column 4, lines 8-12). Claims 2, 3, 6, 10 and 12 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The applicant’s arguments are moot in view of the new rejection. Registered practitioners can telephone the examiner at (571) 272-1843. Any voicemail message left for the examiner should include the registration number of the registered practitioner calling. The examiner’s supervisor is Wael Fahmy, whose telephone number is (571) 272-1705. /MARK V PRENTY/Primary Examiner, Art Unit 2814
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Prosecution Timeline

Jan 09, 2023
Application Filed
Mar 27, 2026
Non-Final Rejection mailed — §103
Aug 27, 2026
Response Filed
Sep 16, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
91%
Grant Probability
94%
With Interview (+2.1%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 740 resolved cases by this examiner. Grant probability derived from career allowance rate.

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