DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 15 January 2026 has been entered.
Status of Claims
Claims 1-26, 28, 30, and 31 of US Application No. 18/152,222 are currently pending and have been examined. Applicant amended claims 3 and 26, canceled claim 27, and added claim 31. Applicant previously canceled claim 29.
Response to Arguments/Amendments
Applicant’s arguments, see REMARKS, filed 15 January 2026, regarding the rejections of claims 1-6, 15-20, and 30 under 35 U.S.C. 102 have been fully considered and are persuasive. The previous rejections are withdrawn.
The previous rejections of claims 7-14, 21-26 and 28 under 35 U.S.C. § 103 are withdrawn because they depend from one of independent claims 1 and 15 and the previous rejections of claims 1 and 15 under § 102 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 15-21, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2019/0095302 A1, “Wang”) in view of Luban et al. (US 11,513,814 B1, “Luban”).
Regarding claims 1 and 15, Wang discloses methods and systems for testing components of parallel computing devices and teaches:
operating an electronic control unit (ECU) in a first state (controller 34 includes any number of computer devices 130a-n, where controller 34 may selectively utilize or not utilize any particular computer device 130a-n to perform a computation – see at least Fig. 2 and ¶ [0027]; i.e., first state = computer device 130 being utilized or not utilized to perform a computations);
detecting one or more criteria being satisfied to perform a test associated with the ECU (test control module 110 performs tasks based on a request structure received by a software application running on controller 34, such as periodic testing in sequence, periodically at random, or based on usage – see at least ¶ [0030]);
performing the test associated with the ECU in response to detecting the one or more criteria being satisfied, while the ECU is in a second state different from the first state (test control module 110 performs tasks based on the request structure – see at least ¶ [0030]; i.e., second state = computer device 130 being tested);
storing a result associated with the test in a memory (test control module 110 selects an operational component of a first computer device 130 for performing a test operation and generating a first result – see at least ¶ [0029]; first result is compared to a second result – see at least ¶ [0044]; i.e., the first result is stored for comparison); and
transitioning the ECU to a third state after storing the result, [ ] (result comparison module 118 may indicate that the first computer device 130 is faulty and may feed the fault indication to the system software and/or applications for mitigation or recover actions; i.e., third state = mitigation or recovery state).
Wang fails to teach the third state being a suspended state for the ECU.
However, Luban discloses state suspension for optimizing start-up processes of autonomous vehicles and teaches:
transitioning the ECU to a third state [ ], the third state being a suspended state for the ECU (at B110, low-power state is entered, where the computer may suspend one or more components – see at least Fig. 1 and 7:3-15; e.g., where the computer system is fully powered off except for wake circuitry – see at least 7:3-15; in low-power mode, components may be powered off or partially powered off – see at least 4:34-58).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward to provide for transitioning to a suspended state, as taught by Luban, with a reasonable expectation of success, because transitioning to a suspended state may provide more rapid start-up of the vehicle (Luban at 1:49-64).
Regarding claims 2 and 16, Ward further teaches:
wherein performing the test comprises performing a built-in self-test (BIST) associated with one or more electrical components or one or more software components of the ECU (test control module 110 is configured for selecting an operational component of the first computer device and for instructing the first computer device to perform the test operation and generate a first result – see at least ¶ [0029]).
Regarding claims 3 and 17, Ward further teaches:
wherein the one or more electrical components include at least one of the memory, a processor, control logic, a power management circuit, or a voltage regulator (computing devices 130a-n may include operational components 132a-n, e.g., ALU, register, memory, cache, and test control module 110 may select an operation component to be tested – see at least ¶ [0029]).
Regarding claims 4 and 18, Ward further teaches:
wherein the second state comprises an opportunistic testing state (test control module 110 performs tasks based on the request structure – see at least ¶ [0030]; i.e., second state = computer device 130 being tested) and wherein the one or more criteria comprise: the vehicle being powered off, the vehicle being in a suspended state, the vehicle not being in use for a duration (testing may be performed during idle cycles of first device 130 – see at least ¶ [0031]), the vehicle transitioning to being in a low power mode.
Luban further teaches:
wherein the second state comprises an opportunistic testing state (running diagnostics at B104 – see at least Fig. 1 and 6:378-53; alternatively, fault checking at B126 – see at least Fig. 1 and 8:44-53) and wherein the one or more criteria comprise: the vehicle being powered off (B104 is executed after a shut-down/power off indication is received at B102 – see at least Fig. 1 and 6:25-36), the vehicle being in a suspended state (B104 may be executed after exiting the low-power mode at B124 – see at least Fig. 1 and 8:32-43), the vehicle not being in use for a duration (B104 may be executed after a time interval has passed at B122 for exiting the low-power mode at B124 – see at least Fig. 1 and 8:54-67), the vehicle transitioning to being in a low power mode (at 126, faults may be detected while the computer system is in the low-power mode – see at least Fig. 1 and 8:44-53).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward to provide for transitioning to the opportunistic test state, as taught by Luban, with a reasonable expectation of success, because it would provide for checking for error accumulation during operation of components and check for latent defects (Luban at 3:45-63).
Regarding claims 5 and 19, Ward further teaches:
wherein the second state comprises an opportunistic testing state (test control module 110 performs tasks based on the request structure – see at least ¶ [0030]; i.e., second state = computer device 130 being tested) and wherein the one or more criteria comprise: the ECU transitioning to being powered off, the ECU transitioning to being in a suspended state, or the ECU transitioning to being in a low power mode (testing may be performed during idle cycles of first device 130 – see at least ¶ [0031]).
Luban further teaches:
wherein the second state comprises an opportunistic testing state (running diagnostics at B104 – see at least Fig. 1 and 6:378-53; alternatively, fault checking at B126 – see at least Fig. 1 and 8:44-53) and wherein the one or more criteria comprise: the ECU transitioning to being powered off (B104 is executed after a shut-down/power off indication is received at B102 – see at least Fig. 1 and 6:25-36), the ECU transitioning to being in a suspended state (at 126, faults may be detected while the computer system is in the low-power mode – see at least Fig. 1 and 8:44-53), or the ECU transitioning to being in a low power mode (at 126, faults may be detected while the computer system is in the low-power mode – see at least Fig. 1 and 8:44-53).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward to provide for transitioning to the opportunistic test state, as taught by Luban, with a reasonable expectation of success, because it would provide for checking for error accumulation during operation of components and check for latent defects (Luban at 3:45-63).
Regarding claims 6 and 20, Ward further teaches:
wherein the one or more criteria are relative to when the test was last performed (test control module 110 performs tasks based on a request structure received by a software application running on controller 34, such as periodic testing in sequence, periodically at random, or based on usage – see at least ¶ [0030]).
Regarding claims 7 and 21, Luban further teaches:
wherein: the one or more criteria are satisfied when a timer expires or when a counter reaches a threshold value (B104 may be executed after a time interval has passed at B122 for exiting the low-power mode at B124 – see at least Fig. 1 and 8:4-67); and the method further comprises restarting the timer or resetting the counter, in response to performing the test associated with the ECU (the loop is repeated – see at least Fig. 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward to provide for using expiration of a timer, as taught by Luban, with a reasonable expectation of success, because the timer would indicate that diagnostics need to be performed for remaining in the low-power mode (Luban at 8:4-20).
Regarding claim 30, Wang discloses methods and systems for testing components of parallel computing devices and teaches:
operating an electronic control unit (ECU) in a first state (controller 34 includes any number of computer devices 130a-n, where controller 34 may selectively utilize or not utilize any particular computer device 130a-n to perform a computation – see at least Fig. 2 and ¶ [0027]; i.e., first state = computer device 130 being utilized or not utilized to perform a computations);
detecting one or more criteria being satisfied to perform a test associated with the ECU (test control module 110 performs tasks based on a request structure received by a software application running on controller 34, such as periodic testing in sequence, periodically at random, or based on usage – see at least ¶ [0030]);
performing the test associated with the ECU in response to detecting the one or more criteria being satisfied, while the ECU is in a second state different from the first state (test control module 110 performs tasks based on the request structure – see at least ¶ [0030]; i.e., second state = computer device 130 being tested);
storing a result associated with the test in a memory (test control module 110 selects an operational component of a first computer device 130 for performing a test operation and generating a first result – see at least ¶ [0029]; first result is compared to a second result – see at least ¶ [0044]; i.e., the first result is stored for comparison); and
transitioning the ECU to a third state after storing the result, [ ] (result comparison module 118 may indicate that the first computer device 130 is faulty and may feed the fault indication to the system software and/or applications for mitigation or recover actions; i.e., third state = mitigation or recovery state).
Wang fails to teach the third state being a low power mode for the ECU.
However, Luban discloses state suspension for optimizing start-up processes of autonomous vehicles and teaches:
transitioning the ECU to a third state [ ], the third state being a low power mode for the ECU (at B110, low-power state is entered, where the computer may suspend one or more components – see at least Fig. 1 and 7:3-15; e.g., where the computer system is fully powered off except for wake circuitry – see at least 7:3-15; in low-power mode, components may be powered off or partially powered off – see at least 4:34-58).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward to provide for transitioning to a low power mode state, as taught by Luban, with a reasonable expectation of success, because transitioning to a suspended state may provide more rapid start-up of the vehicle (Luban at 1:49-64).
Claims 8, 9, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ward in view of Luban, as applied to claims 1 and 15, and further in view of Sarangi et al. (US 2019/0195947 A1, “Sarangi”) and Ogura (US 2020/0307474 A1).
Regarding claims 8 and 22, Ward and Luban fail to teach but Sarangi teaches:
checking the stored result in response to an indication to resume the ECU from a suspended state (system reads the results from EMMC 131 the next time the system is powered up and compares them to previously established metrics – see at least ¶ [0043], [0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined systems for testing components of Ward and Luban to provide for checking a result, as taught by Sarangi, with a reasonable expectation of success, because performing checking that the result meets safety targets may allow the processing unit to continue to function (Sarangi at ¶ [0043]).
Ward and Sarangi fail to teach but Ogura discloses a wire harness and safety management system and teaches:
performing one or more actions in response to checking the result (ECU data is compared to data stored in ROM and if the difference between the data is abnormal a warning may be issued to an occupant at S111 – see at least Figs. 6, 7 and ¶ [0074]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward, Luban, Sarangi to provide for performing an action in response to checking a result, as taught by Ogura, with a reasonable expectation of success, because performing the action may warn an occupant of the vehicle that the ECU is in an abnormal state (Ogura at ¶ [0009]).
Regarding claims 9 and 23, Luban further teaches:
performing one or more safety checks associated with the ECU while the ECU is in the suspended state and prevented from executing a safety application associated with the vehicle (at B126, controller may perform a diagnostic while in the low-power mode – see at least Fig. 1 and 8:44-53); and
allowing the ECU to resume from the suspended state in response to completing the one or more safety checks (after logging the fault at B128 and the passing of the time interval at B122, the low-power mode may be exited at B124 and diagnostics may be performed again at B104 – see at least Fig. 1 and 8:32-67).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined systems for testing components of Ward, Luban, Sarangi, and Ogura to provide for performing safety checks, as further taught by Luban, with a reasonable expectation of success, because it would allow for checking for faults while in the low-power mode (Luban at 8:44-53).
Claims 10 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Ward in view of Luban, Sarangi, and Ogura, as applied to claims 8 and 22 above, and further in view of Sun et al. (US 2019/0250210 A1, “Sun”).
Regarding claims 10 and 24, Sarangi further teaches:
determining that the result indicates an error associated with the ECU (system reads the results from EMMC 131 the next time the system is powered up and compares them to previously established metrics to determine if the SoC 110 and processor meet functional safety targets – see at least ¶ [0043], [0052]); and
storing a result of the subsequent test in the memory (test data and results can be stored in embedded multi-media controller – see at least ¶ [0019], [0029], [0052]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the systems for testing components of Ward to provide for determining that the result indicates an error and storing the result, as taught by Sarangi, with a reasonable expectation of success, because storing the result allows for performing checking that the result meets safety targets may allow the processing unit to continue to function (Sarangi at ¶ [0043]).
Sarangi fails to teach but Sun disclose a system architecture apparatus and method for fault detection and teaches:
performing a subsequent test in response to determining that the result indicates the error (vehicle SoC 300 runes a built-in self-test to detect faults before the key is turned on and new BISTs, generated via machine learning, are executed based on the initial test results – see least Fig. 8 and ¶ [0033]-[0034]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined system test of chips in functional systems of Ward, Sarangi, and Ogura to provide for performing a subsequent test, as taught by Sun, with a reasonable expectation of success, because performing subsequent tests may optimize and improved effectiveness of fault testing (Sun at ¶ [0013]).
Claims 11 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ward in view of Luban, Sarangi, and Ogura, as applied to claims 8 and 22 above, and further in view of Kowkutla et al. (US 2021/0209003 A1, “Kowkutla”).
Regarding claims 11 and 25, Ogura further teaches:
providing, to one or more other ECUs or an entity, an indication that the result indicates an error associated with the ECU (ECU data is compared to data stored in ROM and if the difference between the data is abnormal a warning may be issued to an occupant at S111 – see at least Figs. 6, 7 and ¶ [0074]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system test of chips in functional systems of Ward, Luban, Sarangi, and Ogura to provide for performing an action in response to checking a result, as further taught by Ogura, with a reasonable expectation of success, because providing an indication of an ECU error may warn an occupant of the vehicle that the ECU is in an abnormal state (Ogura at ¶ [0009]).
Ward, Luban, Sarangi, and Ogura fail to teach but Kowkutla discloses an integrated circuit with state machine for pre-boot self-tests and teaches:
preventing the ECU from booting (if the self-test is completed successfully, second boot operations, i.e., safe boot, of the processor core or related SoC is initiated at 1108 – see at least Fig. 11 and ¶ [0050]; i.e., normal booting is prevented).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined system test of chips in functional systems of Ward, Luban, Sarangi, and Ogura to provide for preventing booting, as taught by Kowkutla, with a reasonable expectation of success, because the reliability of the integrated circuit may be improved (Kowkutla at ¶ [0018]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ward in view Luban, as applied to claim 1 above, and further in view of Webopedia (Suspend-to-RAM).
Ward and Luban fail to teach but Webopedia teaches:
wherein the suspended state includes a suspend-to-memory state (suspend-to-RAM occurs when a system enters a low-power state).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined systems for testing components of Ward and Luban to provide for a suspend-to-memory state, as taught by Webopedia, with a reasonable expectation of success, because it will allow the program to waken to perform tasks at any time and prevent information loss if power is interrupted (Webopedia).
Claims 14 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ward in view of Luban, as applied to claims 1 and 8 above, and further in view of Chavali et al. (US 2014/0223052 A1, “Chavali”).
Regarding claims 14 and 28, Ward and Luban fail to teach but Chavali teaches:
wherein operating the ECU in the first state comprises performing, via the ECU, a safety operation and a non-safety operation, associated with the vehicle (safety and non-safety functions may be implemented on a system on a chip (SOC) – see at least ¶ [0022]; CPU 102 may perform non-safety functions and safety functions – see at least Fig. 2 and ¶ [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combined systems for testing components of Ward and Luban to provide for operating the ECU to perform safety and non-safety operations, as taught by Chavali, with a reasonable expectation of success, because integrating safety and non-safety functions on a single chip is less cost-prohibitive (Chavali at ¶ [0022]).
Allowable Subject Matter
Claims 12, 26, and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON L TROOST whose telephone number is (571)270-5779. The examiner can normally be reached Mon-Fri 7:30am-4pm.
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/AARON L TROOST/
Primary Examiner, Art Unit 3666