DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-17 have been presented for examination based on the application filed on 1/10/2023.
Claims 1-6 are rejected under 35 U.S.C. 101 because the claimed invention is directed to software per se.
Claim 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Claims 1-6, 8-10, and 13-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
Claims 1, 5, 7, 11-12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20070157150 A1 by Ogami; Kenneth Y. et al..
Claim(s) 2-3, 8-9, 13-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 20070157150 A1 by Ogami; Kenneth Y. et al., in view of US 20060218454 A1 by Ohara; Yasushi.
Claim(s) 4, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 20070157150 A1 by Ogami; Kenneth Y. et al., in view of US 20060218454 A1 by Ohara; Yasushi, further in view of US 7784011 B2 by Kato; Yoshiyuki et al.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 20070157150 A1 by Ogami; Kenneth Y. et al., in view of US 20080109782 A1 by Adelman; Maxim et al.
This action is made Non-Final.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed in instant application to 111127256, filed 07/20/2022.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6 are rejected under 35 U.S.C. 101 because the claimed invention is directed to software per se.
Claims 1-6 discloses a “system" in the preamble; however none of the modules in the limitations are specifically claimed as structural elements constituting a system and the claim is rejected as software per se. Specification [0005] discloses "... [0005] According to the purposes of the present disclosure, embodiments of the present disclosure provide an online integrated microcontroller development tool system. The online integrated microcontroller development tool system comprises a pin required module, a functional component module and a description code project output module....". The claim mentions modules connected to database; however the database is not positively recited as being part of the structure of the system. The claim at best appears to include online software modules, executing the functionality and does not include any additional structural components for the system claim; therefore the claim 1 and dependent claims 2-6 as a whole appear to be software per se.
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Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
For system claim 1 limitations:
a pin required module, signally coupled to a database, and configured to select a suitable model number of a microcontroller from the database according to a pin requirement information of a client, perform a pin arrangement on a microcontroller block corresponding to the suitable model number, and output the microcontroller block with a plurality of arranged pins;
a functional component module, signally coupled to the pin required module and the database, and configured to select a functional component corresponding to a functional component requirement information, and connect the microcontroller block with the plurality of arranged pins to the functional component to generate a circuit structure respectively; and
a description code project output module, signally coupled to the functional component module, and configured to output a microcontroller application circuit hardware description code based on the circuit structure.
in claim 1.
The three prong test for each of the above module shows that (A) “configured to” is as a substitute for "means" and that is a generic placeholder; (B) generic placeholder (configured to) is modified by functional language as identified by the italicized part of limitation above.
(C) the generic placeholder (configured to) is not modified by sufficient structure. The structure disclosed in the claim is not the structure belonging to the generic placeholder, but to the what it connects.
The pin required module is recited in claim 1 explicitly. The functional component module is recited in claims 1, 2, 4 explicitly. The description code project output module is recited in claims 1-4 explicitly. These limitations are inherited in the remaining claims 1-6.
Additionally for system claim 2 limitations:
a test circuit project output module, signally coupled to the functional component module, and configured to form and output a test circuit hardware description code; and
an online program development compilation module, signally coupled to the description code project output module and the test circuit project output module, and configured to compile the microcontroller application circuit hardware description code and the test circuit hardware description code to generate a hardware description compiled code, and provide the client to download the hardware description compiled code to a development board for testing.
Discloses a test circuit project output module & an online program development compilation module in claim 2, using generic placeholder “configured to” and not further modified by sufficient structure describing the module itself (not what is connects to).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
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Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically claim discloses “pin required module” as recited in claim 1. The “functional component module” as recited in claims 1, 2, 4 explicitly. The “description code project output module” as recited in the claims 1-4. Similarly “test circuit project output module” & “online program development compilation module” also lack specific structure identified in the specification. The specification does not appear to disclose any structure for the modules for the system claims. Therefore what structure is included in these modules is indefinite. These limitations are inherited in the claims 2-6. See specific mapping for each module reference as recited in the specification in the rejection under 35 USC 112(a).
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Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6, 8-10, and 13-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1-6 are directed to a system, however the modules disclosed therein do not have structural support in the specification. The specification is therefore lacks written description in view of citation for each module below.
Module invoking 112/6th
Support in specification (lacking the structure support)
pin required module
[0005], [0017], [0022], [0025], [0027], [0033], [0036]
functional component module
[0005], [0017]-[0018], [0023], [0027], [0036], [0038]
description code project output module
[0005], [0017]-[0018], [0020], [0023], [0038]
test circuit project output module
[0019], [0024], [0038]
online program development compilation module
[0019], [0024], [0038]-[0039]
Claim 2 additionally recites:
2. The online integrated microcontroller development tool system according to claim 1, further comprising:
a test circuit project output module, signally coupled to the functional component module, and configured to form and output a test circuit hardware description code;…
Specification discloses support for a test circuit project output module as follows:
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The specification lacks written description for what steps are performed/what specific hardware is used to form and output a test circuit hardware description code. Specifically specification is devoid of any means to form [test] code for given functionality (user design provided in step S203) let alone forming an output for the test code. Claims 8 & 13 recite similar limitations suffer from similar deficiency and are rejected likewise. Dependent claims 3-4, 9-10 and 14-15 are also rejected for inheriting this deficiency.
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Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 7, 11-12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20070157150 A1 by Ogami; Kenneth Y. et al..
Regarding Claim 1, 7 and 12
Ogami teaches
(Claim 1). An online integrated microcontroller development tool system (Ogami: Abstract & Fig.3 teaching the processing device maker 300; online aspect can be seen in Fig.11 w.r.t. computer system 1100 connected to network elements 1124 & 1125; [0116] computer/server) , comprising:
(Claim 7) A method of implementing an online integrated microcontroller , development tool (Ogami: Fig.1, Fig.3 teaching the processing device maker 300; online aspect can be seen in Fig.11 w.r.t. computer system 1100 connected to network elements 1124 & 1125), comprising:
(Claim 12) A microcontroller development combination kit (Ogami: Abstract & Fig.3 teaching the processing device maker 300; online aspect can be seen in Fig.11 w.r.t. computer system 1100 connected to network elements 1124 & 1125; [0116] computer/server), comprising: a non-transitory storage media (Ogami: [0123]-[0124]) , storing a plurality of description code, and configured to communicatively couple a computer device and an online integrated microcontroller development tool system, and execute a method of implementing an online integrated microcontroller development tool through the online integrated microcontroller development tool system (Ogami: Figs.9-11 & [0116]-[0126] showing process programmed to generate the code for FPGA) , and the method comprising:
a pin required module (Ogami: in Fig. 3 as Device Selection UI 314 and Base project selector 304) , signally coupled to a database (Ogami: [0048] "... In one embodiment, the design evaluator 302 accesses the base project library 310 [as database which contains the model number of a microcontroller/processing device] to find base project metadata describing hardware resources pertaining to each base project. ..." [0049] "... [0049] As discussed above, each base project corresponds to a specific processing device...." – here the base projects are the available processing devices from which based on resources (e.g. pin information), one of them is selected [0047]-[0050]) , and configured to select a suitable model number of a microcontroller from the database according to a pin requirement information of a client (Ogami: [0047] "... As the user composes the application design, the design evaluator 302 detects changes to the design and determines resource needs associated with the new design. In particular, in one embodiment, the design evaluator 302 identifies channel types required by device drivers selected by the user, and determines resource needs specified by the channels. The resource needs may include, for example, blocks and pins to be used by user modules associated with the channels...."; [0048]-[0050]; Fig.1 shows the flow; [0061]-[0065]) , perform a pin arrangement on a microcontroller block corresponding to the suitable model number (Ogami: [0051]; Fig.7 shows automatic pin assignment as pin arrangement; Fig.8A shows manual pin assignment) , and output the microcontroller block with a plurality of arranged pins (Ogami: [0076]"... FIG. 8B illustrates data components of a placeable channel 850. The channel 850 includes metadata 852, fragments 854, and source code templates 856. The metadata 852 is used by the processing device maker 106 for resource management (e.g., to map drivers into the base projects that contain enough resources to implement the required functionality). The source code templates 856 are used for code generation (to generate the embedded application project)...."); In general channel/pin assignment and placement is discussed in [0067]-[0099]);
a functional component module (Ogami: Fig.3 Application Composer 306 as functional component module) , signally coupled to the pin required module and the database (Ogami: See Fig.3 showing it being connected to database 308, 310 and connected to elements 314 & 304 mapped to pin required module; [0051]) , and configured to select a functional component corresponding to a functional component requirement information, and connect the microcontroller block with the plurality of arranged pins to the functional component to generate a circuit structure respectively (Ogami: [0051]; Fig.10 showing functional components 1008, 1020, 1022; which are implemented on the processing device; Fig.9 [0100] – [0112] shows the flow how the functional components ) ; and
a description code project output module, signally coupled to the functional component module (Ogami: Fig.1 and Fig.9 flow culminating in the implementation as shown in Fig.10) , and configured to output a microcontroller application circuit hardware description code based on the circuit structure (Ogami: Fig.1 generating the code in step 132 and eventually the binary in step 138 which is stored in Fig.10 Non-Volatile Storage (NVS) 142 of actual implementation processing device 140 and Fig.10 element 1006 & 1018) .
Regarding Claims 51,2, 11 and 16
Ogami teaches wherein the pin requirement information comprises a pin count (Ogami: [0060] "... [0060] At block 604, processing logic determines resource requirements of the new design. The resource requirements may include, for example, the number of blocks and pins needed to accommodate the combination of drivers in the user design....") and a specification type of each of the pins (Ogami: [0005] "... An I/O driver maps onto a channel that provides an adaptation layer between the I/O driver and microcontroller peripherals. For each type of microcontroller, several application projects are predefined with different selections of channel resources...." [0060] "... each driver specifies a channel type that defines resource requirements such as blocks and pins required for user modules performing the functionality of the relevant driver....") – here the channel type can be digital or analog as shown in the Fig.10 and there is separate channel database/library 308 for it and its implementation is Fig.8B).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-3, 8-9, 13-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 20070157150 A1 by Ogami; Kenneth Y. et al., in view of US 20060218454 A1 by Ohara; Yasushi.
Regarding Claims 2, 8 and 13
Teachings of Ogami are shown in the parent claim 1 or 7 or 12.
Ogami does not specifically teach a test circuit project output module and associated functionality. Ogami assumes the intended functionality is exhaustively tested before hand (Ogami: [0027], [0031]).
Ohara teaches a test circuit project output module (Ohara : Fig.1 elements 9/10 and 19-20; 10th embodiment Fig. 11 [0202]-[0207] showing the module to generate the test circuit; Alternately 12th Fig.13 embodiment showing the test circuit including test circuit placement with the functional/user design) , signally coupled to the functional component module (Ohara: [0202] "... The circuit automatic generation method of the embodiment is a method of automatically generating a top-layer circuit based on the HDL description syntax by inputting generation specifications of a test mode signal for controlling a semiconductor integrated circuit, terminal test specifications for controlling terminals by a test mode signal, input/output information of function circuit and circuit information to which function circuit is connected, test specifications added to each function circuit, and input/output information of the top-layer circuit and circuit information to which the top-layer circuit is connected to an input section...." [0202]-[0205]) , and configured to form and output a test circuit hardware description code (Ohara : Fig.11 elements 54-55) ; and an online program development compilation module, signally coupled to the description code project output module and the test circuit project output module, and configured to compile the microcontroller application circuit hardware description code and the test circuit hardware description code to generate a hardware description compiled code (Ohara : Fig.1 elements 9/10 and 19-20; Fig.18 element 77 showing the combined output as HDL; ) , and provide the client to download the hardware description compiled code to a development board for testing (Ohara : See [0025]; Ogami also teaches downloading as shown in Fig.10 & [0065][0111]) .
It would have been obvious to one (e.g. a designer) of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Ohara to Ogami to account for insitu testing of the implemented design rather than relying assumed pre-testing of the user design (as in Ogami: [0027]-[0031]). The motivation to combine would have been that Ohara complements Ogami to generate test circuit (in HDL) along with functional circuit (as in Ohara: Fig.1 elements 17-21) so that the input data and the expectation value data input to the top-layer circuit, the function circuit, and the test circuit required for executing function verification of the semiconductor integrated circuit can be generated, so that the time taken for creating the input data and the expectation value data can be reduced (Ohara: [0047]). Further motivation to combine would be that Ogami and Ohara are analogous art to the instant claim in the field of implementing user design/functionality as HDL (or binary) (Ogami: Fig.1 and 10; Ohara: Fig.1 showing design implemented as HDL Fig.1 elements 17-21).
Regarding Claims 3, 9 and 14
Ogami teaches wherein the description code project output module further outputs an application programming interface (API), a driver or a third-party code library of the functional component to a computer device connected to the development board (Ogami: Fig.2 [0039]-[0040] [0077] [0085]-[0087] discussing API and drivers implemented on the base project 206 (user design) / channels which are outputted as binary on the processing device 1000 (development board) in Fig.10) .
Regarding Claim 17
Ohara & Ogami teaches wherein the plurality of description codes of the non-transitory storage media comprises a verification program (Ohara: Figs.8-9 & [0019]-[0023] [0188]"... [0188] A processing section 2 includes storage means 4 and verification input data and expectation value data generation means 38, and automatically generates verification input data 39 and verification expectation value data 40....") ; wherein the verification program is configured to verify the development board (Ohara: [0191] Fig.9 "... [0191] FIG. 9 is a drawing to show a specific mode of automatically generating the verification input data and the verification expectation value data to verify the terminals of a semiconductor integrated circuit in the embodiment....") ; and the computer device is allowed to be communicatively coupled to the online integrated microcontroller development tool system after the development board is verified (Ohara: See [0025]; Ogami also teaches downloading as shown in Fig.10 & [0065][0111]) .
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Claim(s) 4, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 20070157150 A1 by Ogami; Kenneth Y. et al., in view of US 20060218454 A1 by Ohara; Yasushi, further in view of US 7784011 B2 by Kato; Yoshiyuki et al.
Regarding Claim 4, 10 and 15
Teachings of Ogami and Ohara are shown in the parent claim 3/9/14. Ogami & Ohara do not specifically teach claim 4 limitations.
Kato teaches the description code project output module further outputs a circuit application diagram of the functional component and the microcontroller to the client (Kato: Fig.1 outputting the circuit diagram from 100 ; Fig.4A and 4B Col.4 Lines 55-Col.5 Lines 11 showing the circuit application diagram rearranged based on pin management; Fig.2 circuit diagram reflecting unit 130 showing the micro-controller as chip with connections as in Fig.3; Also see Fig.7).
It would have been obvious to one (e.g. a designer) of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kato to Ogami and Ohara to output circuit diagram implemented on FPGA, complementing the Ogami (Ogami: Fig.10 showing various functional components 1008, 1020, 1022 without connection details; Ohara: HDL without circuit digram), showing connection details as seen at least in Fig.2 output circuit diagram (Kato: Fig.2 output of 100). The motivation to combine would have been that Kato addresses the pin swap/reassignment by visualizing that in circuit representation complements the Ogami’s pin assignment issues (Ogami: Fig.7-8) thererby showing some assignments may violate constraints and can be fixed with pin assignment (Kato: Fig.7 Col.7 Lines 5-36). Further motivation to combine would be that Ogami and Kato are analogous art to the instant claim where the programming a processing device (like FPGA) is addressed based on user design specification (pin assignment)(Kato: Fig.7 Col.7 Lines 5-36; Ogami: Fig.1 and 10).
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 20070157150 A1 by Ogami; Kenneth Y. et al., in view of US 20080109782 A1 by Adelman; Maxim et al.
Regarding Claim 6
Teachings of Ogami are shown in the parent claim 5.
Ogami does not specifically teach pin requirement information further comprises a functional requirement, an operating voltage, an operating frequency, a digital-to-analog conversion resolution, a bit rate, a core type, a power consumption, a minimum operating temperature, a maximum temperature or a combination thereof.. Ogami teaches assignment of pins (I/O) to channels and each channel is associated with channel types with their own functional requirements (Ogami : [0089]
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- although claimed functional requirements would be implicit in channel type definition, such).
Adelman teaches wherein the pin requirement information further comprises a functional requirement, an operating voltage, an operating frequency, a digital-to-analog conversion resolution, a bit rate, a core type, a power consumption, a minimum operating temperature, a maximum temperature or a combination thereof (Adelman: [0011] "... Such tools provide a visual representation of the FPGA or ASIC device. The visual representation of the FPGA or ASIC illustrates the limitations and/or properties of the package pins (such as through color coding or shading). Such tools may also provide an engineer making logical pin to package pin assignments with an indication when the properties of a logical pin do not match the properties of a package pin or a signal pin bank in which the package pin is included. As is known, signal pins in FPGA devices may be divided into "signal pin banks", where the signal pin banks share certain properties, such as power supply voltage, input reference voltage and differential reference voltage, as some examples. ..." [0034] "... When assigning package pins to logical pins, the compatibility of the properties of the package pins with the properties of the logical pins is also considered. For instance, a package pin with a 3.3V power supply voltage should not be assigned to a logical pin that is defined as a 2.5V input/output structure. In such a case, the package pin properties would be incompatible with the logical pin properties...."; [0038], [0041]; Fig.3) .
It would have been obvious to one (e.g. a designer) of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Adelman to Ogami to assign logical pin which are compatible to pins on the actual device, further detailing pin assignment discussed in Ogami (Ogami: Fig.7-8: Adelman: Figs. 3, 5, 7). Further motivation to combine would have been that Adelman and Ogami are analogous art to the instant claim in the domain of pin assignment on a programmable device (Adelman: Figs. 3, 5, 7 discussing pin assignment to a certain group, pins having properties (like assigned voltages of 3.3V or 2.5V); Ogami: [0089], Fig. 7-8).
Conclusion
All claims are rejected.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
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Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKASH SAXENA whose telephone number is (571)272-8351. The examiner can normally be reached Mon-Fri, 7AM-3:30PM.
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AKASH SAXENA
Primary Examiner
Art Unit 2188
/AKASH SAXENA/Primary Examiner, Art Unit 2188 Thursday, May 28, 2026
1 Also see US Patent No. 10664636 (Hodge; Damon G. et al.) pin management and validation from PE2E Search L13
2 Also see US PGPUB No. US 20150199088 A1 (Chandaria; Trisala et al.) showing pin configuration from PE2E Search L14 (IP.com)
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