Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Acknowledgment is made of the amendment filed 06/01/2026 (“A.NE”), in which: claim 14 is amended; no claims are cancelled; no new claims are added; and the rejection of the claims are traversed. Claims 1 – 20 are currently pending an Office action on the merits as follows.
Examiner acknowledges the amendment to claim 14, rending the objection to claim 14 as moot. Examiner withdraws the previous objection of claim 14 due to an informality.
Response to Arguments
Applicant’s arguments with respect to claims 1 – 20 currently pending, have been fully considered but are moot in view of the new grounds of rejection.
Applicant invokes the common ownership exception under 35 USC § 102(b)(2)(C) on pgs. 9 – 11 of the instant remarks such that Cheng et al. (US 20220343862 A1) is disqualified prior art. This necessitates a Second Non-Final Rejection, provided below. Examiner asserts that US 20200144346 A1 (previously cited as pertinent art) discloses the features that Cheng was relied upon for.
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 3 and 11 – 14, and 16 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 20200219453 A1), and further in view of Kim et al. (US 20160043159 A1) and Lee et al. (US 20200144346 A1).
Regarding independent claim 1, Park teaches a display panel, comprising
a base substrate (Fig. 3; substrate 10), a plurality of subpixels (Fig. 1; plurality of pixels PX), a respective subpixel comprising a respective light emitting element ([0160] teaches that pixels include an organic light emitting diode OLED) and a respective pixel driving circuit (Fig. 20; circuit including driving voltage line 181 and driving transistor T1. See [0159] – [0161]);
wherein the respective pixel driving circuit comprises:
a third transistor ([0160] teaches first through third transistor T1 – T3. Examiner is interpreting second transistor T2 to be analogous to the instant third transistor);
a driving transistor ([0161] and [0169] teach driving transistor T1); and
a storage capacitor (Fig. 20; storage capacitor Cst. Further, Park teaches storage capacitor Cst in Fig. 21. See [0182]) comprising a first capacitor electrode (Fig. 21; first electrode cap-1) in a first conductive layer ([0185] teaches first electrode cap-1 included gate conductive layer) and a second capacitor electrode (Fig. 21; second electrode cap-2) in a second conductor layer ([0186] – [0188]);
wherein the second conductive layer is on a side of the first conductive layer away from the base substrate (Fig. 21);
a source electrode of the third transistor is connected to a drain electrode of the driving transistor (Park: Fig. 20 and [0172]);
the second capacitor electrode comprises an extension (Fig. 21; output electrode DD is considered to be an extension) extending away from an electrode main body of the second capacitor electrode (Fig. 21); …
However, Park remains silent regarding the display panel further comprising:
… an orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate; and
the orthographic projection of the extension on the base substrate is non-overlapping with an orthographic projection of a reset control signal line controlling a reset transistor of the respective pixel driving circuit on the base substrate.
However, in the same field of endeavor, Kim teaches a second storage capacitor plate 127 (Fig. 5 and [0060]). As Park does not clearly disclose the shape of the second capacitor electrode, Kim may supplement the deficiency of Park for at least what is disclosed regarding Kim’s display device circuitry in [0057] - [0060]. This may be motivated by the transistor circuitry around the storage capacitor, as shown in Fig. 11 of Kim with relationship to the second storage capacitor plate 127 and TFT T3, wherein an orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate (Fig. 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s second capacitor electrode to include extension shapes wherein an orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate, as disclosed by Kim (Fig. 11), because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Kim’s second capacitor electrode is comparable to Park’s second capacitor electrode because they both function as storage capacitor electrodes for pixel driving circuitry. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s second capacitor electrode to include extension shapes wherein an orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the respective pixel driving circuit on the base substrate, as disclosed by Kim (Fig. 11), with the predictable result of forming a shield layer (Kim: [0079])
Further, in the same field of endeavor, Lee teaches a similar pixel circuit (Fig. 2; pixel circuit area PA) wherein the pixel circuit includes a third transistor T3 (understood to be a reset transistor from at least Fig. 1, [0049], and [0067]); such that Lee’s third transistor T3 may be considered a reset transistor of the respective pixel driving circuit on the base substrate. Lee’s third transistor T3 includes line (Fig. 2; third voltage line VL3) connected to a control electrode CE3; such that that Lee’s third voltage line VL3 may be considered a control signal line. Further, Lee teaches their reset transistor spaced from the capacitor plates (Fig. 2; first capacitor Cst including a first capacitor electrode CSE1 and a second capacitor electrode CSE2) in a top down view in Fig. 2. Examiner asserts that Lee’s second transistor T2 is analogous to Park’s second transistor T2, i.e., the third transistor, because they both function as switching transistors; and Lee’s first transistor T1 is comparable to Park’s driving transistor T1, because they both function as driving transistors. Since the circuits structure around the pixels between the disclosures is similarly designed, Lee’s disclosed pixel circuit structure, including reset circuitry, may be used to modify Park’s pixel circuit structure such that the orthographic projection of the extension on the base substrate is non-overlapping with an orthographic projection of a reset control signal line controlling a reset transistor of the respective pixel driving circuit on the base substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the pixel circuit structure of Park, further in view of Kim, to include reset transistors connected to reset control signal lines, as disclosed by Lee, such that the orthographic projection of the extension on the base substrate is non-overlapping with an orthographic projection of a reset control signal line controlling a reset transistor of the respective pixel driving circuit on the base substrate, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, the pixel circuit structure of Park, further in view of Kim, as modified by Lee’s reset circuitry can yield a predictable result of adding reset function, such that the pixel associated with the reset circuitry may be reset. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Regarding dependent claim 2, Park, further in view of Kim and Lee, teach the display panel of claim 1, wherein
the third transistor comprises a first gate electrode ([0172] of Park teaches the transistor T2 including a gate electrode) and …
However, Park remains silent regarding:
… a second gate electrode;
an orthographic projection of the first gate electrode on the base substrate overlaps with an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate;
an orthographic projection of the second gate electrode on the base substrate overlaps with an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate;
the active layer of the third transistor further comprises a portion connecting the first channel part and the second channel part; and
the orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel part and the second channel part on the base substrate.
However, in the same field of endeavor, Lee discloses a transistor T2 analogous to Park’s switching transistor; however, Lee’s second transistor T2 has a dual gate electrode structure ([0066] and Fig. 2). Examiner asserts that Park’s switching transistor may be modified in a similar way to Lee’s dual gate electrode structure, such that Park’s switching transistor may be a dual gate transistor including a second gate electrode. This would mean modifying the active layer manufacturing process such that a dual gate transistor may be formed, a method of manufacturing known within the art. This further would yield a second channel part of the active layer such that an orthographic projection of the first gate electrode on the base substrate overlaps with an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate and an orthographic projection of the second gate electrode on the base substrate overlaps with an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate. Due to the structure of dual gate transistors, a portion between the first channel part and the second channel part may be interpreted as a connecting portion such that the active layer of the third transistor further comprises a portion connecting the first channel part and the second channel part, such as the example shown in Lee’s Fig. 2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s third transistor to include a dual gate structure, as disclosed by Lee’s second transistor T2, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Lee’s dual gate transistor, i.e., second transistor T2, is comparable to Park’s third transistor because they function as switching transistors. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s switching transistor to include a dual gate structure such as Lee’s switching transistor, i.e., second transistor T2, with the predictable result of modifying Park’s third transistor to include a first gate electrode and a second gate electrode wherein an orthographic projection of the first gate electrode on the base substrate overlaps with an orthographic projection of a first channel part of the active layer of the third transistor on the base substrate and an orthographic projection of the second gate electrode on the base substrate overlaps with an orthographic projection of a second channel part of the active layer of the third transistor on the base substrate; and the active layer of the third transistor further comprises a portion connecting the first channel part and the second channel part.
Further, in the same field of endeavor, Kim’s second storage capacitor plate 127 that has an extension portion overlapping a connection portion (Fig. 11; transistor T3); such that Kim discloses the structural feature wherein the orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel part and the second channel part on the base substrate (Kim: Fig. 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the second capacitor electrode of Park and Kim, to include extension shapes wherein the orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel part and the second channel part on the base substrate, as disclosed by Kim (Fig. 11), because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Kim’s second capacitor electrode is comparable to Park’s second capacitor electrode because they both function as storage capacitor electrodes for pixel driving circuitry. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s second capacitor electrode to include extension shapes wherein the orthographic projection of the extension on the base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel part and the second channel part on the base substrate, as disclosed by Kim (Fig. 11), with the predictable result of forming a shield layer (Kim: [0079]).
Regarding dependent claim 3, Park, further in view of Kim and Lee, teach the display panel of claim 1, further comprising
a first signal line layer (Park: data conductive layer taught in [0188]) on a side of the storage capacitor away from the base substrate (Park: Fig. 21 and [0188]);
wherein multiple second capacitor electrodes respectively from multiple pixel driving circuits are sequentially connected to each other along a first direction (Park: Fig. 20, further in view of Figs. 1 and 19);
the first signal line layer comprises a plurality of first high voltage signal lines (Park: Fig. 19; horizontal driving voltage line 181′) respectively along a first direction (Park: Fig. 19); and
a respective one of the plurality of first high voltage signal lines is connected to the second capacitor electrode (Park: Figs. 20 – 21; also [0154] and [0157]).
Regarding dependent claim 11, Park, further in view of Kim and Lee, teach the display panel of claim 1, further comprising
a plurality of second low voltage signal lines (Park: driving low-voltage lines 182 taught in [0054]) respectively along a second direction in a second signal line layer (Park: Fig. 21);
wherein the plurality of second low voltage signal lines are electrically connected to a cathode (Park: Fig. 21; cathode 410) of a light emitting element (Park: Fig. 21).
Regarding dependent claim 12, Park, further in view of Kim and Lee, teach the display panel of claim 1, further comprising:
a plurality of first high voltage signal lines (Park: driving voltage line 181′ in [0153]) respectively extending along the first direction in a first signal line layer (Park: Fig. 19); and
a plurality of second high voltage signal lines (Park: driving voltage line 181 in [0153]) respectively extending along a second direction in a second signal line layer (Park: Fig. 19);
wherein the plurality of first high voltage signal lines respectively cross over the plurality of second high voltage signal lines (Park: Fig. 19);
a respective one of the plurality of first high voltage signal lines is connected to at least multiple ones of the plurality of second high voltage signal lines through vias (Park: See [0154]; wherein the opening is interpreted to be a via); and
a respective one of the plurality of second high voltage signal lines is connected to at least multiple ones of the plurality of first high voltage signal lines through vias (Park: [0154] and [0157]).
Regarding dependent claim 13, Park, further in view of Kim and Lee, teach the display panel of claim 12, wherein a respective one of the plurality of first high voltage signal lines comprises:
a main body extending along a first direction (driving voltage line 181 shown in Fig. 1); …
However, Park remains silent regarding:
… a protrusion protruding away from the main body along a second direction, and
wherein the protrusion is a portion where the respective one of the plurality of second high voltage signal line is connected to a respective one of the plurality of first high voltage signal lines through one or more vias.
However, in a different embodiment within the same disclose, Park does teach:
… a protrusion (Fig. 1; a peripheral driving voltage line 181-1) protruding away from the main body along a second direction (Fig. 1), and
wherein the protrusion is a portion where the respective one of the plurality of second high voltage signal line is connected to a respective one of the plurality of first high voltage signal lines through one or more vias (Fig. 15. See [0205]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s high voltage signal lines to include a protrusion, as disclosed in another embodiment disclosed by Park, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Park’s embodiment including a protrusion is comparable to Park’s embodiment shown in Fig. 19 because both structures allow for the formation of a grid network of high voltage signal lines. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s high voltage signal lines to include a protrusion, as disclosed in another embodiment disclosed by Park, with the predictable result of forming a grid network of high voltage signal lines.
Regarding dependent claim 14, Park, further in view of Kim and Lee, teach the display panel of claim 12, wherein
the respective pixel driving circuit further comprises a driving transistor (Park: driving transistor T1. See [0169]), and a node connecting line connecting a drain electrode of the third transistor with a gate electrode of the driving transistor (Park: Fig. 20 and [0172]);
wherein the drain electrode of the third transistor is connected to the gate electrode of the driving transistor (Park: Fig. 20 and [0172]);
a source electrode of the third transistor is connected to a drain electrode of the driving transistor (Park: Fig. 20); and
an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate covers an orthographic projection of the node connecting line on the base substrate (Park: Fig. 20).
Regarding dependent claim 16, Park, further in view of Kim and Lee, teach the display panel of claim 1, wherein the display panel comprises:
a plurality of light emitting elements (Park: [0160] teaches that pixels include an organic light emitting diode OLED); and
an interconnected first voltage supply network (Park: Fig. 19; driving low-voltage lines 182 and 182′; wherein [0157] teaches that driving low-voltage lines 182 and 182′ may have a network structure. Also see [0064]) configured to provide a first voltage signal to cathodes (Park: Fig. 21; cathode 410) of the plurality of light emitting elements (Park: See Fig. 21 and [0155]);
wherein the interconnected first voltage supply network comprises signal lines (Park: Fig. 19; driving low-voltage lines 182 and 182′) in a display area of the display panel (Park: Fig. 19), the display area being at least partially surrounded by a peripheral area (Park: Fig. 1; peripheral area 120);
the signal lines comprise a plurality of first signal lines (Park: Fig. 19; driving low-voltage lines 182) in a first signal line layer and a plurality of second signal lines (Park: Fig. 19; driving low-voltage lines 182′) in a second signal line layer (Park teaches in [0155] that the vertical driving low-voltage lines 182 are disposed in the data conductive layer, and the horizontal driving low-voltage lines 182′ are disposed in the data conductive layer or in another layer);
the display panel further comprises a planarization layer (Park: Fig. 21; organic insulation layer 15 is considered by the examiner to be a planarization layer) … ; and
the plurality of first signal lines are electrically connected to the plurality of second signal lines (Park teaches in [0155] that when the vertical driving low-voltage lines 182 and the horizontal driving low-voltage lines 182′ are disposed in different layers, they may be electrically connected with each other through an opening).
However, Park remains silent regarding the planarization layer …
between the first signal line layer and the second signal line layer.
However, examiner asserts that when Park teaches that the horizontal driving low-voltage lines 182′ are disposed in another layer, the obvious choice would be to form the horizontal driving low-voltage lines 182′ in the same layer as the anode (Fig. 21 and [0192]), i.e., on a side of the organic insulation layer 15 away from the substrate. Examiner understand this to be supported by the description in [0198] – [0199] of the embodiment shown in Fig. 22, wherein Park details a layer formed on the second interlayer insulation layer 14-1 that is called a second data conductive layer (also referred to as a pixel electrode layer in other embodiments). This is the obvious implication from Park’s teaching of the horizontal driving low-voltage lines 182′ being disposed in another layer, because of the connectivity required for the low driving voltage lines being connected with the cathode 410 (e.g., Figs. 21 and 22). Thus, it would have been obvious from the disclosure of Park to form a display panel including a planarization layer between the first signal line layer and the second signal line layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s interconnected first voltage supply network to include a planarization layer between the first signal line layer and the second signal line layer, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Park’s teaching of the signal lines in the interconnected first voltage supply network being in different conductive layers is comparable to Park’s teaching of the signal lines in the interconnected first voltage supply network being in the same conductive layer because they perform the same function. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s interconnected first voltage supply network to include a planarization layer between the first signal line layer and the second signal line layer with the predictable result of reducing the depth of a via, especially the reducing the depth at which the cathode of the pixels is disposed in the via.
Regarding dependent claim 17, Park, further in view of Kim and Lee, teach the display panel of claim 16; however, Park remains silent wherein the interconnected first voltage supply network comprises:
a plurality of first-first voltage signal lines respectively along a first direction; and
a plurality of second-first voltage signal lines respectively along a second direction;
wherein the plurality of first-first voltage signal lines respectively cross over the plurality of second-first voltage signal lines.
However, Park teaches another embodiment within their disclosure wherein:
a plurality of first-first voltage signal lines (peripheral driving low-voltage connection portions 182-1) respectively along a first direction (Fig. 1); and
a plurality of second-first voltage signal lines (Figs. 2 – 3 and 22; peripheral driving low-voltage horizontal connection portion 192 and interlayer low-voltage connection portion C-PXL are considered to be a plurality of second-first voltage signal lines) respectively along a second direction (Fig. 1);
wherein the plurality of first-first voltage signal lines respectively cross over the plurality of second-first voltage signal lines (Fig. 2).
See further description in [0078] – [0082]. Thus, examiner asserts that it would have been obvious, further in view of the disclosure of Park, to form a display panel wherein the interconnected first voltage supply network comprises a plurality of first-first voltage signal lines respectively along a first direction; and a plurality of second-first voltage signal lines respectively along a second direction; wherein the plurality of first-first voltage signal lines respectively cross over the plurality of second-first voltage signal lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s interconnected first voltage supply network to include first-first voltage signal lines and second-first voltage signal lines, as disclosed through another embodiment of Park, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Park’s teaching of first-first voltage signal lines and second-first voltage signal lines is comparable to Park’s teaching of the signal lines in the interconnected first voltage supply network shown in Fig. 19 of their disclosure. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s interconnected first voltage supply network to include first-first voltage signal lines and second-first voltage signal lines with the predictable result of reducing the depth of a via, especially the reducing the depth at which the cathode of the pixels is disposed in the via, providing easy connection of the driving low-voltage lines 182 to the cathode 410 ([0082]).
Regarding dependent claim 18, Park, further in view of Kim and Lee, teach the display panel of claim 17, wherein the interconnected first voltage supply network comprises
a first sub-network (Park: network formed by peripheral driving low-voltage connection portions 182-1 as disclosed in [0123]. Also see [0078] – [0082] and [0148]) formed by the plurality of first-first voltage signal lines (Park: peripheral driving low-voltage connection portions 182-1) and a second sub-network (Park: network formed by peripheral driving low-voltage connection portions 182-2 as disclosed in [0123]. Also see [0148]) formed by the plurality of second-first voltage signal lines (Park: peripheral driving low-voltage connection portions 182-2).
Regarding dependent claim 19, Park, further in view of Kim and Lee, teach the display panel of claim 17, wherein
a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines (Park: Fig. 2); and
a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines (Park: Fig. 2).
Regarding dependent claim 20, Park, further in view of Kim and Lee, teach the display panel of claim 17, wherein
the plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines interconnect through first vias respectively extending through the planarization layer (Park: Fig. 3), at least some of the first vias being in the display area (Park: Fig. 22);
a respective one of the plurality of first-first voltage signal lines is connected to at least multiple ones of the plurality of second-first voltage signal lines respectively through multiple first vias extending through the planarization layer (Park: Figs. 3 and 22); and
a respective one of the plurality of second-first voltage signal lines is connected to at least multiple ones of the plurality of first-first voltage signal lines respectively through multiple first vias extending through the planarization layer (Park: Figs. 3 and 22).
Claims 4 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 20200219453 A1), and further in view of Kim et al. (US 20160043159 A1), Lee et al. (US 20200144346 A1), and Eom (US 20220037437 A1).
Regarding dependent claim 4, Park, further in view of Kim and Lee, teach the display panel of claim 1; however, Park remains silent wherein
the extension comprises a first extension part along a second direction and a second extension part along a first direction;
the first extension part connects the second extension part with the electrode main body of the second capacitor electrode; and
an orthographic projection of the second extension part on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate.
However, in the same field of endeavor, Eom teaches a similar storage capacitor electrode CST wherein the storage capacitor may receive the voltage ELVDD (See [0056]. Also, see teaching of Eom’s first capacitor electrode 1310 (Fig. 9) configured to receive the voltage ELVDD from first power voltage line 1520, wherein first power voltage line 1520 is taught in [0107] to carry the voltage ELVDD). Examiner asserts that due to the similarity disclosed between the connectivity of Eom’s first capacitor electrode 1310 and Kim’s second capacitor electrode, the extension part disclosed by Kim (and thus the capacitor of Park and Kim) may be modified by Eom’s voltage line 1520 (Fig. 12) to have:
a first extension part (Eom: Fig. 12; portion of first power voltage line 1520 along the direction D2) along a second direction and a second extension part (Eom: Fig. 12; portion of first power voltage line 1520 along the direction D1) along a first direction;
the first extension part connects the second extension part with the electrode main body of the second capacitor electrode (Eom: Fig. 13); and
an orthographic projection of the second extension part on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate (Eom: Fig. 13; wherein Eom’s fourth dual transistors T4_1 and T4_2 is considered analogous to the instant third transistor. See Fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the extension part of Park, further in view of Kim, to include Eom’s extension part structure including a first extension part and a second extension part, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s extension part is comparable to the extension part of Park, further in view of Kim, because both may be configured to transmit/receive the voltage ELVDD. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the extension part of Park, further in view of Kim, to include Eom’s extension part structure including a first extension part and a second extension part with the predictable result of expanding the areas of which the extension part of the second electrode may cover over the substrate of the display device in order to provide further functionality of the extension part, such as shielding over transistor structures of the display panel.
Regarding dependent claim 5, Park, further in view of Kim, Lee, and Eom, teach the display panel of claim 4, however, Park remains silent wherein
the second extension part comprises a shielding portion and a non-shielding portion;
an orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate;
an orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; and
a line width of the shielding portion is greater than a line width of the non-shielding portion.
However, in the same field of endeavor, Eom discloses that the first voltage line 1520 may prevent a coupling phenomenon that may occur in the first initialization electrode extension part 1211 of the fourth transistor and the second initialization electrode extension part 1212 of the fourth transistor ([0116]); wherein the examiner understands the first voltage line 1520 preventing a coupling phenomenon to be a shielding function thereof. Thus, Eom’s extension part may be used to modify the extension part of Park, in view of Kim and Eom, to include:
the second extension part comprises a shielding portion (Eom: Fig. 13: portion of the second extension part overlapping initialization electrode extension part 1211) and a non-shielding portion (Eom: Fig. 13: portion of the second extension part overlapping dual transistor T3);
an orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate (Eom: Fig. 13);
an orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate (Eom: Fig. 13); and
a line width of the shielding portion is greater than a line width of the non-shielding portion (Eom: Fig. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the extension part of Park, further in view of Kim and Eom, to include Eom’s extension part structure wherein the second extension part comprises a shielding portion and a non-shielding portion; and further wherein an orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; an orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; and a line width of the shielding portion is greater than a line width of the non-shielding portion, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s extension part is comparable to the extension part of Park, further in view of Kim, because both may be configured to transmit/receive the voltage ELVDD. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the extension part of Park, further in view of Kim, to include Eom’s extension part structure including a second extension part wherein the second extension part comprises a shielding portion and a non-shielding portion; an orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; an orthographic projection of the non-shielding portion on the base substrate is non-overlapping with the orthographic projection of the active layer of the third transistor of the respective pixel driving circuit on the base substrate; and a line width of the shielding portion is greater than a line width of the non-shielding portion with the predictable result of expanding the areas of which the extension part of the second electrode may cover over the substrate of the display device in order to provide further functionality of the extension part, such as shielding over transistor structures of the display panel.
Regarding dependent claim 6, Park, further in view of Kim, Lee, and Eom, teach the display panel of claim 4, wherein
the respective pixel driving circuit further comprises (Park: Fig. 20 and [0172]);
wherein the drain electrode of the third transistor is connected to the gate electrode of the driving transistor (Park: Fig. 20 and [0172]); and
However, Park remains silent wherein:
… an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line.
However, in the same field of endeavor, Eom discloses a node connecting line via first compensation connection pattern 1450 (Fig. 11) connecting a drain electrode of the third transistor with a gate electrode of the driving transistor (transistor T1 in [0044]). Further, Eom’s Fig. 13 shows an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line. Thus, examiner asserts that Eom’s connectivity may be used to modify the display panel of Park, in view of Kim and Eom, to yield the display panel wherein an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the extension part of Park, further in view of Kim and Eom, to include Eom’s feature wherein an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s extension part is comparable to the extension part of Park, further in view of Kim, because both may be configured to transmit/receive the voltage ELVDD. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the extension part of Park, further in view of Kim and Eom, to include Eom’s feature wherein an orthographic projection of the first extension part on a line extending along the second direction at least partially overlaps with an orthographic projection of the node connecting line on the line with the predictable result of conserving space over the substrate of the display panel.
Regarding dependent claim 7, Park, further in view of Kim, Lee, and Eom, teach the display panel of claim 6, further comprising
a plurality of data lines (Park: Fig. 1; data lines 171); …
However, Park remains silent wherein:
… wherein the first extension part is between the node connecting line and a respective data line of the plurality of data lines.
However, in the same field of endeavor, Eom teaches plurality of data lines 1510, 2510, and 3510 ([0038] and Fig. 13); wherein the first extension part is between the node connecting line and a respective data line of the plurality of data lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the extension part of Park, further in view of Kim and Eom, to include Eom’s feature wherein the first extension part is between the node connecting line and a respective data line of the plurality of data lines, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s extension part is comparable to the extension part of Park, further in view of Kim, because both may be configured to transmit/receive the voltage ELVDD. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the extension part of Park, further in view of Kim and Eom, to include Eom’s feature wherein the first extension part is between the node connecting line and a respective data line of the plurality of data lines with the predictable result of conserving space over the substrate of the display panel.
Regarding dependent claim 8, Park, further in view of Kim and Lee, teach the display panel of claim 1, further comprising
a plurality of gate lines (Park: [0074] teaches gate lines. Also see [0160]); …
However, Park remains silent wherein:
… wherein a respective gate line of the plurality of gate lines comprises a plurality of metal blocks spaced apart from each other in a first conductive layer, and a metal line along a first direction in a first signal line layer, the metal line along the first direction being connected to the plurality of metal blocks through vias, respectively.
However, in the same field of endeavor, Eom teaches a similar display device including a plurality of gate lines, wherein a respective gate line (Fig. 6; line of initialization gate electrodes 1210, 2210, 3210, etc.) includes a plurality of metal blocks, e.g., initialization gate electrodes 1210, spaced apart from each other in a first conductive layer. Further, Eom teaches in Fig. 10 an initialization gate line 1420, i.e., a metal line along a first direction, that connects the plurality of metal blocks through a via (Fig. 11; third contact hole CNT3. See [0091]). Examiner asserts that Eom’s display device may be used to modify Park’s display device to yield the display device wherein a respective gate line of the plurality of gate lines comprises a plurality of metal blocks spaced apart from each other in a first conductive layer, and a metal line along a first direction in a first signal line layer, the metal line along the first direction being connected to the plurality of metal blocks through vias, respectively.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s gate lines to include a plurality of metal blocks, as disclosed by Eom, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Eom’s metal blocks is comparable to Park’s plurality of gate lines because they are both gate lines. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s gate lines to include a plurality of metal blocks, as disclosed by Eom, with the predictable result of conserving space of the substrate of the display panel by selectively forming the gate line as a plurality of metal blocks.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s gate line to include a structure wherein the gate line is formed of a plurality of metal blocks, as disclosed by Eom, because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Park’s gate line and Eom’s metal blocks perform the same general and predictable function, the predictable function being the function of a gate line. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself - that is in the substitution of Park’s gate line by replacing it with Eom’s metal blocks and metal line. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious before the effective filing date of the instant invention.
Regarding dependent claim 9, Park, further in view of Kim, Lee, and Eom, teach the display panel of claim 8, wherein
a respective metal block of the plurality of metal blocks has a L shape (Eom: Fig. 6);
an orthographic projection of a first channel part of the active layer (Eom: Figs. 5 – 7; a third channel region CA13) of the third transistor on the base substrate overlaps with an orthographic projection of a first metal portion of the respective metal block of the plurality of metal blocks on the base substrate (Eom: Fig. 7);
an orthographic projection of a second channel part of the active layer (Eom: Figs. 5 – 7; a fourth channel region CA14) of the third transistor on the base substrate overlaps with an orthographic projection of a second metal portion of the respective metal block of the plurality of metal blocks on the base substrate (Eom: Fig. 7); and
the first metal portion and the second metal portion are a first gate electrode and a second gate electrode of the third transistor (Eom: [0075] – [0077] and Fig. 7).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 20200219453 A1), and further in view of Kim et al. (US 20160043159 A1), Lee et al. (US 20200144346 A1), and Du et al. (US 20240206267 A1).
Regarding dependent claim 10, Park, further in view of Kim and Lee, teach the display panel of claim 1, however, Park remains silent on the display panel further comprising:
a plurality of first reset signal lines respectively along a first direction in a semiconductor material layer; and
a plurality of second reset signal lines respectively along a second direction in a second signal line layer;
wherein the plurality of first reset signal lines respectively cross over the plurality of second reset signal lines;
a respective one of the plurality of first reset signal lines is connected to at least multiple ones of the plurality of second reset signal lines through vias; and
a respective one of the plurality of second reset signal lines is connected to at least multiple ones of the plurality of first reset signal lines through vias.
However, in the same field of endeavor, Du teaches:
a plurality of first reset signal lines (Fig. 4A; reset control line 220/RST) respectively along a first direction in a semiconductor material layer (first conductive layer in [0097]); and
a plurality of second reset signal lines (Fig. 4E; reset voltage line 240/VT) … in a second signal line layer (second conductive layer in [104]); …
a respective one of the plurality of first reset signal lines is connected to at least multiple ones of the plurality of second reset signal lines through vias (Fig. 4C; second connecting electrode 232 connection with sixth transistor T6); and
a respective one of the plurality of second reset signal lines is connected to at least multiple ones of the plurality of first reset signal lines through vias (Fig. 4C; second connecting electrode 232 connection with sixth transistor T6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the reset circuitry of the display device of Park, further in view of Kim and Lee, to include a plurality of first reset signal lines and a plurality of second reset signal lines in the same structure as disclosed by Du, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Du’s plurality of first reset signal lines and plurality of second reset signal lines is comparable to Lee reset circuitry to which an initialization voltage is applied because both are configured to transmit an initialization voltage and reset display elements. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s display panel to include a plurality of first reset signal lines and a plurality of second reset signal lines, as disclosed by Du, with the predictable result of providing a reset functionality to the circuitry of the display panel.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over by Park et al. (US 20200219453 A1), and further in view of Kim et al. (US 20160043159 A1), Lee et al. (US 20200144346 A1), and Jung et al. (US 20170025492 A1).
Regarding dependent claim 15, Park, further in view of Kim and Lee, teach the display panel of claim 12; however, Park remains silent wherein
an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate.
However, in the same field of endeavor, Jung teaches a data line DA, considered by the examiner to be analogous to Park’s second high voltage signal line, an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate (Fig. 2; see dual gate transistor T4). Thus, examiner asserts that Jung’s disclosure may be used to modify the display panel of Park and Jung to yield the display panel wherein an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Park’s display panel to include Jung’s feature wherein an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Jung’s data line is comparable to Park’s second high voltage signal line because Jung discloses the data line DA may transmit a data voltage via a data signal ([0079]). Therefore, it is within the capabilities of one of ordinary skill in the art to modify Park’s display panel to include Jung’s feature wherein an orthographic projection of the respective one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate electrode of the third transistor on the base substrate with the predictable result of conserving space over the substrate of the display panel.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20210183914 A1 considered for first capacitor plate shape.
US 20200302877 A1 considered for its teaching of pixel driving circuitry.
US 20220077277 A1 considered for its teaching of pixel driving circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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