DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/23/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6 and 9-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Winkelhoff et al. (US 201120299636).
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With respect to claim 1, fig. 1 of Van Winkelhoff et al. (US 20120299636) discloses an apparatus, comprising: a common drain (6), a common source (12), and a common gate (24), respectively of a power semiconductor device (10); and paralleled transistor cells (14’s, i.e. 14 left most, 14 center, 14 right most) of the power semiconductor device, wherein: a configuration of a gate structure of a first respective transistor cell (14 left most) coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell (subsequent 14 center) coupled with the common gate; or a configuration of a first structure( R or C) coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a second structure (R’s or C’s, see [0058]) coupled between a second portion of the paralleled transistor cells and the common gate, wherein the first structure is a single discrete resistive element (R) or a single discrete capacitive element (C) and the second structure is a single element (here: R or C) wherein the first structure and the second structure differ in at least one of material, shape or dimensions, such that the first structure provides a first resistance or capacitance distinct from a second resistance or capacitance provided by the second structure. (Here, if the first structure is considered a single capacitor and the second structure is considered a single resistor or alternatively the first structure is considered a single resistor and the second structure is considered a single capacitor, they differ in material shape and dimensions)
With respect to claim 2, fig. 1 discloses the apparatus of claim 1, wherein the first structure( R or C) , responsive to the configuration of the first structure ( R or C), exhibits a first capacitance (C) or resistance (R)( see [0058]), and the second structure (R or C, see [0058]), responsive to the configuration of the second structure (R or C, see [0058]), exhibits a second capacitance or resistance, and wherein the first capacitance or resistance is different than the second capacitance or resistance.
With respect to claim 6, fig.1 discloses the apparatus of claim 1, wherein the paralleled transistor cells of the power semiconductor device comprise metal-oxide-semiconductor field-effect transistor cells (14 are mosfets).
With respect to claim 9, fig. 1 discloses the apparatus of claim 1, wherein the first structure ( R or C) is coupled between the common gate (at 24) and a gate of a transistor cell (14) of the first portion of the paralleled transistor cells (14’s), and the second structure (R or C, see [0058]) is coupled between the common gate (24) and a gate of a transistor cell (subsequent 14) of the second portion of the paralleled transistor cells (14’s).
With respect to claim 10, fig. 1 discloses the apparatus of claim 1, wherein a response of the first structure ( R or C) to a stimulus is different than a response of the second structure (R or C, see [0058]) to a further stimulus (see [0051]-[0058] describing the effect of the stimulus on the miller effect with regard to the transistors).
With respect to claim 11, fig. 1 discloses the apparatus of claim 10, wherein the stimulus is a gate-drain charge of a transistor cell (i.e. turning on or off of the power gating transistors as disclosed in [0055]) of the first portion of the paralleled transistor cells, and the further stimulus is a gate-drain charge of a transistor cell of the second portion of the paralleled transistor cells (seen as the variance of the transistors downstream).
With respect to claim 12, fig. 1 discloses the apparatus of claim 11, wherein the response of the first structure ( R or C) sets a rate-of-change in the gate-drain charge of the transistor cell of the first portion of the paralleled transistor cells, and the response of the second structure (R or C, see [0058])sets a rate-of-change in gate-drain charge of the transistor cell of the second portion of the paralleled transistor cells (see [0055]- [0058]).
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With respect to claim 13, fig. 1 produces a method, comprising: providing a turn OFF signal (see [0059]) to a common gate (24) of a power semiconductor device (10); turning OFF a first portion of paralleled transistor cells (14) of the power semiconductor device over a first time duration; and turning OFF a second portion (subsequent 14’s i.e center 14 or right most 14) of paralleled transistor cells of the power semiconductor device over a second time duration, wherein the first time duration is different than the second time duration (based on desired Miller effect), and wherein the first time duration is at least partially responsive to a first resistance or capacitance exhibited by operative coupling between the common gate and respective gates of the first portion of paralleled transistor cells wherein the operative couplings between the common gate and respective gates of the first portion comprise a first structure that is a single discrete resistive element (R) or a single discrete capacitive element (here this can be interpreted as the resistor R or the capacitor C), and the second time duration is at least partially responsive to a second resistance or capacitance exhibited by operative coupling b between the common gate and the respective gates of the second portion of paralleled transistor cells wherein the operative couplings between the common gate and respective gates of the second portion comprise a second structure that is a single discrete resistive element or a single discrete capacitive element and wherein the first resistance or capacitance is different from the second resistance or capacitance due to the difference in at least one of material, shape, or dimensions of structures coupling the common gate to the respective gates. (Here, if the first structure is considered a single capacitor or resistor and the second structure is considered multiple resistors or capacitors, the result is that the structures differ in shape, dimensions and if a resistor is seen as the first structure and a capacitor is seen as the second structure they differ in material as well). (Secondly, it is within the scope of the invention to vary the resistor and capacitor values and thus would also read on the newly added limitations.)
With respect to claim 14, fig. 1 produces the method of claim 13, wherein the first time duration is at least partially responsive to a first resistance or capacitance (R or C) exhibited by operative couplings between the common gate (24) and respective gates of the first portion of paralleled transistor cells (14’s) of the power semiconductor device (10), and the second time duration is at least partially responsive to a second resistance or capacitance (R or C) exhibited by operative couplings between the common gate (24) and respective gates of the second portion of paralleled transistor cells (14’s) of the power semiconductor device, wherein the first resistance or capacitance is different than the second resistance or capacitance.
With respect to claim 15, fig. 1 produces the method of claim 13, wherein a time duration to turn OFF the power semiconductor device is at least partially responsive to the first time duration and the second time duration (based on feedback).
With respect to claim 16, fig. 1 produces the method of claim 13, wherein the first time duration is at least partially responsive to a first resistance or capacitance (R or C) exhibited by a gate structure of a first respective transistor cell (14) coupled with the common gate (24), and the second time duration is at least partially responsive to a second resistance or capacitance (subsequent R or C) exhibited by a gate structure of a second respective transistor cell (14) coupled with the common gate(24), wherein the first resistance or capacitance is different than the second resistance or capacitance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Winkelhoff et al. (US 20120299636) in view of Beasor et. Al. (10832839).
With respect to claim 3, Van Winkelhoff discloses the apparatus of claim 1, but fails to disclose wherein the configuration of the first structure comprises a first material and the configuration of the second structure comprises a second material, wherein a resistivity exhibited by the first material is different than a resistivity exhibited by the second material.
Beasor et. Al. (10832839) discloses (col.1 lines 9-19) that the resistivity of the resistors are due to materials, shape, dimensions, etc.) It would be obvious to adjust/select different resistors having different materials, shapes, etc, to set the desired turn on/ turn off times of the transistors of Van Winkelhoff et al. as Van Winkelhoff discloses that the drive current output is dependent on the resistance values, (see [0058]).
With respect to claim 4, the combination above produces the apparatus of claim 1, wherein the configuration of the first structure ( R or C) comprises a first shape and the configuration of the second structure (R or C, see [0058]) comprises a second shape (different shapes for different resistances as taught by Beasor).
With respect to claim 5, the combination above produces the apparatus of claim 1, wherein the configuration of the first structure (R or C) comprises a first dimensions and the configuration of the second structure (R or C, see [0058]) comprises a second dimensions, wherein at least one of the first dimensions and the second dimensions are different. (different dimensions for different resistances as taught by Beasor).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Winkelhoff et al. (US 20120299636) in view of Arai (Us 9543453).
With respect to claim 7, Van Winkelhoff et al. discloses the apparatus of claim 1, but fails to disclose wherein the paralleled transistor cells of the power semiconductor device comprises silicon-carbide (SiC) transistor cells.
Arai discloses the benefits of SIC transistors over MOSFETs, in (col. 3 lines 36-41) disclosing that Sic’s have the advantage of having larger breakdown voltages.
It would have been obvious before the effective filing date of the claimed invention to substitute the MOSFETs of Van Winkelhoff for SICs for the purpose of having larger break down voltages.
With respect to claim 8, the combination above produces the apparatus of claim 7, wherein the SiC transistor cells comprise power metal–oxide–semiconductor field-effect transistor cells (SiC power MOSFETs as combined above).
Response to Arguments
Applicant's arguments filed 2/23/2025 have been fully considered but they are not persuasive.
With applicant’s argument that Van Winkelhoff does not anticipate claims 1 and 13 as amended, the Examiner disagrees. The first element can be conceived to be the discrete element of the capacitor and the second element can be conceived to be the resistor or vice versa making each first and second structure different discrete elements. Each are coupled as the claim requires.
With respect to the single discrete element, the first can be chosen to be the capacitor and the second as the resistor, reading on the claim language.
With respect to different architectures achieving different effects, the Examiner agrees, however the affects as noted would be obvious expedient. This is not relied on in the prima facie rejection.
With respect to applicant’s argument concerning coupled or or, the new configurations are still “coupled” as such and the elements can be chosen to meet the required parameters as discussed above.
With respect to the fifth argument, although not relied on, using different type of transistors would be sufficient to read on the claim language.
With respect to Beasor, the replacement would teach the requirements of claims 3-5 as the arguments with regard to the base claim still are maintained above.
With repsect to Arai, the combination would teach the structure above as the arguments with regard to the base claims are still maintained above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
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