Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 10-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Winkelhoff et al. (US 201120299636).
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With respect to claim 1, fig. 1 of Van Winkelhoof et al. (US 20120299636) discloses an apparatus, comprising: a common drain (6), a common source (12), and a common gate (24), respectively of a power semiconductor device(10); and paralleled transistor cells (14;s, i.e. 14 left most, 14 center, 14 right most) of the power semiconductor device, wherein: a configuration of a first structure (14 left most and C) coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a second structure (subsequent 14 center R) coupled between a second portion of the paralleled transistor cells and the common gate, wherein the first structure ( C) is a single discrete resistive element or a single discrete capacitive element (C) coupled between the common gate (via intervening R, 20, 22 and 24) and a gate of a transistor cell of the first portion of the paralleled transistor cells (14 left most) and the second structure is a single discrete resistive element (R) or a single discrete capacitive element coupled between the common gate (via R, R 20, 22 and 24) and a gate of a transistor cell of the second portion of the paralleled transistor cells (subsequent 14 center), wherein the first structure and the second structure differ in at least one of material, shape, or dimensions, such that the first structure provides a first resistance or capacitance distinct from a second resistance or capacitance provided by the second structure. (See [0058]).
With respect to claim 2, fig. 1 discloses the apparatus of claim 1, wherein the apparatus of claim 1, wherein the first structure (R), responsive to the configuration of the first structure (C), exhibits a first capacitance or resistance (C), and the second structure (R), responsive to the configuration of the second structure (R), exhibits a second capacitance or resistance, and wherein the first capacitance or resistance is different than the second capacitance or resistance.
With respect to claim 3, fig.1 discloses the apparatus of claim 1, wherein the configuration of the first structure (C) comprises a first material and the configuration of the second structure (R) comprises a second material, wherein a resistivity exhibited by the first material is different than a resistivity exhibited by the second material. (see 0058).
With respect to claim 4, fig. 1 discloses the apparatus of claim 1, wherein the configuration of the first structure (C) comprises a first shape and the configuration of the second structure (R) comprises a second shape.
With respect to claim 5, fig. 1 discloses the apparatus of claim 1, wherein the configuration of the first structure (C) comprises a first dimensions and the configuration of the second structure (R) comprises a second dimensions, wherein at least one of the first dimensions and the second dimensions are different.
With respect to claim 6, fig. 1 discloses the apparatus of claim 1, wherein the paralleled transistor cells of the power semiconductor device comprise metal-oxide-semiconductor field-effect transistor cells (14s are mosfets).
With respect to claim 10, fig. 1 discloses the apparatus of claim 1, wherein a response of the first structure to a stimulus is different than a response of the second structure to a further stimulus (see [0058]) (Each is the structure is the summation of others before based on Miller effect).
With respect to claim 11, fig. 1 discloses the apparatus of claim 10, wherein the stimulus is a gate-drain charge of a transistor cell (i.e. turning on or off of the power gating transistors as disclosed in [0055]) of the first portion of the paralleled transistor cells, and the further stimulus is a gate-drain charge of a transistor cell of the second portion of the paralleled transistor cells (seen as the variance of the transistors downstream).
With respect to claim 12, fig. 1 discloses the apparatus of claim 11, wherein the response of the first structure (C) sets a rate-of-change in the gate-drain charge of the transistor cell of the first portion of the paralleled transistor cells, and the response of the second structure (R see [0058]) sets a rate-of-change in gate- drain charge of the transistor cell of the second portion of the paralleled transistor cells (see [0055]-[0058]).
With respect to claim 13, fig. 1 produces a method, comprising: providing a turn OFF signal (see[0059]) to a common gate (24) of a power semiconductor device (10); turning OFF a first portion of paralleled transistor cells (14) of the power semiconductor device over a first time duration; and turning OFF a second portion (subsequent 14’s i.e center 14 or right most 14) of paralleled transistor cells of the power semiconductor device over a second time duration, wherein the first time duration is different than the second time duration, (based on desired Miller effect) and wherein the first time duration is at least partially responsive to a first resistance or capacitance exhibited by operative couplings between the common gate and respective gates of the first portion of paralleled transistor cells, wherein the operative couplings between the common gate and respective gates of the first portion comprise a first structure that is a single discrete resistive element or a single discrete capacitive element (C), and the second time duration is at least partially responsive to a second resistance (R) or capacitance exhibited by operative couplings between the common gate and respective gates of the second portion of paralleled transistor cells, wherein the operative couplings between the common gate and respective gates of the second portion comprise a second structure (R) that is a single discrete resistive element or a single discrete capacitive element, and wherein the first resistance or capacitance is different from the second resistance or capacitance due to differences in at least one of material, shape, or dimensions of structures coupling the common gate to the respective gates.
With respect to claim 14, fig. 1 produces the method of claim 13, wherein the first time duration is at least partially responsive to a first resistance or capacitance (C) exhibited by operative couplings between the common gate (24) and respective gates of the first portion of paralleled transistor cells (14’s) of the power semiconductor device, and the second time duration is at least partially responsive to a second resistance (R) or capacitance exhibited by operative couplings between the common gate and respective gates of the second portion of paralleled transistor cells of the power semiconductor device, wherein the first resistance or capacitance is different than the second resistance or capacitance.
With respect to claim 15, fig. 1 produces the method of claim 13, wherein a time duration to turn OFF the power semiconductor device is at least partially responsive to the first time duration and the second time duration (based on feedback).
With respect to claim 16, fig 1 produces the method of claim 13, wherein the first time duration is at least partially responsive to a first resistance or capacitance (C) exhibited by a gate structure of a first respective transistor cell (14) coupled with the common gate (24), and the second time duration is at least partially responsive to a second resistance (R) or capacitance exhibited by a gate structure of a second respective transistor cell coupled with the common gate (24), wherein the first resistance or capacitance is different than the second resistance or capacitance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Winkelhoff et al. (US 20120299636) in view of Arai (US 9543453).
With respect to claim 7, fig. 1 discloses the apparatus of claim 1, but fails to disclose wherein the paralleled transistor cells of the power semiconductor device comprises silicon-carbide (SiC) transistor cells.
Arai discloses the benefits of SIC transistors over MOSFETSs, in (col. 3 lines 36-41) disclosing that SIC’s have the advantage of having larger breakdown voltages.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute the MOSFETs of Van Winkellhoff for SICs for the purpose of having larger breakdown voltages.
With respect to claim 8, the combination above produces the apparatus of claim 7, wherein the SiC transistor cells comprise power metal-oxide-semiconductor field-effect transistor cells (SIC power MOSFETs as combined above).
Response to Arguments
Applicant's arguments filed 6/17/2026 have been fully considered but they are not persuasive.
With respect to Applicant’s argument that Van Winkeloff does not disclose a first structure that is a discrete element, the first structure is disclosed as a capacitance.
With respect to Applicant’s argument that Van Winkelhoff does not disclose a single discrete resistive element, the second structure is a resistor. A resistor differs in material, size and dimension than a capacitor.
With respect to Applicant’s argument that there is no difference in shape material or size, resistors differ in size, material and dimension than capacitors.
With respect to capacitor as first element and resistor as second, the reading tracks with anticipation of claim 1. A shape of a capacitor as well as the shape of a resistor would are different as well as the material and size.
With respect to claims 3-5, with the amended presentation these claims directly read on Van Winkelhoff.
With respect to the rejection of Arai, are is brought in to disclose the benefits of SIC. Adapting Van Winkelhoff with Arai therefore teaches a combination as disclosed in claim 7 and 8.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)-270-3684 M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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