DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 08/10/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 08/10/2026 in reply to the final rejection mailed on 06/10/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 21 is added. According, pending in this Office action are Claims 1-5 & 21.
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21 recites “wherein the at least one section and the at least another section are engage with one another…” the limitation “engage” is a minor spelling error.
Appropriate correction is required.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, & 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang (US 20220320046).
Regarding Claim 1, Chang (see, e.g., figs. 1a-b, figs. 2a-b, fig. 3, see, e.g., fig. 5) shows a semiconductor package, comprising:
at least one section 10 (see, e.g., figs. 1a-b, para.0034) having
at least one die 100 (see, e.g., para.0041)
and at least one electrical structure 150 (see, e.g., para.0048) operably engaged directly with the at least one die;
and at least another section 20 (see, e.g., figs. 2a-b, para.0052) having
at least another die 200 (see, e.g., para.0058)
and at least another electrical structure 240 (see, e.g., para.0067) operably engaged directly with the at least another die (see, e.g., fig. 5, para.0079);
wherein the at least one electrical structure 150 and the at least another electrical structure 240 each include
a first electrical engaging surface (bottom surface of 150, top surface of 240)
and a second electrical engaging surface (top surface of 150, bottom surface of 240) that is opposite to the opposite to the first electrical engaging surface (top and bottom surfaces of the elements are opposites, see, e.g., fig. 5)
wherein the second electrical engaging surface of the at least one electrical structure (top surface of 150) is directly connected to the second electrical engaging surface of the at least another electrical structure (bottom surface of 240)
such that there are no intervening features or elements presented between the second electrical engaging surfaces (direct physical contact as a result of direct metal-to-metal bonding of 150 & 240, see, e.g., fig. 5, para.0079)
Regarding Claim 2, Chang shows the semiconductor package of claim 1,
wherein the at least one section 10 comprises:
at least one compliant support structure 160 (see, e.g., para.0049) operably engaged with the at least one die 100 and the at least one electrical structure 150;
wherein the at least one die 100 and the at least one electrical structure 150 are encased by the at least one compliant support structure 160 (encapsulating 100 & 160 with 108 & 110 surrounding the die, see, e.g., fig. 1b).
Regarding Claim 4, Chang shows the semiconductor package of claim 2,
wherein the at least another section 20 comprises:
at least another compliant support structure 260 (see, e.g., para.0066) operably engaged with the at least another die 200 and the at least another electrical structure 240;
wherein the at least another die 200 and the at least another electrical structure 240 are encased by the at least another compliant support structure 260 (encapsulating 200 & 260 with 208 & 210 surrounding the die, see, e.g., fig. 2 b).
Regarding Claim 21, Chang shows the semiconductor package of claim 1,
wherein the at least one section 10 and the at least another section 20 are engage with one another via wafer bonding of the at least one electrical structure 150 and the at least another electrical structure 240 (the cross section in fig. 5 shows the individual connection between dies of 10 & 20 in the entire wafer bonded structure 30 in fig. 3, see, e.g., fig. 3, fig. 5, para.0068, para.0070, para.0079);
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220320046) in view of Lai (US 20200105641).
Regarding Claim 3, Chang shows the semiconductor package of claim 2,
Chang, however, fails to show
wherein the at least one compliant support structure is a non-stochastic lattice structure -that forms about the at least one die.
Lai (see, e.g., fig. 1a, para.0022), in a similar device to Chang, states a configuration wherein the at least another compliant support structure 130 is a crystalline resin (crystalline resin, crystalline structure is the non-stochastic lattice structure) encapsulating the die 110 of a semiconductor package and would improve heat resistance of the device.
The configuration of Lai is incorporated into the device of Chang.
It would have been obvious to one of ordinary skill in the art to incorporate the configuration of Lai, in the device of Chang, to improve heat resistance of the device.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220320046) in view of Yu (US 20200402920).
Regarding Claim 5, Chang shows the semiconductor package of claim 4,
wherein the at least another compliant support structure further includes a stochastic structure or a non-stochastic structure.
Chang, however, fails to show
wherein the at least another compliant support structure further includes a stochastic structure.
Yu (see, e.g., fig. 4, para.0041-0042), in a similar device to Chang, states a configuration wherein the at least another compliant support structure 170 includes a stochastic structure (the open foam cell structure shown in figs. 5-6) encapsulating the die of a semiconductor package and would provide structural support to abate warpage of the device.
The configuration of Yu is incorporated into the device of Chang.
It would have been obvious to one of ordinary skill in the art to configuration of Yu, in the device of Chang, to provide structural support to abate warpage of the device.
Response to Arguments
Applicant’s arguments, see page 1, filed 08/10/2026, with respect to the rejection of claim 1 under 35 U.S.C. 112 (b) have been fully considered and are persuasive. The rejection of claim 1 under 35 U.S.C. 112 (b) has been withdrawn.
Applicant’s arguments filed on 08/10/2026 with respect to claim(s) 1-5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
