Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Authorization for Internet Communications in a Patent Application
Applicant is encouraged to file an Authorization for Internet Communications in a Patent Application form (http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) along with the response to this office action to facilitate and expedite future communication between Applicant and the examiner. If the form is submitted then Applicant is requested to provide a contact email address in the signature block at the conclusion of the official reply.
Claim Objections
As per claim 20, in ll. 5, “active” should be “activate”. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (an abstract idea) without significantly more.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 1. A method comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
determining an interrupt flag has been set indicative of a request to interrupt execution of a first inference model in favor of a second inference model (abstract idea mental process);
in response to determining that the interrupt flag has been set, determining a time to reach a preemptable boundary of the first inference model (abstract idea mental process).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
by processing circuitry of a computing device (generic computing components);
preempting the first inference model in favor of the second inference model based on whether the time to reach the next preemptable boundary exceeds an allowable breathing time of the second inference model (generic computing components performing extra-solution activity of saving/storing/recording data/information e.g., at least [0026], [0029]-[0030], and [0037] of the instant specification disclose storing and reloading context data of a reactivated inference model from memory to on-chip memory).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
by processing circuitry of a computing device;
preempting the first inference model in favor of the second inference model based on whether the time to reach the next preemptable boundary exceeds an allowable breathing time of the second inference model (extra-solution activity of saving/storing/recording data/information e.g., at least [0026], [0029]-[0030], and [0037] of the instant specification disclose storing and reloading context data of a reactivated inference model from memory to on-chip memory).
Claim 2. The method of claim 1 wherein the preempting occurs at the preemptable boundary when the time to reach the preemptable boundary does not exceed the allowable breathing time of the second inference model (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 3. The method of claim 2 wherein the preempting occurs before reaching the preemptable boundary when the time to reach the preemptable boundary exceeds the allowable breathing time of the second inference model (extra-solution activity of merely reciting the words "apply it" or an equivalent with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using the computer as a tool to perform the abstract idea).
Claim 4. The method of claim 3 further comprising identifying preemptable boundaries of the first inference model based on performance characteristics of each of the multiple layers of the first inference model and an allowable breathing time of a higher-priority inference model (abstract idea mental process).
Claim 5. The method of claim 4 wherein the performance characteristics include a context size and a processing time of each of the layers (abstract idea mental process).
Claim 6. The method of claim 1 wherein the allowable breathing time of the second inference model comprises a difference between an execution time of the second inference model and a tolerable latency of the second inference model (abstract idea mental process).
Claim 7. The method of claim 1 wherein the preempting includes deactivating the first inference model and activating the second inference model, and wherein the method further comprises, by the processing circuitry, re-activating the first inference model after completion of the second inference model (extra-solution activity of saving/storing/recording data/information e.g., at least [0026], [0029]-[0030], and [0037] of the instant specification disclose storing and reloading context data of a reactivated inference model from memory to on-chip memory).
As per claim 8, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 9, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 10, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 11, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
As per claim 12, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 13, it has similar limitations as claim 6 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 15. An embedded system comprising.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
determine that an interrupt flag has been set indicative of a request to interrupt execution of a first inference model in favor of a second inference model (abstract idea mental process);
in response to determining that the interrupt flag has been set, determine time to reach a preemptable boundary of the first inference model (abstract idea mental process).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
a sensor interface (generic computing components) configured to receive input data from an array of sensors (generic computing components performing extra-solution activity of receiving data/information) and set interrupt flags to indicate an arrival of the input data (generic computing components performing extra-solution activity of saving/storing/recording data/information); and
a processor (generic computing components) configured to at least:
preempt the first inference model in favor of the second inference model based on whether the time to reach the preemptable boundary exceeds an allowable breathing time of the second inference model (generic computing components performing generic computing components performing extra-solution activity of saving/storing/recording data/information e.g., at least [0026], [0029]-[0030], and [0037] of the instant specification disclose storing and reloading context data of a reactivated inference model from memory to on-chip memory).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
a sensor interface configured to receive input data from an array of sensors (extra-solution activity of receiving data/information) and set interrupt flags to indicate an arrival of the input data (extra-solution activity of saving/storing/recording data/information); and
a processor configured to at least:
preempt the first inference model in favor of the second inference model based on whether the time to reach the preemptable boundary exceeds an allowable breathing time of the second inference model (generic computing components performing extra-solution activity of saving/storing/recording data/information e.g., at least [0026], [0029]-[0030], and [0037] of the instant specification disclose storing and reloading context data of a reactivated inference model from memory to on-chip memory).
As per claim 16, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 17, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claims 6 and 7 and is therefore rejected using the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu et al. (US 2023/0418677) (hereinafter Fadelu) in view of Engstrom et al. (US 2021/0141987) (hereinafter Engstrom as previously cited).
As per claim 1, Fadelu teaches the invention primarily as claimed including a method comprising:
by processing circuitry of a computing device (abstract integrated circuits and [0048] processors):
determining an interrupt flag has been set indicative of a request to interrupt execution of a first inference process in favor of a second inference process ([0019] each context including one or more inference processes that are to be executed on the system of ASICs and context switching between the inference processes; [0026]-[0027] preemption of an inferences process and switch active contexts and load the new inferences process to the ASICs and minimize a time delay between when the preemption is requested and when a preemption checkpoint is reached; [0029] receive interrupt to perform context switching between inference processes; [0034] identified data synchronization points can be flagged as usable preemption checkpoints; and [0075] synchronize on data through sync flag controls that are managed within compute tile. The sync flag controls manage concurrency between executions of different instruction types within compute tile);
in response to determining that the interrupt flag has been set, determining a time to reach a preemptable boundary of the first inference process ([0027] preemption checkpoints can be inserted into the inference process during compile time to ensure the inference process will reach a preemption checkpoint at a predetermined frequency e.g., every 10 ms or every 50 ms, etc. to minimize a time delay between when the preemption is requested by the job scheduler and when a preemption checkpoint is reached); and
preempting the first inference process in favor of the second inference process based on whether the time to reach the next preemptable boundary exceeds an allowable breathing time of the second inference process (fig. 2; [0032] if the process itself takes a maximum of 16.6 ms to complete, then a maximum time between preemption points in the process to be preempted must be 41.6 ms−16.6 ms=25 ms; and [0036] the expected maximum time delay is compared to the maximum allowable latency. If the maximum expected time delay is greater than the maximum allowable latency process then additional preemption checkpoints are inserted into the code to reduce the maximum expected time delay).
While Fadelu teaches inference processes, Fadelu does not explicitly teach inference models. However, Engstrom teaches inference models ([0105]-[0106] activate different inference models based on input detection).
Engstrom and Fadelu are both concerned with context switching in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom because the inference processes taught by Fadelu can be interpreted as part of the inference models taught by Engstrom.
As per claim 7, Fadelu further teaches wherein the preempting includes deactivating the first inference model and activating the second inference model, and wherein the method further comprises, by the processing circuitry, re-activating the first inference model after completion of the second inference model ([0029] scalar core sends an interrupt to job scheduler, which selects the next context to be activated, sends the next active context ID to the scalar core, which broadcasts the updated context ID to the ASICs. The ASICs can then begin computations on the newly loaded inference process. When the new inference process is complete, an end pointer instruction will indicate to the scalar core that the process is complete. The scalar core can then perform another context switch, in some implementations, switching back to the previous context).
As per claim 8, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
Claims 2-3 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Tucker et al. (US 10,055,369) (hereinafter Tucker).
As per claim 2, Fadelu in view of Engstrom do not explicitly teach wherein the preempting occurs at the preemptable boundary when the time to reach the preemptable boundary does not exceed the allowable breathing time of the second inference model.
However, Tucker teaches wherein the preempting occurs at the preemptable boundary when the time to reach the preemptable boundary does not exceed the allowable breathing time of the second inference model (fig. 4, blocks 414-416 when the latency tolerance does not exceed a threshold then send an indication to wake up an inactive processor identified as capable of servicing the interrupt).
Tucker and Fadelu are both concerned with context switching in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Tucker because it would provide a way for when a timer expires, for an interrupt controller to send an indication to wake up to processors in an idle or sleep state followed by sending indications of the interrupts to the processors. Therefore, the processors transition from a sleep state to a wake state based on interrupt servicing at a lower frequency as the interrupts are coalesced temporally. The less frequent transitions reduces power consumption.
As per claim 3, Tucker teaches wherein the preempting occurs before reaching the preemptable boundary when the time to reach the preemptable boundary exceeds the allowable breathing time of the second inference model (abstract an interrupt controller maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts).
As per claim 9, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 10, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Tucker in view of Croxford (US 2019/0385024).
As per claim 4, Fadelu further teaches identifying preemptable boundaries of the first inference model based on an allowable breathing time of a higher-priority inference model ([0003] and [0010] interrupt/preempt a long-running process with a higher priority process).
Fadelu in view of Engstrom in view of Tucker do not explicitly teach performance characteristics of layers of the first inference model.
However, Croxford teaches performance characteristics of layers of the first inference model ([0044] performance characteristic values may be determined respectively for each neural network system of the plurality of neural network systems, and the processing of further image data may be switched to the neural network system having the fewest layers that has a determined performance characteristic value within a predetermined tolerance of that determined for the neural network system last used to process image data).
Croxford and Fadelu are both concerned with neural networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Tucker in view of Croxford because it would provide a way for extra layers of a second neural network to be only used when the system is in a mode in which the second neural network is selected to process the image data, and when the first neural network detects an object but is unable to classify said object, e.g. above a predetermined probability threshold. Thus, the additional processing of the second neural network may be used more efficiently compared to processing all image data with the second neural network when it is selected based on the trigger. In cases where an object is not detected by the first neural network, the additional layers of the second neural network may not be used to process the image feature data, and so the associated additional processing may be saved. Furthermore, in cases where an object is detected by the first neural network and the additional layers of the second neural network are used to process the stored feature data, the processing of the image data using the initial layers of the second neural network may be bypassed, which may also increase processing efficiency.
As per claim 11, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Tucker in view of Croxford in view of Wang (US 2022/0121551).
As per claim 5, Fadelu in view of Engstrom in view of Tucker in view of Croxford do not explicitly teach wherein the performance characteristics include a context size and a processing time of each of the layers.
However, Wang teaches wherein the performance characteristics include a context size and a processing time of each of the layers ([0071] time information can be the same or different for different network layers, which is depending on a size of input data quantity or output data quantity of the different network layers. For the first time information, if data quantity of the input data of the network layer A is greater than that of the network layer B, the time used by the processor to perform the data stream 1 in a course of performing calculation on a network layer a is greater than the time used by the processor to perform the data stream 1 in a course of performing calculation on a network layer b. That is to say, the first time information corresponding to the network layer a is greater than the first time information corresponding to the network layer b).
Wang and Fadelu are both concerned with machine learning and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Tucker in view of Croxford in view of Wang because it would provide a way of calculating the runtime of a neural network on a processor provided that a time value of the processor corresponding to each tiling mode can be estimated without compiling the neural network. A tiling mode with a part of relatively smaller time value or with a time value smaller than a time cost threshold can be selected from a large number of tiling modes for compiling and deploying to obtain a corresponding processor, based on the time value of each processor. Then the processor is measured to determine the tiling mode used by the processor with the optimal processing performance, rather than needing to compile each tiling mode one by one. Thus, the compilation efficiency can be greatly improved.
As per claim 12, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Cheon et al. (US 2012/0253773) (hereinafter Cheon)
As per claim 6, Fadelu in view of Engstrom do not explicitly teach wherein the allowable breathing time of the second inference model comprises a difference between an execution time of the second inference model and a tolerable latency of the second inference model.
However, Cheon teaches wherein the allowable breathing time of the second inference model comprises a difference between an execution time of the second inference model and a tolerable latency of the second inference model ([0022] determine whether the difference between a simulation execution time and an actual time spent is within an allowable delay value, the real-time simulation determination unit compares the difference between a simulation execution time and an actual time spent with a preset allowable delay value so that the time taken owing to abstraction and a delay value generated in a previous simulation cycle do not affect the check of a current cycle).
Cheon and Fadelu are both concerned with computing networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Cheon because it would provide a way of constructing an optimized network simulation environment which guarantees a real-time network simulation by synchronizing the operation time between the real equipment and the network model. Constructing an optimized network simulation environment enables a real-time network simulation by simplifying the construction of a network model and lowering the fidelity of communication equipment models when the construction of the network model is complicated or when the necessary time taken to perform calculation for a network simulation is longer.
As per claim 13, it has similar limitations as claim 6 and is therefore rejected using the same rationale.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view Krauss et al. (US 2020/0147810) (hereinafter Krauss as previously cited) in view of VanBlon et al. (US 2018/0046495) (hereinafter VanBlon as previously cited).
As per claim 15, Fadelu teaches the invention primarily as claimed including an embedded system comprising:
a processor configured to at least (abstract integrated circuits and [0048] processors):
determine that an interrupt flag has been set indicative of a request to interrupt execution of a first inference process in favor of a second inference process ([0019] each context including one or more inference processes that are to be executed on the system of ASICs and context switching between the inference processes; [0026]-[0027] preemption of an inferences process and switch active contexts and load the new inferences process to the ASICs and minimize a time delay between when the preemption is requested and when a preemption checkpoint is reached; [0029] receive interrupt to perform context switching between inference processes; [0034] identified data synchronization points can be flagged as usable preemption checkpoints; and [0075] synchronize on data through sync flag controls that are managed within compute tile. The sync flag controls manage concurrency between executions of different instruction types within compute tile);
in response to determining that the interrupt flag has been set, determine a time to reach a preemptable boundary of the first inference process ([0027] preemption checkpoints can be inserted into the inference process during compile time to ensure the inference process will reach a preemption checkpoint at a predetermined frequency e.g., every 10 ms or every 50 ms, etc. to minimize a time delay between when the preemption is requested by the job scheduler and when a preemption checkpoint is reached); and
preempt the first inference process in favor of the second inference process based on whether the time to reach the next preemptable boundary exceeds an allowable breathing time of the second inference process (fig. 2; [0032] if the process itself takes a maximum of 16.6 ms to complete, then a maximum time between preemption points in the process to be preempted must be 41.6 ms−16.6 ms=25 ms; and [0036] the expected maximum time delay is compared to the maximum allowable latency. If the maximum expected time delay is greater than the maximum allowable latency process then additional preemption checkpoints are inserted into the code to reduce the maximum expected time delay).
Fadelu does not explicitly teach inference models, and a sensor interface configured to receive input data from an array of sensors and set interrupt flags to indicate the arrival of the input data.
However, Engstrom teaches inference models ([0105]-[0106] activate different inference models based on input detection).
Engstrom and Fadelu are both concerned with context switching in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom because the inference processes taught by Fadelu can be interpreted as part of the inference models taught by Engstrom.
Fadelu in view of Engstrom do not explicitly teach a sensor interface configured to receive input data from an array of sensors.
However, Krauss teaches a sensor interface configured to receive input data from an array of sensors ([0028] sensor data input can be an interface operable to receive sensor input data from a sensor array such as a microphone for recording sounds and voice commands from the user).
Krauss and Fadelu are both concerned with data manipulation in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Krauss because it would provide a way for accessible sensors that are best suited for a task to be selected as well as various settings, configurations, etc., of such sensors which can further enable a user to customize the performance of certain tasks performed based on the available sensors.
Fadelu in view of Engstrom in view of Krauss do not explicitly teach set interrupt flags to indicate the arrival of the input data.
However, VanBlon teaches set interrupt flags to indicate the arrival of the input data ([0064] interrupt active application responsive to a predefined voice command; [0074] interrupt cue is received from sensors and monitor/detect interrupt cues; [0077] monitor/detect interrupt cues).
VanBlon and Fadelu are both concerned with data manipulation in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Krauss in view of VanBlon because it would provide a way to improve the functionality and/or usability of the computer, computing technology, computing environment, or the like, by automatically interrupting one or more applications executing on a device in response to an interrupt cue, e.g., an individual speaking to the user of the device, an individual entering a room where the device is being used, or the like. In this manner, the user of the device may give an individual his/her full attention without being distracted with content, applications, sounds, games, or the like that are being consumed by the user on the user's device.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker.
As per claim 16, Fadelu in view of Engstrom in view of Krauss in view of VanBlon do not explicitly teach wherein the processor is configured to, when the time to reach the preemptable boundary does not exceed the allowable breathing time of the second inference model, preempt the first inference model in favor of the second inference model upon reaching the preemptable boundary.
However, Tucker teaches wherein the processor is configured to, when the time to reach the preemptable boundary does not exceed the allowable breathing time of the second inference model, preempt the first inference model in favor of the second inference model upon reaching the preemptable boundary (fig. 4, blocks 414-416 when the latency tolerance does not exceed a threshold then send an indication to wake up an inactive processor identified as capable of servicing the interrupt).
Tucker and Fadelu are both concerned with context switching in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker because it would provide a way for when a timer expires, for an interrupt controller to send an indication to wake up to processors in an idle or sleep state followed by sending indications of the interrupts to the processors. Therefore, the processors transition from a sleep state to a wake state based on interrupt servicing at a lower frequency as the interrupts are coalesced temporally. The less frequent transitions reduces power consumption.
As per claim 17, Tucker teaches wherein the processor is configured to, when the time to reach the preemptable boundary exceeds the allowable breathing time of the second inference model, preempt the first inference model in favor of the second inference model before reaching the preemptable boundary (abstract an interrupt controller maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker in view of Croxford.
As per claim 18, Fadelu further teaches wherein the processor is further configured to identify preemptable boundaries of the first inference model based on an allowable breathing time of a higher-priority inference model ([0003] and [0010] interrupt/preempt a long-running process with a higher priority process).
Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker do not explicitly teach performance characteristics of layers of the first inference model.
However, Croxford teaches performance characteristics of layers of the first inference model ([0044] performance characteristic values may be determined respectively for each neural network system of the plurality of neural network systems, and the processing of further image data may be switched to the neural network system having the fewest layers that has a determined performance characteristic value within a predetermined tolerance of that determined for the neural network system last used to process image data).
Croxford and Fadelu are both concerned with neural networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker in view of Croxford because it would provide a way for extra layers of a second neural network to be only used when the system is in a mode in which the second neural network is selected to process the image data, and when the first neural network detects an object but is unable to classify said object, e.g. above a predetermined probability threshold. Thus, the additional processing of the second neural network may be used more efficiently compared to processing all image data with the second neural network when it is selected based on the trigger. In cases where an object is not detected by the first neural network, the additional layers of the second neural network may not be used to process the image feature data, and so the associated additional processing may be saved. Furthermore, in cases where an object is detected by the first neural network and the additional layers of the second neural network are used to process the stored feature data, the processing of the image data using the initial layers of the second neural network may be bypassed, which may also increase processing efficiency.
Claim 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker in view of Croxford in view of Wang.
As per claim 19, Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker in view of Croxford do not explicitly teach wherein the performance characteristics include a context size and a processing time of each of the layers.
However, Wang teaches wherein the performance characteristics include a context size and a processing time of each of the layers ([0071] time information can be the same or different for different network layers, which is depending on a size of input data quantity or output data quantity of the different network layers. For the first time information, if data quantity of the input data of the network layer A is greater than that of the network layer B, the time used by the processor to perform the data stream 1 in a course of performing calculation on a network layer a is greater than the time used by the processor to perform the data stream 1 in a course of performing calculation on a network layer b. That is to say, the first time information corresponding to the network layer a is greater than the first time information corresponding to the network layer b).
Wang and Fadelu are both concerned with machine learning and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Tucker in view of Croxford in view of Wang because it would provide a way of calculating the runtime of a neural network on a processor provided that a time value of the processor corresponding to each tiling mode can be estimated without compiling the neural network. A tiling mode with a part of relatively smaller time value or with a time value smaller than a time cost threshold can be selected from a large number of tiling modes for compiling and deploying to obtain a corresponding processor, based on the time value of each processor. Then the processor is measured to determine the tiling mode used by the processor with the optimal processing performance, rather than needing to compile each tiling mode one by one. Thus, the compilation efficiency can be greatly improved.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Cheon.
As per claim 20, Fadelu further teaches wherein to preempt the first inference model in favor of the second inference model, the processor is further configured to deactivate the first inference model and active the second inference model, and wherein the processor is further configured to re-activate the first inference model upon completion of the second inference model ([0029] scalar core sends an interrupt to job scheduler, which selects the next context to be activated, sends the next active context ID to the scalar core, which broadcasts the updated context ID to the ASICs. The ASICs can then begin computations on the newly loaded inference process. When the new inference process is complete, an end pointer instruction will indicate to the scalar core that the process is complete. The scalar core can then perform another context switch, in some implementations, switching back to the previous context).
Fadelu in view of Engstrom in view of Krauss in view of VanBlon do not explicitly teach wherein the allowable breathing time of the second inference model comprises a difference between an execution time of the second inference model and a tolerable latency of the second inference model.
However, Cheon teaches wherein the allowable breathing time of the second inference model comprises a difference between an execution time of the second inference model and a tolerable latency of the second inference model ([0022] determine whether the difference between a simulation execution time and an actual time spent is within an allowable delay value, the real-time simulation determination unit compares the difference between a simulation execution time and an actual time spent with a preset allowable delay value so that the time taken owing to abstraction and a delay value generated in a previous simulation cycle do not affect the check of a current cycle).
Cheon and Fadelu are both concerned with computing networks and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fadelu in view of Engstrom in view of Krauss in view of VanBlon in view of Cheon because it would provide a way of constructing an optimized network simulation environment which guarantees a real-time network simulation by synchronizing the operation time between the real equipment and the network model. Constructing an optimized network simulation environment enables a real-time network simulation by simplifying the construction of a network model and lowering the fidelity of communication equipment models when the construction of the network model is complicated or when the necessary time taken to perform calculation for a network simulation is longer.
Response to Arguments
All of Applicant's arguments have been considered. The arguments pertaining to the 35 U.S.C. 103 prior art rejections are moot in view of the new ground(s) of rejection necessitated by Applicant’s amendments because the new ground(s) of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments directed to the 35 U.S.C. 101 abstract idea rejections have been fully considered but they are not persuasive.
In the Remarks on pg. 7, Applicant argues that the claims cannot be practically performed in the human mind because claim 1 is amended to indicate the method is performed by processing circuitry of the computing device. The examiner respectfully traverses. The instant specification provides evidence in at least [0085]-[0086] that the processing circuitry is a generic computing component (e.g., “The aforementioned media, connections, and devices are well known and need not be discussed at length here” and “The aforementioned communication networks and protocols are well known and need not be discussed at length here”). A claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry does not qualify as significantly more. The use of generic computer components to transmit information through an unspecified interface does not impose any meaningful limit on the computer implementation of the abstract idea. Thus, taken alone, the additional elements do not amount to significantly more than a judicial exception. Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology. Their collective functions merely provide for a conventional computer implementation. Merely adding generic computer components to perform the method is not sufficient. Thus, the claim must include more than mere instructions to perform the method on a generic component or machinery to qualify as an improvement to an existing technology. See MPEP § 2106.05(f) for more information about mere instructions to apply an exception. An abstract idea does not become non-abstract by limiting the invention to a particular field of use or technological environment, such as the Internet or a computer. Lastly eligibility should not be evaluated based on whether the claimed invention has utility, because utility is not the test for patent-eligible subject matter (see MPEP 2106). If a claim fails the Alice/Mayo test (i.e., is directed to an exception at Step 2A and does not amount to significantly more than the exception in Step 2B), then the claim is ineligible even if it passes the M-or-T test. DDR Holdings, LLC v. Hotels.com, L.P., 773 F.3d 1245, 1256, 113 USPQ2d 1097, 1104 (Fed. Cir. 2014) ("[I]n Mayo, the Supreme Court emphasized that satisfying the machine-to- transformation test, by itself, is not sufficient to render a claim patent-eligible, as not all transformations or machine implementations infuse an otherwise ineligible claim with an "inventive concept."). Similarly, a claimed process covering embodiments that can be performed on a computer, as well as embodiments that can be practiced verbally or with a telephone, cannot improve computer technology. See RecogniCorp, LLC v. Nintendo Co., 855 F.3d 1322, 1328, 122 USPQ2d 1377, 1381 (Fed. Cir. 2017) (process for encoding/decoding facial data using image codes assigned to particular facial features held ineligible because the process did not require a computer). To show that the involvement of a computer assists in improving the technology, the claims must recite the details regarding how a computer aids the method, the extent to which the computer aids the method, or the significance of a computer to the performance of the method. The Federal Circuit has also indicated that mere automation of manual processes or increasing the speed of a process where these purported improvements come solely from the capabilities of a general-purpose computer are not sufficient to show an improvement in computer-functionality (see FairWarning IP, LLC v. Iatric Sys., 839 F.3d 1089, 1095, 12 USPQ2d 1293, 1296 (Fed. Cir. 2016) and Credit Acceptance Corp. v. Westlake Services, 859 F.3d 1044, 1055, 123 USPQ2d 1100, 1108-09 (Fed. Cir. 2017)). Similarly, "claiming the improved speed or efficiency inherent with applying the abstract idea on a computer" does not provide an inventive concept (Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1367, 115 USPQ2d 1636, 1639 (Fed. Cir. 2015)) nor does merely using a computer to perform an abstract idea (Return Mail, Inc. v. U.S. Postal Service, -- F.3d --, --, -- USPQ2d --, -- slip op. at 33 (Fed. Cir. August 28, 2017). Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not provide significantly more. See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016) (computer server and telephone unit). Additionally, mental processes remain unpatentable even when automated to reduce the burden on the user of what once could have been done with pen and paper (see CyberSource, 654 F.3d at 1375 (“that purely mental processes can be unpatentable, even when performed by a computer, was precisely the holding of the Supreme Court in Gottschalk v. Benson”). It is notable that mere physicality or tangibility of an additional element or elements is not a relevant consideration in Step 2B. As the Supreme Court explained in Alice Corp., mere physical or tangible implementation of an exception is not in itself an inventive concept and does not guarantee eligibility: The fact that a computer "necessarily exist[s] in the physical, rather than purely conceptual, realm," is beside the point. There is no dispute that a computer is a tangible system (in § 101 terms, a "machine"), or that many computer-implemented claims are formally addressed to patent-eligible subject matter. But if that were the end of the § 101 inquiry, an applicant could claim any principle of the physical or social sciences by reciting a computer system configured to implement the relevant concept. Such a result would make the determination of patent eligibility "depend simply on the draftsman’s art," Flook, supra, at 593, 98 S. Ct. 2522, 57 L. Ed. 2d 451, thereby eviscerating the rule that "‘[l]aws of nature, natural phenomena, and abstract ideas are not patentable,’" Myriad, 133 S. Ct. 1289, 186 L. Ed. 2d 124, 133). Whether the claim recites only the idea of a solution or outcome i.e., the claim fails to recite details of how a solution to a problem is accomplished. The recitation of claim limitations that attempt to cover any solution to an identified problem with no restriction on how the result is accomplished and no description of the mechanism for accomplishing the result, does not provide significantly more because this type of recitation is equivalent to the words "apply it". See Electric Power Group, LLC v. Alstom, S.A., 830 F.3d 1350, 1356, 119 USPQ2d 1739, 1743-44 (Fed. Cir. 2016); Intellectual Ventures I v. Symantec, 838 F.3d 1307, 1327, 120 USPQ2d 1353, 1366 (Fed. Cir. 2016); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1417 (Fed. Cir. 2015) (see MPEP 2106.05(f)). Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
On pg. 7 of the Remarks, Applicant alleges that claim 1 is eligible because it sets forth a concrete scenario in which processing circuitry determines when to preempt the execution of a first inference model in favor of the execution of a second inference model. The examiner respectfully disagrees. Initially, it should be noted that setting “forth a concrete scenario” is not provided in MPEP 2106 as a valid reason for supporting claim eligibility. It appears that Applicant is suggesting that the supposed improvement allows processing circuitry to determine when to preempt the execution of a first inference model in favor of the execution of a second inference model (emphasis added by the examiner). Hence, Applicant is alleging that the supposed improvement is directed to an abstract idea of making a determination. Applicant’s attempt to show that the recited abstract idea is the improvement is not persuasive. An “improved” abstract idea is still an abstract idea nonetheless and is not eligible for patent protection without significantly more recited in the claim. The examiner respectfully submits that an improvement in computer functionality is a reason for supporting the significance of the additional elements in a claim (Step 2A Prong Two and Step 2B, and not Step 1 or Step 2A Prong One). In other words, the “improvement” rationale is reserved for evaluating whether the additional elements and not the abstract idea itself amount to significantly more than the abstract idea itself (see MPEP 2106.05). Applicant is reminded that the abstract idea itself cannot be directed to an improvement in computer functionality (Step 2A Prong One). Rather only the additional elements can qualify as significantly more (i.e., the improvement) than the abstract idea itself (Step 2A Prong Two and Step 2B). Contrary to Applicant’s assertion, the claims are not directed to a specific asserted improvement in computer capabilities because no capability of the computer is being improved in any way. Hence, for at least the rationale provided above, Applicant’s arguments are not persuasive and the rejections are maintained.
In the Remarks on pg. 7, Applicant argues that claim 1 provides a method for optimizing the execution of inference models within the context of multi-priority inference model environments. The examiner respectfully disagrees. It should be noted that none of the claims recite “a method for optimizing the execution of inference models within the context of multi-priority inference model environments”. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
On pg. 7 of the Remarks, Applicant alleges that the dependent claims are eligible at least due to their dependency from an eligible base claim. The examiner respectfully traverses. Applicant fails to interact with or address any of the examiner’s limitation-by-limitation analysis of the dependent claims provided in the rejection above. Applicant’s arguments fail to comply with 37 CFR 1.111(b)-(c) because they amount to a general allegation that the claims are eligible without specifically pointing out how the language of the claims makes the claims eligible in view of the rejections made. Further, they do not show how the amendments avoid such rejections. Applicant’s Remarks are only directed to the independent claims and fail to address any of the abstract idea rejections to the dependent claims. Even if an independent claims is deemed eligible then it does not necessarily mean that all of the dependent claims are also eligible. Hence, for at least the rationale provided above, Applicant’s arguments are not persuasive and the rejections are maintained.
In the Remarks on pg. 11, Applicant argues that there is no motivation to combine the cited prior art references. The examiner respectfully disagrees. In response to Applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). Thus, for at least the reasons provided above, Applicant’s arguments are unpersuasive and the rejections are sustained.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Rossi et al. (US 2020/0082273) in at least the abstract, [0065], and [0075] disclose switching from executing an operation from a lower priority neural network model to an operation of a higher priority neural network model.
Baldwin et al. (US 2023/0396435) in at least [0116] disclose context switching between different ML models.
Sethi et al. (US 2021/0406993) in at least [0046] and [0048] disclose resuming a training process of a ML model utilizing checkpointing.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached on 571-272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated-interview-request-air-form.
/Adam Lee/Primary Examiner, Art Unit 2198 March 10, 2026