DETAILED ACTION
This Office Action is in response to the amendments filed 05 January 2026. Claims 1, 5-15 are pending in this application. Claims 2-4 have been cancelled.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Applicant’s Amendments have addressed the prior 112B issue. Therefore, the prior 112b rejections are withdrawn.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 5, 8, 14 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Williams et. al (US 2025/0040456 A1) (of record).
Regarding Claim 1, Williams discloses (as shown in Fig. 2A-E, 3) A high frequency transistor ([0067] In this regard, FIG. 3 shows an example in which the die 205 includes a first transistor 280-1 and a second transistor 280-2.), comprising:
a substrate ([0045] substrate of the die 205);
a plurality of gates ([0069] the gates 120-1 to 120-7) extending along a first direction ([0071] the second direction 118) on a surface of the substrate (205); ([0067] In this regard, FIG. 3 shows an example in which the die 205 includes a first transistor 280-1 and a second transistor 280-2…[0068] In this example, the gates 120-1 to 120-7 extend contiguously (i.e., continuously) across the first transistor 280-1 and the second transistor 280-2)
a plurality of sources/drains ([0071] The source/drain contact layers of the each of the transistors 280-1 to 280-2 may correspond to the respective source/drain contact layers 235-1 to 235-8 shown in FIG. 2D) disposed in the substrate (205) on both sides of each of the gates (120-1-7); ([0048] FIG. 2A, each of the gates 120-1 to 120-7 is between two of the source/drain contact layers 130-1 to 130-8)
a first metal layer ([0063] As shown in FIG. 2D, the first gate metal layer 270 and the second gate metal layer 272 are located on opposite ends of the source/drain metal layers 275) comprising a plurality of first portions ([0059] FIG. 2D also shows source/drain metal layers 275) extending along the first direction (118) and a plurality of second portions ([0069] In one example, the gate metal layers 272-1 and 270-2 may be merged into a common gate metal layer 370) extending along a second direction ([0048] first direction 115), ([0057] FIG. 2D shows a first gate metal layer 270 formed on the gate vias 250-1 to 250-7 and extending in the first direction 115…[0058] FIG. 2D also shows a second gate metal layer 272 formed on the gate vias 252-1 to 252-7 and extending in the first direction 115)
wherein the first direction (118) is perpendicular to the second direction (115), ([0024] the second direction 118 is perpendicular to the first direction 115.)
and each of the first portions (275) comprises discontinuous line segments over the sources/drains (235-1-8), ([0060] Thus, each of the source/drain metal layers 275 is electrically coupled to the respective one of the source/drain contact layers 235-1 to 235-8 through five vias in this example.) (See Fig. 3, showing segmented source/drain metal layers 275)
a plurality of discontinuous regions (An. Fig. 3 DR) extends in the second direction (118), (See An. Fig. 3)
wherein each discontinuous region (DR) is configured between a pair of the discontinuous line segments (275), (See An. Fig. 3, showing the common gate metal layer 370 is between source/drain metal layers 275-1, 275-2) ([0067] In certain aspects, multiple instances of the transistor 280 may be fabricated on the die 205 to form an array of transistors)
each of the second portions (370) is a continuous line segment configured over the gates (120-1-7), ([0069] the common gate metal layer 370 is electrically coupled to each of the gates 120-1 to 120-7 by two parallel gate vias)
and the continuous line segment (370) passing passes through the discontinuous region (DR); (See An Fig. 3, showing the common gate metal layer 370 is in the discontinuous region DR between the source/drain metal layers 275)
a plurality of source/drain contacts ([0063] vias 260, 262, 264, 266, and 268) respectively connected to the plurality of first portions (275) and the plurality of sources/drains (235-1-8); ([0063] In this example, the source/drain contact layers 235-1 to 235-8 provide routing between the fins 110-5 and 110-6 and the vias 260, 262, 264, 266, and 268, which are electrically coupled to the source/drain metal layers 275.)
and a plurality of first gate contacts ([0069] two rows of gate vias) respectively connected to the continuous line segment (370) of the each of the second portions and the gates (120-1-7). ([0069] the gate metal layers 272-1 and 270-2 may be merged into a common gate metal layer 370 with two rows of gate vias disposed between the common gate metal layer 370 and the gates 120-1 to 120-7… In this example, the gates 120-1 to 120-7 extend contiguously under the common gate metal layer 370)
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Regarding Claim 5, Williams further discloses (as shown in Fig. 3) further comprising a back-end-of-the-line (BEOL) metal interconnect disposed above the first metal layer (370, 275). ([0037] The first metal layer may be a metal-1 (M1) layer used for routing. Other metal layers on the die 105 located above the M1 layer with respect to the substrate may be designated with higher numbers, in which a metal-2 (M2) layer is above the M1 layer, a metal-3 (M3) layer is above the M2 layer, and so forth)
Regarding Claim 8, Williams further discloses (as shown in Fig. 3) wherein a type of the high frequency transistor comprises planar MOSFET, FinFET, nanosheet transistor or nanowire field effect transistor. ([0022] In the example shown in FIGS. 1A to 1F, each of the transistors 180 and 185 is a Fin Field Effect Transistor (FinFET). However, it is to be appreciated that exemplary layout techniques disclosed herein may also be applied to planar transistor technologies, nanowire technologies, nanosheet technologies, gate-all-around FET technologies, etc.)
Regarding Claim 14, Williams further discloses (as shown in Fig. 3) wherein an active area is defined in the substrate ([0063] The extension of the source/drain contact layers 235-1 to 235-8 over the fins 110-5 and 110-6 allow the fins 110-5 and 110-6 to be part of the active region (also referred to as the diffusion region) of the transistor 280 while maintaining the minimum space between the source/drain metal layers 275 and the first gate metal layer 270)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Williams et. al (US 2025/0040456 A1) (of record).
Regarding Claim 6, Williams further discloses (as shown in Fig. 3) wherein the number of layers of the BEOL metal interconnect is 6 or less ([0048] one or more metal layers (e.g., M1 layer) in a back-end-of-line (BEOL).)
Since Williams teaches that there is one or more BEOL metal layers ([0048]) it would be obvious, before the effective filing date of the application, to have 1-6 BEOL metal interconnect layers, since 1-6 is included in 1 or more.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Williams et. al (US 2025/0040456 A1) (of record) as applied to claim 5 above, and further in view of Wikipedia: Back End of Line (https://en.wikipedia.org/w/index.php?title=Back_end_of_line&oldid=1075830314) (of record)
Regarding Claim 7, Williams fails to disclose wherein a material of the BEOL metal interconnect comprises platinum, titanium, titanium nitride, aluminum, tungsten, tungsten nitride, ruthenium, ruthenium oxide, tantalum, nickel, cobalt, copper, silver or gold.
Wikipedia discloses wherein a material of the BEOL metal interconnect comprises platinum, titanium, titanium nitride, aluminum, tungsten, tungsten nitride, ruthenium, ruthenium oxide, tantalum, nickel, cobalt, copper, silver or gold. ([Para. 1 Line 3] Common metals are copper and aluminum)
Wikipedia teaches that copper and aluminum are metals commonly used for BEOL metal interconnects. ([Para. 1 Line 3] Common metals are copper and aluminum) Therefore, it would have been obvious, to a person having ordinary skill in the art before the effective filing date, to make the BEOL metal interconnect form copper or aluminum.
Claim(s) 9-13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Williams et. al (US 2025/0040456 A1) (of record) as applied to claim 1 above, and further in view of Chen et. al (US 2023/0009803 A1) (of record)
Regarding Claim 9, Williams fails to disclose wherein the number of the gates (125-1-7; 128-1-7), calculated along the second direction, is 50 per micron or less
Chen discloses (as shown in Fig. 2) wherein the number of the gates, calculated along the second direction, is 50 per micron or less. ([0032] segmented gate structures 204) ([0032] the first gate pitch PG1 may be between about 40 nm and about 65 nm)
Williams is silent regarding the dimensions of the parts of the transistor it discloses. Therefore, it would have been obvious to use the dimensions of Chen, which is similarly directed to transistor arrays, which are known to produce a working transistor array.
Regarding Claim 10, Williams fails to disclose wherein the number of the discontinuous regions (174, 176) of the first portion, calculated along the first direction, is 50 per micron or less.
Chen teaches that the pitch between active regions is between 50 and 120 nm ([0032] the first active region pitch PA1 may be between about 50 nm and about 120 nm). Williams teaches that the discontinuous regions (An. Fig. 3, DR) of the first portion extend across multiple active regions ([0023] fins 110-1 to 110-28). (See An. Fig. 3) Therefore, using the pitch taught in Chen in Williams, since the pitch of the active region (PA1)is at least 50 nm, and the discontinuous regions (174, 176) of the first portion extend across multiple active regions ([0023] fins 110-1 to 110-28), the discontinuous regions would be at least 50 nm in length. Therefore, the number of discontinuous regions along the first direction would be less than 20/micron (1000nm/micron * 1 discontinuous region/50nm = 20 discontinuous regions/micron). Therefore, it would have been obvious before the effective filing date of the application, to have the number of the discontinuous regions (174, 176) of the first portion, calculated along the first direction, be 50 per micron or less.
Regarding Claim 11, Chen further discloses (as shown in Fig. 2) a width of each of the gates is 10 nm to 500 nm. ([0034] the first gate width WG1 is between about 20 nm and about 30 nm)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have:
wherein a length of each of the gates (120-1-7, 128-1-7) is 20 nm to 200 µm.
Williams teaches (as shown in Fig. 2E) that the gate crosses 21 active regions (Gates 120-1-7 cross from fin 110-3 to fin 110-14, Gates 128-1-7 cross from fin 110-15 to fin 110-26) in each transistor (See Fig. 2E, showing the fins 110-4 through 110-25 in the transistor 280). Chen teaches that the pitch is between 50 and 120 nm ([0032] the first active region pitch PA1 may be between about 50 nm and about 120 nm). Therefore, the combination of Williams and Chen would make the gates (120-1-7, 128-1-7) between 1.05 µm and 2.52 µm (crossing twelve fins means crossing 21 fin pitches. 50 nm/pitch * 21 pitches = 1050 nm; 120 nm/pitch *21 pitches = 2520 nm) for each transistor. Williams further teaches multiple transistors 280 arranged in an array ([0067] In certain aspects, multiple instances of the transistor 280 may be fabricated on the die 205 to form an array of transistors) Therefore, it would have been obvious, before the effective filing date of the application, to make an array of transistors having a combined gate length between 20 nm and 200 µm when each transistor has a gate length between 1.05 µm and 2.52 µm.
Regarding Claim 12, Chen further teaches that the contact width of the source/drain contacts is between 15 and 25 nm ([0034] As shown in FIG. 3, the segmented source/drain contact 206 has a first contact width WD1 along the X direction and the segmented gate structure 204 has a first gate width WG1 along the X direction. In some instances, the first contact width WD1 is between about 15 nm and about 25 nm)
Williams teaches (as shown in Fig. 1F) that the source/drain metal layers (174, 176) are wider than the source/drain contact layers (135-1-8, 138-1-8). Williams further teaches that the source/drain metal layers (174, 176) are narrower than the pitch between source/drain contact layers (See Fig. 1F). Therefore, it would be obvious for the width of the source/drain metal layers (174, 176) to be between the width of the source/drain contacts in Chen ([0034] . In some instances, the first contact width WD1 is between about 15 nm and about 25 nm) and the width of the pitch in Chen ([0032] the first gate pitch PG1 may be between about 40 nm and about 65 nm). Therefore, it would have been obvious before the effective filing date of the application based on the teachings of Williams and Chen, to have the width of the source/drain metal layers (174, 176) be between 15 nm and 120 nm, which is between 10 nm and 500 nm.
Williams further teaches that the source/drain metal layers (174, 176) cross some of the fins (of either fins 110-6-23 as shown in Fig. 2E) . Therefore it would have been obvious for the length of the source/drain metal layers (174, 176) to be greater than the pitch of the active areas (Chen: [0032] the first active region pitch PA1 may be between about 50 nm and about 120 nm) and the width of one group of active areas (either fins 110-6-23) which has a width of 850 nm to 2040 nm (crossing 18 fins means crossing 17 fin pitches. 50 nm/pitch * 17 pitches = 850 nm; 120 nm/pitch *17 pitches = 2040 nm). Therefore, it would have been obvious, before the effective filing date of the application based on the teachings of Williams and Chen, to have the source/drain metal layers (174, 176) have a length between 850 nm and 2.04 µm, which is between 20 nm and 200 µm.
Regarding Claim 13, while Williams in view of Chen does not expressly disclose:
wherein a distance between the continuous line segment in the discontinuous region and the discontinuous line segment is 5 nm to 5 µm;
it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application based on the teachings of Williams and Chen.
Williams teaches (as shown in Fig. 2E) that the source/drain metal layer (176) is separated from the second gate metal layer (272-1) by about 2 pitches of the fins (110-23-25). Chen teaches that the pitch is between 50 and 120 nm ([0032] the first active region pitch PA1 may be between about 50 nm and about 120 nm). Therefore, it would have been obvious, from Williams in view of Chen, that the source/drain metal layer (176) is separated from the second gate metal layer (172) by about 100 to 240 nm, which is between 5 nm and 5 µm.
Regarding Claim 15, Chen teaches wherein a width of the active area is 20 nm to 200 µm. (the first active region width WA1 may be between about 10 nm and about 60 nm.)
Chen teaches wherein a width of the active area is 10 nm to 60 nm. ([0032] the first active region width WA1 may be between about 10 nm and about 60 nm.) Therefore, it would have been obvious for the active area to have a width anywhere in the range of 20nm to 200 µm, such as anywhere between 20 nm and 60 nm which is withing the claimed range of 20 nm and 200 µm.
Williams teaches (as shown in Fig. 3) that the active area has a length greater than 6 gate pitches, but less than 8 gate pitches (See Fig. 3). Chen teaches that the gate pitch is between 40 nm and 65 nm ([0032] the first gate pitch PG1 may be between about 40 nm and about 65 nm). Therefore, it would have been obvious before the effective filing date based on the teachings of Williams in view of Chen to have the active area (110-1-28) be more than 240 nm (40 nm/ pitch * 6 pitches) and less than 520 nm (65 nm/pitch * 8 pitches), which is between the claimed range of 20 nm and 200 µm.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because of the new grounds of rejection above.
Applicant’s argument with respect to Claim 1 ([Page 10]) are persuasive in regard to the embodiment relied upon in the Non-Final rejection sent 04 November 2025. However, there is another embodiment in Williams (US 2025/0040456 A1) (See Fig. 3) which contains the gates being continuous between adjacent transistors. This embodiment contains the shortcomings Applicant points out in their remarks, regarding the gate contacts connected each of the second portions and gates ([Page 10 Lines 3-7]).
With regards to applicant’s argument regarding increasing gate resistance in the embodiment of Fig. 2C of Williams ([Page 10, Lines 13-17]), Examiner does not find this argument convincing. Applicant relies on reasoning from the specification on why the arrangement in Williams would not be as good as their invention but does not include how the claimed structure is different from the embodiment in Williams. The claimed invention is what is compared to the prior art. If applicant believes a portion of their claim structurally distinguishes from the embodiment in Williams, they are free to make an argument based on that, but a benefit disclosed in the specification does not distinguish a claim from the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893