DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 18, 2026 has been entered.
Response to Amendment
The amendment filed February 18, 2026 has been entered. Claims 1 and 3-20 remain pending in the application. Applicant’s amendments to the specification and claims have overcome each and every objection and 35 U.S.C. § 112 rejection previously set forth in the Final Office Action mailed November 18, 2025.
Response to Arguments
Applicant’s arguments, see pages 12-16, filed February 18, 2026, with respect to the rejections of claims 1 and 3-20 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of newly found prior art reference Frank et al. (Patent Publication Number US 2016/0226458 A1), hereafter referred to as Frank.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11, and 16 recite the limitation “the differential signal output from the second differential amplifier stage” in lines 16, 16, and 17, respectively. There is insufficient antecedent basis for this limitation in the claims. Amending the limitation to “a differential signal output from the second differential amplifier stage” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 3-10, 12-15, and 17-20 are likewise rejected under this logic by virtue of their dependencies on claims 1, 11, and 16, respectively.
Claims 1, 11, and 16 recite the limitation “the differential signal output from the first differential amplifier stage” in lines 21, 21, and 22, respectively. There is insufficient antecedent basis for this limitation in the claims. Amending the limitation to “a differential signal output from the first differential amplifier stage” (for claims 1 and 16), and “a single-ended signal output from the single-ended first amplifier stage” (for claim 11) is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 3-10, 12-15, and 17-20 are likewise rejected under this logic by virtue of their dependencies on claims 1, 11, and 16, respectively.
Claim 11 recites the limitation “a single-ended first differential amplifier stage” in line 2. This limitation is indefinite because it is unclear whether it refers to a single-ended amplifier or to a differential amplifier. Amending the limitation to “a single-ended first amplifier stage” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 12-15 are likewise rejected under this logic by virtue of their dependency on claim 11. Examiner notes that this element is additionally referred to in multiple instances throughout claims 11-15, and that any amendment should ensure consistency throughout the claims.
Claim 11 recites the limitation “the first single-ended differential amplifier stage” in lines 18-19. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the single-ended first amplifier stage” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 12-15 are likewise rejected under this logic by virtue of their dependency on claim 11.
Claim 12 recites the limitation “the single-ended amplifier stage” in line 3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the single-ended first amplifier stage” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim 16 recites the limitation “the second amplifier stage” in line 6. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the second differential amplifier stage” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 17-20 are likewise rejected under this logic by virtue of their dependency on claim 16.
Claim 16 recites the limitation “a signal” in line 37. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the signal” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 17-20 are likewise rejected under this logic by virtue of their dependency on claim 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 7-8, 10, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (Patent Publication Number US 2016/0308566 A1), as cited by applicant, hereafter referred to as Chang, in view of Frank and Lee et al. (Patent Publication Number US 2004/0157573 A1), as cited by applicant, hereafter referred to as Lee.
Regarding claim 1, Chang discloses:
A circuit structure (Chang, Fig. 7), comprising: a first differential amplifier stage (Fig. 7, Gain_stage 1) having an input (Fig. 7, see inputs of inverters of Gain_stage 1); a second differential amplifier stage (Fig. 7, see Gain_stage 2 and Gain_stage 3) connected to the first differential amplifier stage (Fig. 7, see connection between Gain_stage 2 and Gain_stage 1), the second differential amplifier stage having an output (Fig. 7, see outputs of transistors of Gain_stage 3), wherein the first differential amplifier stage and the second differential amplifier stage carry a signal (Paragraph 39, lines 10-14); a controller (Fig. 7, Control Circuit) configured to measure and modify at least one operational parameter of the signal (Paragraph 39, lines 8-10), the controller including: a first controller input (Fig. 7, see connection between Control Circuit and the LPF coupled to Vocmm2), a first controller output (Fig. 7, see connection between Control Circuit and Gain_stage 1) connecting the controller to the input (Fig. 7, see connection between Control Circuit and inputs of inverters of Gain_stage 1); a second controller input (Fig. 7, see connection between Control Circuit and the LPF coupled to Vocmm1); and a second controller output (Fig. 7, see connection between Control Circuit and Gain_stage 2) connecting the controller to the second differential amplifier stage (Fig. 7, see connection between Control Circuit and Gain_stage 2); a first offset polarity detector and low pass filter circuit (Fig. 7, see LPF coupled to Vocmm2) connecting and a first common-mode voltage signal based on the differential signal output from the second differential amplifier stage to the controller through the first controller input (Fig. 7, see connection between outputs of transistors of Gain_stage 3 and Control Circuit via Vocmm2 and the respective LPF), wherein the first offset polarity detector and low-pass filter circuit includes at least one first low-pass filter (Fig. 7, see low-pass filter between Vocmm2 and Control Circuit); and a second offset polarity detector and low-pass filter circuit (Fig. 7, see LPF coupled to Vocmm1) connecting and a second common-mode voltage signal based on the differential signal output from the first differential amplifier stage to the controller through the second controller input (Fig. 7, see connection between Gain_stage 2 and Control Circuit via Vocmm1 and the respective LPF), wherein the second offset polarity detector and low-pass filter circuit includes at least one second low-pass filter (Fig. 7, see low-pass filter between Vocmm1 and Control Circuit); wherein the controller measures the at least one operational parameter of the signal for offset based on input from the first offset polarity detector and low-pass filter circuit and the second offset polarity detector and low-pass filter circuit (Paragraph 40, lines 21-24), and wherein the controller modifies the at least one operational parameter of the signal to correct signal offset through the first controller output and the second controller input (Paragraph 40, lines 24-27), wherein the circuit structure further includes a second feedback loop (Fig. 7, see feedback loop from Vocmm1 to Gain_stage 1), and a third feedback loop (Fig. 7, see feedback loop from Vocmm2 to Gain_stage 2), wherein the second feedback loop includes the second offset polarity detector and low-pass filter circuit, the second controller input, the controller, and the first controller output (Fig. 7, see feedback loop including Vocmm1, LPF, Control Circuit, and connection to Gain_stage 1), and wherein the third feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the second controller output (Fig. 7, see feedback loop including Vocmm2, LPF, Control Circuit, and connection to Gain_stage 2), but fails to disclose [connecting] one terminal of the output of the second differential amplifier stage [to the controller], [connecting] one terminal of the first differential amplifier stage [to the controller], a first feedback loop, wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output.
However, Frank teaches [connecting] one terminal of the output of the second differential amplifier stage [to the controller] (Frank, Fig. 1, see connection between output of amplifier 104 and controller elements 120 and 112 via LPF 116), [connecting] one terminal of the first differential amplifier stage [to the controller] (Fig. 1, see connection between output of amplifier 104 and controller elements 120 and 112 via LPF 116), but fails to teach a first feedback loop, wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output.
However, Lee teaches a first feedback loop (Lee, Fig. 3, see feedback loop from offset detector 313 through first stage amplifier 305), wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output (Fig. 3, consider offset detector 313 [see also Paragraph 30], connections between offset detector 313 and output of second amplifier stage 309 and controller 315, and connection between controller 315 and first stage amplifier 305).
Chang, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Frank and Lee to include the low-pass filter circuit of Frank in the amplifier of Chang, which would have the effect of enabling control over the signal level of the signal of Chang (Frank, Paragraph 17, lines 8-17), and to include the feedback loop of Lee in the amplifier of Chang, which would have the effect of reducing mismatches between internal components within the amplifier of Chang (Lee, Paragraph 8, lines 1-5).
Regarding claim 3, Chang further discloses:
further including a plurality of additional offset polarity detector and low pass filter circuits (Chang, Fig. 7, see LPF-Control Circuit combinations), wherein each additional offset polarity detector and low-pass filter circuit in the plurality of additional offset polarity detector and low-pass filter circuits connects the controller to the second differential amplifier stage at different points within the second differential amplifier stage relative to each other (Fig. 7, see connections between Control Circuit and the Gain Stages, see also Paragraph 39, lines 15-17, consider variations of breaking up the Gain Stages of Fig. 7 of Chang into further, smaller stages).
Regarding claim 4, Chang further discloses:
wherein each additional offset polarity detector and low-pass filter circuit is connected to the second differential amplifier stage in a common mode configuration. (Chang, Fig. 7, see that connections between Gain Stages and the LPFs are at common mode voltages)
Regarding claim 7, Chang further discloses:
wherein the second controller output further includes a first connection and a second connection (Chang, Fig. 7, see both connections between Control Circuit and Gain_stage 2), wherein the first connection and the second connection connect the controller to the second amplifier stage (Fig. 7, see both connections between Control Circuit and Gain_stage 2).
Regarding claim 8, Chang fails to disclose:
wherein the first connection includes a first digital-to-analog converter (DAC) and the second connection includes a second DAC.
However, Lee further teaches wherein the first connection includes a first digital-to-analog converter (DAC) and the second connection includes a second DAC (Lee, Fig. 2, see DACs 125A-B to couple output of controller to amplifier stages).
Chang, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Lee to include the DACs of Lee in the circuit of Chang, which would have the effect of enabling conversion between digital and analog signals.
Regarding claim 10, Chang further discloses:
wherein the second differential amplifier stage includes any of a transimpedance amplifier (TIA); a single-end-to-differential amplifier; a limiting amplifier; a linear amplifier; a radio frequency (RF) amplifier; an impedance-matched buffer amplifier; and a resistive buffer (Chang, Fig. 7, see also Paragraph 39, lines 1-2 and Paragraph 24, lines 9-11 [Fig. 7 is a linear amplifier]).
Regarding claim 16, Chang discloses:
A method for correcting offset in a signal (Chang, Fig. 7), the method comprising: providing a circuit including (Fig. 7): a first differential amplifier stage (Fig. 7, Gain_stage 1) having an input (Fig. 7, see inputs of inverters of Gain_stage 1); a second differential amplifier stage (Fig. 7, see Gain_stage 2 and Gain_stage 3) connected to the first differential amplifier stage (Fig. 7, see connection between Gain_stage 2 and Gain_stage 1), the second differential amplifier stage having an output (Fig. 7, see outputs of transistors of Gain_stage 3), wherein the first differential amplifier stage and the second amplifier stage carry a signal (Paragraph 39, lines 10-14); a controller (Fig. 7, Control Circuit) configured to measure and modify at least one operational parameter of the signal (Paragraph 39, lines 8-10), the controller including: a first controller input (Fig. 7, see connection between Control Circuit and the LPF coupled to Vocmm2), a first controller output (Fig. 7, see connection between Control Circuit and Gain_stage 1) connecting the controller to the input (Fig. 7, see connection between Control Circuit and inputs of inverters of Gain_stage 1); a second controller input (Fig. 7, see connection between Control Circuit and the LPF coupled to Vocmm1); and a second controller output (Fig. 7, see connection between Control Circuit and Gain_stage 2) connecting the controller to the second differential amplifier stage (Fig. 7, see connection between Control Circuit and Gain_stage 2); a first offset polarity detector and low-pass filter circuit (Fig. 7, see LPF coupled to Vocmm2) connecting and a common-mode voltage signal based on the differential signal output from the second differential amplifier stage to the controller through the first controller input (Fig. 7, see connection between outputs of transistors of Gain_stage 3 and Control Circuit via Vocmm2 and the respective LPF), wherein the first offset polarity detector and low-pass filter circuit includes at least one first low-pass filter (Fig. 7, see low-pass filter between Vocmm2 and Control Circuit); and a second offset polarity detector and low-pass filter circuit (Fig. 7, see LPF coupled to Vocmm1) connecting and a common-mode voltage signal based on the differential signal output from the first differential amplifier stage to the controller through the second controller input (Fig. 7, see connection between Gain_stage 2 and Control Circuit via Vocmm1 and the respective LPF), wherein the second offset polarity detector and low-pass filter circuit includes at least one second low-pass filter (Fig. 7, see low-pass filter between Vocmm1 and Control Circuit); wherein the controller measures the at least one operational parameter of the signal for offset based on input from the first offset polarity detector and low-pass filter circuit and the second offset polarity detector and low-pass filter circuit (Paragraph 40, lines 21-24), and wherein the controller modifies the at least one operational parameter of the signal to correct signal offset through the first controller output through the first controller output and the second controller input (Paragraph 40, lines 24-27), the circuit further includes a second feedback loop (Fig. 7, see feedback loop from Vocmm1 to Gain_stage 1), and a third feedback loop (Fig. 7, see feedback loop from Vocmm2 to Gain_stage 2), wherein the second feedback loop includes the second offset polarity detector and low-pass filter circuit, the second controller input, the controller, and the first controller output (Fig. 7, see feedback loop including Vocmm1, LPF, Control Circuit, and connection to Gain_stage 1), and the third feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the second controller output (Fig. 7, see feedback loop including Vocmm2, LPF, Control Circuit, and connection to Gain_stage 2); calibrating a signal carried by the provided circuit by: measuring at least one operational parameter of the signal with the controller (Paragraph 40, lines 21-24), and calibrating the signal with the controller by modifying the at least one operational parameter of the signal at the input of the circuit in the second feedback loop, and the third feedback loop (Paragraph 40, lines 24-27); and tracking the signal by: measuring the at least one operational parameter of the signal at the output of the circuit (Fig. 7, see connection between outputs of transistors of Gain_stage 3 and Control Circuit via Vocmm2 and the respective LPF), the controller measuring the signal through the second offset polarity detector and low-pass filter circuit (Fig. 7, see LPF coupled to Vocmm1 and connection to Control Circuit), but fails to disclose [connecting] one terminal of the output of the second differential amplifier stage [to the controller], [connecting] one terminal of the first differential amplifier stage [to the controller], a first feedback loop, the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output, [calibrating the signal with the controller by modifying the at least one operational parameter of the signal at an input of the circuit in] the first feedback loop.
However, Frank teaches [connecting] one terminal of the output of the second differential amplifier stage [to the controller] (Frank, Fig. 1, see connection between output of amplifier 104 and controller elements 120 and 112 via LPF 116), [connecting] one terminal of the first differential amplifier stage [to the controller] (Fig. 1, see connection between output of amplifier 104 and controller elements 120 and 112 via LPF 116), but fails to teach a first feedback loop, the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output, [calibrating the signal with the controller by modifying the at least one operational parameter of the signal at an input of the circuit in] the first feedback loop.
However, Lee teaches a first feedback loop (Lee, Fig. 3, see feedback loop from offset detector 313 through first stage amplifier 305), the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output (Fig. 3, consider offset detector 313 [see also Paragraph 30], connections between offset detector 313 and output of second amplifier stage 309 and controller 315, and connection between controller 315 and first stage amplifier 305), [calibrating the signal with the controller by modifying the at least one operational parameter of the signal at an input of the circuit in] the first feedback loop (Paragraph 57, lines 1-4).
Chang, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Frank and Lee to include the low-pass filter circuit of Frank in the amplifier Chang, which would have the effect of enabling control over the signal level of the signal of Chang (Frank, Paragraph 17, lines 8-17), and to include the feedback loop of Lee in the amplifier of Chang, which would have the effect of reducing mismatches between internal components within the amplifier of Chang (Lee, Paragraph 8, lines 1-5).
Regarding claim 17, Chang fails to disclose:
wherein tracking the signal further comprises: comparing the at least one operational parameter of the signal to a pre-set value, and either: taking no action, or modifying the at least one operational parameter of the signal at a point in the circuit in the second feedback loop.
However, Lee further teaches wherein tracking the signal further comprises: comparing the at least one operational parameter of the signal to a pre-set value (Lee, Fig. 3, see also Paragraph 99, lines 1-8), and either: taking no action, or modifying the at least one operational parameter of the signal at a point in the circuit in the second feedback loop (Paragraph 99, lines 8-13).
Chang, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Lee to include the offset compensation circuitry of Lee in the circuit of Chang, which would have the effect of enabling real time offset removal (Lee, Paragraph 94, lines 5-7).
Regarding claim 18, Chang fails to disclose:
wherein the controller continuously measures the at least one operational parameter of the signal in the circuit.
However, Lee further teaches wherein the controller continuously measures the at least one operational parameter of the signal in the circuit (Lee, Paragraph 94, lines 1-7).
Chang, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Lee to include the offset compensation circuitry of Lee in the circuit of Chang, which would have the effect of enabling real time offset removal (Lee, Paragraph 94, lines 5-7).
Regarding claim 19, Chang fails to disclose:
wherein the controller periodically measures the at least one operational parameter of the signal in the circuit.
However, Lee further teaches wherein the controller periodically measures the at least one operational parameter of the signal in the circuit (Lee, Paragraph 71, lines 1-6).
Chang, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Lee to include the offset compensation circuitry of Lee in the circuit of Chang, which would have the effect of enabling real time offset removal (Lee, Paragraph 69, lines 1-8).
Regarding claim 20, Chang further discloses:
further including measuring the at least one operational parameter of the signal at a plurality of connections in the circuit with the controller (Chang, Fig. 7, see LPF-Control Circuit combinations and connections to Gain_stages 1-3), the controller measuring the signal through a plurality of additional offset polarity detector and low-pass filter circuits connecting the controller to the plurality of connections in the circuit (Fig. 7, see LPF-Control Circuit combinations); and modifying the at least one operational parameter of the signal through the controller (Paragraph 40, lines 24-27), the controller modifying the at least one operational parameter of the signal in a plurality of feedback loops (Fig. 7, see feedback loops formed by LPF-Control Circuit combinations with the Gain Stages), wherein the plurality of feedback loops connect the controller to a second plurality of connections in the circuit (Fig. 7, see connections between Control Circuit and the Gain Stages, see also Paragraph 39, lines 15-17, consider variations of breaking up the Gain Stages of Fig. 7 of Chang into further, smaller stages).
Claims 5-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Frank and Lee as applied to claim 1, and further in view of Szilagyi et al. “A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS”, as cited by applicant, hereafter referred to as Szilagyi.
Regarding claim 5, Chang further discloses:
and wherein the second differential amplifier stage includes a differential circuit (Chang, Fig. 7, see that Gain_stage 2 and Gain_stage 3 are differential), but fails to disclose wherein the first differential amplifier stage further includes a single-ended circuit.
However, Szilagyi teaches wherein the first differential amplifier stage further includes a single-ended circuit (Szilagyi, Fig. 1, TIA).
Chang, Frank, Lee, and Szilagyi are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Szilagyi to include the single-ended input TIA of Szilagyi in the circuit of Chang, which would have the effect of enabling the circuit of Chang to incorporate optical signals (Szilagyi, Page 2, Col. 1, lines 7-10).
Regarding claim 6, Chang fails to disclose:
wherein the first differential amplifier stage further includes a transimpedance amplifier connected to a single-ended-to-differential amplifier in the second amplifier stage, and wherein the single-ended-to-differential amplifier is connected to a limiting amplifier.
However, Szilagyi teaches wherein the first differential amplifier stage further includes a transimpedance amplifier (Szilagyi, Fig. 1, TIA) connected to a single-ended-to-differential amplifier in the second amplifier stage (Fig. 1, LA, see also connection between TIA and LA), and wherein the single-ended-to-differential amplifier is connected to a limiting amplifier (Fig. 1, LA).
Chang, Frank, Lee, and Szilagyi are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Szilagyi to include the input stages of Szilagyi in the circuit of Chang, which would have the effect of enabling the circuit of Chang to incorporate optical signals (Szilagyi, Page 2, Col. 1, lines 7-10).
Regarding claim 9, Chang fails to disclose:
wherein the input of the first differential amplifier stage is a photodiode.
However, Szilagyi teaches wherein the input of the first differential amplifier stage is a photodiode (Szilagyi, Fig. 1, PD).
Chang, Frank, Lee, and Szilagyi are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Szilagyi to include the photodiode of Szilagyi in the circuit of Chang, which would have the effect of enabling the circuit of Chang to incorporate optical signals (Szilagyi, Page 2, Col. 1, lines 7-10).
Claim 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Szilagyi, Frank, and Lee.
Regarding claim 11, Chang discloses:
A silicon photonic receiver circuit (Chang, Fig. 7), comprising: a second differential amplifier stage (Fig. 7, see Gain_stage 1-3); a controller (Fig. 7, Control Circuit) configured to measure and modify at least one operational parameter of the signal (Paragraph 39, lines 8-10), the controller including: a first controller input (Fig. 7, see connection between Control Circuit and the LPF coupled to Vocmm2), a second controller input (Fig. 7, see connection between Control Circuit and the LPF coupled to Vocmm1); a first controller output (Fig. 7, see connection between Control Circuit and Gain_stage 1) connecting the controller to the input (Fig. 7, see connection between Control Circuit and inputs of inverters of Gain_stage 1), and a second controller output (Fig. 7, see connection between Control Circuit and Gain_stage 2) connecting the controller to the second differential amplifier stage (Fig. 7, see connection between Control Circuit and Gain_stage 2); a first offset polarity detector and low pass filter circuit (Fig. 7, see LPF coupled to Vocmm2) connecting one terminal of an output of the second differential amplifier stage and a first common-mode voltage signal based on the differential signal output from the second differential amplifier stage to the controller through the first controller input (Fig. 7, see connection between outputs of transistors of Gain_stage 3 and Control Circuit via Vocmm2 and the respective LPF); and a second offset polarity detector and low-pass filter circuit (Fig. 7, see LPF coupled to Vocmm1) connecting one terminal of the first single-ended differential amplifier stage and a second common-mode voltage signal based on the differential signal output from the first differential amplifier stage to the controller through the second controller input (Fig. 7, see connection between Gain_stage 2 and Control Circuit via Vocmm1 and the respective LPF); wherein the controller measures the at least one operational parameter of the signal for offset based on input from the first offset polarity detector and low-pass filter circuit and the second offset polarity detector and low-pass filter circuit (Paragraph 40, lines 21-24), and wherein the controller modifies the at least one operational parameter of the signal to correct signal offset through the first controller output and the second controller input (Paragraph 40, lines 24-27), wherein the silicon photonic receiver circuit includes a second feedback loop (Fig. 7, see feedback loop from Vocmm1 to Gain_stage 1), and a third feedback loop (Fig. 7, see feedback loop from Vocmm2 to Gain_stage 2), wherein the second feedback loop includes the second offset polarity detector and low-pass filter circuit, the second controller input, the controller, and the first controller output (Fig. 7, see feedback loop including Vocmm1, LPF, Control Circuit, and connection to Gain_stage 1), and wherein the third feedback loop includes the first offset polarity detector and low-pass filter circuit , the first controller input, the controller and the second controller output (Fig. 7, see feedback loop including Vocmm2, LPF, Control Circuit, and connection to Gain_stage 2), but fails to disclose a single-ended amplifier stage; a photodiode configured to feed a signal to the single-ended amplifier stage; [the differential amplifier stage] receiving input from the single-ended amplifier stage, [connecting] one terminal of an output of the second differential amplifier stage [to the controller], [connecting] one terminal of the first single-ended differential amplifier stage [to the controller], a first feedback loop, wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output.
However, Szilagyi teaches a single-ended amplifier stage (Szilagyi (Fig. 1, TIA); a photodiode configured to feed a signal to the single-ended amplifier stage (Fig. 1, PD and connection to TIA); [the differential amplifier stage] receiving input from the single-ended amplifier stage (Fig. 1, LA and connection to TIA), but fails to teach [connecting] one terminal of an output of the second differential amplifier stage [to the controller], [connecting] one terminal of the first single-ended differential amplifier stage [to the controller], a first feedback loop, wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output.
However, Frank teaches [connecting] one terminal of an output of the second differential amplifier stage [to the controller] (Frank, Fig. 1, see connection between output of amplifier 104 and controller elements 120 and 112 via LPF 116), [connecting] one terminal of the first single-ended differential amplifier stage [to the controller] (Fig. 1, see connection between output of amplifier 104 and controller elements 120 and 112 via LPF 116), but fails to teach a first feedback loop, wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output.
However, Lee teaches a first feedback loop (Lee, Fig. 3, see feedback loop from offset detector 313 through first stage amplifier 305), wherein the first feedback loop includes the first offset polarity detector and low-pass filter circuit, the first controller input, the controller, and the first controller output (Fig. 3, consider offset detector 313 [see also Paragraph 30], connections between offset detector 313 and output of second amplifier stage 309 and controller 315, and connection between controller 315 and first stage amplifier 305).
Chang, Szilagyi, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Szilagyi, Frank, and Lee to include the input stages of Szilagyi in the circuit of Chang, which would have the effect of enabling the circuit of Chang to incorporate optical signals (Szilagyi, Page 2, Col. 1, lines 7-10), to include the low-pass filter circuit of Frank in the amplifier of Chang, which would have the effect of enabling control over the signal level of the signal of Chang (Frank, Paragraph 17, lines 8-17), and to include the feedback loop of Lee in the amplifier of Chang, which would have the effect of reducing mismatches between internal components within the amplifier of Chang (Lee, Paragraph 8, lines 1-5).
Regarding claim 12, Chang fails to disclose:
wherein the second differential amplifier stage further includes a single-ended-to-differential amplifier, wherein the single-ended amplifier stage includes a single-ended transimpedance amplifier (TIA) having an output thereof connected to an input of the single-ended-to-differential amplifier.
However, Szilagyi further teaches wherein the second differential amplifier stage further includes a single-ended-to-differential amplifier (Szilagyi, Fig. 1, LA), wherein the single-ended amplifier stage includes a single-ended transimpedance amplifier (TIA) (Fig. 1, TIA) having an output thereof connected to an input of the single-ended-to-differential amplifier (Fig. 1, see connection between TIA and LA).
Chang, Szilagyi, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Szilagyi to include the input stages of Szilagyi in the circuit of Chang, which would have the effect of enabling the circuit of Chang to incorporate optical signals (Szilagyi, Page 2, Col. 1, lines 7-10).
Regarding claim 13, Chang fails to disclose:
wherein the second differential amplifier stage further includes at least one of a limiting amplifier and a resistive buffer.
However, Szilagyi further teaches wherein the second differential amplifier stage further includes at least one of a limiting amplifier and a resistive buffer (Szilagyi, Fig. 1, see that LA is a limiting amplifier).
Chang, Szilagyi, Frank, and Lee are all considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in receiver circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Chang to incorporate the teachings of Szilagyi to include the input stages of Szilagyi in the circuit of Chang, which would have the effect of enabling the circuit of Chang to incorporate optical signals (Szilagyi, Page 2, Col. 1, lines 7-10).
Regarding claim 14, Chang further discloses:
further including a plurality of additional offset polarity detector and low pass filter circuits (Chang, Fig. 7, see LPF-Control Circuit combinations), wherein each additional offset polarity detector and low-pass filter circuit in the plurality of offset polarity detector and low-pass filter circuits connects the second differential amplifier stage to the controller at different points within the differential amplifier stage relative to each other offset polarity detector and low-pass filter circuit (Fig. 7, see connections between Control Circuit and the Gain Stages, see also Paragraph 39, lines 15-17, consider variations of breaking up the Gain Stages of Fig. 7 of Chang into further, smaller stages).
Regarding claim 15, Chang further discloses:
wherein each additional offset polarity detector and low-pass filter circuit is connected to the second differential amplifier stage in a common mode configuration (Chang, Fig. 7, see that connections between Gain Stages and the LPFs are at common mode voltages).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. (Patent Publication Number CN 115,549,610 A) discloses (Fig. 1) an amplifier system with an offset correction-low pass filter circuit with an output coupled to differential amplifiers via DACs.
Tanaka et al. (Patent Publication Number US 2016/0285563 A1) discloses (Fig. 1) a receiving circuit for a photodiode that includes an offset correction-low pass filter circuit.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843