DETAILED ACTION
1. Claims 21-40 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 21-22 and 24-40 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Appu et al (hereafter Appu)(US Pub. 20190304054).
5. As to claim 21, Appu discloses a microprocessor system ([0151] microprocessor), comprising:
a plurality of matrix processors which form a node engine ([0041], [0138], [0166] matrix operations);
a control unit configured to provide matrix processors instructions to the matrix processors ([0209] control logic); and
a plurality of processor registers allocated to store a plurality of bit depth formats ([0069] registers, [0155]-[0158] bit depths),
wherein the node engine is configured to execute a plurality of matrix processor instructions, wherein operations associated with the matrix processor instructions are interleaved for execution by the matrix processors which form the node engine ([0059]-[0061]), and
wherein the matrix processors are configured to execute the operations in different bit depth formats based on the associated matrix processor instructions ([0155]-[0158]).
6. As to claim 22, Appu discloses wherein a first bit depth format is an 8-bit floating point format, and wherein input data associated with a particular matrix processor instruction is formatted according to the first bit depth format ([0155]-[0157] 8 bit depth).
7. As to claims 24 and 37, Appu discloses wherein a particular matrix processor instruction specifies a configurable exponent bias ([0115]-[0121] bias).
8. As to claims 25 and 32, Appu discloses wherein the matrix processors interleave the operations based on data availability ([0059]-[0061]).
9. As to claims 26 and 33, Appu discloses wherein each of the plurality of matrix processors includes a plurality of accumulators ([0159] and [0320] accumulating).
10. As to claim 27, Appu discloses wherein each matrix processor uses different accumulators for operations associated with different matrix processor instructions ([0159] and [0320] accumulating).
11. As to claim 28, 29, 35, and 40, Appu discloses wherein for a particular matrix processor, the different accumulators are designated to accumulate and store intermediate results associated with the different matrix processor instructions and wherein the different accumulators store the intermediate results using a first bit depth format with a higher-bit floating point format than a second bit depth format used for input operands ([0156]-[0160]).
12. As to claims 30 and 39, Appu discloses wherein a particular matrix processor instruction specifies a particular accumulator for operations associated with the particular matrix processor instruction ([0159] and ([0320]).
13. As to claims 31 and 38, the claim is rejected for similar reasons as claim 21 above.
14. As to claim 36, Appu discloses wherein a particular matrix processor instruction specifies a first floating-point matrix operand and a second floating-point matrix operand, and wherein the first and second floating-point matrix operands are formatted using a first bit depth format ([0156]-[0160]).
Claim Rejections - 35 USC § 103
15. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
16. Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Appu.
17. As to claim 23, Appu discloses wherein intermediate results associated with the particular matrix processor instruction are formatted according to a second bit depth format ([0155]-[0157]).
Appu does not explicitly disclose wherein a second bit depth format is a 21-bit floating point format. However, it would have been obvious to one of ordinary skill in the art to apply any second bit depth format as needed, as this is not limiting. For example, Appu teaches it may process operations having higher bit depths ([0158]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Appu by utilizing a second bit depth format of 21 bits, for example, in order to format results as needed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20040098548 – related to a programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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