DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities:
Claim 16 recites on Line 3, “a memory adress” which should “a memory address”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gulati et al. (US PGPUB 2014/0052930; hereinafter “Gulati”) in view of Ableidinger et al. (US PGPUB 2022/0308878; hereinafter “Ableidinger”), Das (US PGPUB 2018/0278714; hereinafter “Das”) and Sultana et al. (US PGPUB 2020/0026519; hereinafter “Sultana”).
Claim 1: (Currently Amended)
Gulati teaches an integrated circuit comprising:
at least one processing unit for executing instructions of at least one computer program (Fig. 1: System on a Chip 100 comprising Processors 150a-d. [0042] “Each one of the processors 150a-150d may include one or more cores and one or more levels of a cache memory subsystem. Each core may support the out-of-order execution of one or more threads of a software process and include a multi-stage pipeline.”),
the at least one computer program comprising at least one logging command with at least one store instruction ([0007] “Software and hardware traces provide a historical account of application code execution.” [0053] “One example of a trace instruction is a trace start operation… qualified trace history may be collected and stored in a trace buffer…The trace buffer may be divided into physical partitions,” wherein the “trace start operation” is the “at least one logging command”. [0078] “a Write Bus or other storage operation may have been executed after the Started trace instruction has been executed,” wherein the “Write Bus or other storage operation” is the “at least one store instruction”. [0053] “A trace unit … for collecting trace history and bus event statistics for one or more buses”, wherein [0054] “another bus event filter may be assigned to a bus class that includes memory access request bus 240a and memory response bus 234a.” [0049] “The bus traffic may also include asynchronous memory access requests 240a-240b from the multiple IC designs on the SOC and corresponding memory responses 234a-234b from the memory interface.”); and
at least one instruction tracer circuitry configurable for tracing instructions executed by the at least one processing unit (Fig. 1: Trace Unit 140 coupled to Processors 150a-d. [0051] “the trace unit 116 may monitor buses 234a-234b, 240a-240b, 242a-242b and 244 and store trace history and collect statistics on bus events.” [0053] “A trace unit may include programmable on-die debug hardware or resources for collecting trace history and bus event statistics for one or more buses located at a coherence point,” wherein the “trace unit” is the “at least one instruction tracer circuitry.”); and
wherein the at least one instruction tracer circuitry is configured to:
- intercept the at least one store instruction when executed by the at least one processing unit; and - retrieve the logging data from the intercepted store instruction ([0078] “a Write Bus or other storage operation may have been executed after the Started trace instruction has been executed.” [0079] “The trace storage 506 may include multiple separate physical partitions 550a-550b, such as RAMs… each separate one of the partitions 550a-550b may be used to capture trace history for different bus events, such as memory access requests,” wherein the captured “memory access request”, i.e. “a Write Bus or other storage operation”, is the intercepted “at least one store instruction”.).
With further regard to Claim 1, Gulati does not teach the following, however, Ableidinger teaches:
the at least one instruction tracer circuitry respectively directly coupled to the at least one processing unit ([0017] “The trace encoder may be connected to a processor core via a trace interface. The trace encoder may receive instruction trace information (e.g., instruction addresses, instruction types, context information, and the like) from the processor core via the trace interface,” wherein Fig. 1 shows that the “Trace Encoder 120” is directly connected to the “Processor Core 110”. [0018] “the processor core 110, the trace encoder 120, and the trace buffer 130 may be implemented together in an integrated circuit 125, such as an application-specific integrated circuit (ASIC) or a system on a chip (SoC).” [0019] “The trace encoder 120 may receive the instruction trace information and may compress the information into lower bandwidth trace packets or messages for instruction tracing.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati with the directly coupled tracer circuitry as taught by Ableidinger in order “to determine system performance and to help identify possible optimizations for improving the system” (Ableidinger [0003]).
With further regard to Claim 1, Gulati in view of Ableidinger does not teach the following, however, Das teaches wherein
the at least one computer program being associated with a memory region ([0061] “a database system storage client 116a may comprise at least a portion of the acceleration module 150, and may be configured to send one or more database log entries or other transaction log entries to the volatile memory 1013 of the non-volatile storage device 102,” wherein the “database system storage client 116a”, comprising the “acceleration module 150”, is the “at least one computer program”. [0096] “the acceleration module 150 may cooperate with the ACM 1011 to destage, copy, transfer, migrate, and/or move data from volatile memory buffers 1013 to… the non-volatile storage device 121,” wherein the “database system storage client 116a,” via the “acceleration module 150”, stores data to the “non-volatile storage device 121”, i.e. the “memory region,” and as such the “database system storage client 116a” can be said to be “associated with” the “non-volatile storage device 121.”); and
- intercept the at least one store instruction, in response to the store instruction being an instruction to store logging data within the memory region associated with the at least one computer program ([0037] “acceleration module 150 may receive storage requests as an API call from a storage client 116, as an IO-CTL command,” wherein the “storage requests” comprise “an instruction to store”. [0055] “The non-volatile storage device interface 139 may communicate with the one or more non-volatile storage devices 102, 121 using input-output control (IO-CTL) command(s).” [0062] “the acceleration module 150 may… reroute one or more transaction log entries, such as database log entries, which the storage client 116 has sent to another location, such as the second non-volatile storage device 121, to the volatile memory 1013 of the non-volatile storage device 102,” wherein the “transaction log entries… sent to… the second non-volatile storage device 121” comprises the “instruction to store logging data within the memory region associated with the at least one computer program”. [0256] “log module 1902 executing on the host computing device 110 intercepts 2402 one or more database log entries from a database system 116a executing on the host computing device 110…The commit module 1904 executing on the host computing device 110 reroutes 2404 the intercepted 2402 one or more database log entries over the network 115 to the volatile memory 1013 of the non-volatile storage device 102,” wherein Fig. 1 of Das shows that “Database System ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger with the interception of an instruction store logging data as taught by Das in order to “accelerate storage of a transaction log, operation of a storage client 116, or the like transparently, with little or no cooperation from the storage client 116 itself” (Das [0062]) and further “To make efficient use of the volatile memory 1013, which may have a smaller storage capacity than the non-volatile storage medium 122, and to provide the access speed of the volatile memory 1013 and the persistence of the non-volatile storage medium 122” (Das [0096]).
With further regard to Claim 1, Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches wherein the at least one instruction tracer circuitry is configured to:
- generate a logging packet comprising the logging data ([0060] “the packet generator circuit 703 can perform operations of the packet generation logic 311 in the trace module 109, as shown in FIG. 3. The packet generator circuit 703 can work in concert with the instruction tracer 707 of the retirement unit 706 to generate a processor trace packets that describe the traced instructions,” wherein a “trace packet” is a “logging packet”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the generation of a logging packet as taught by Sultana in order to “facilitate the development of real-time, low overhead, and efficient security solutions able to defend against advanced security attacks” (Sultana [0013]).
Claim 2:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1, and Gulati further teaches:
wherein the at least one instruction tracer circuitry is further configured to add a time reference to the logging packet ([0059] “Referring to FIG. 4, a generalized block diagram illustrating one embodiment of trace data storage allocations 330 is shown.” [0060] “The trace buffer 340 may be partitioned on a bus basis… Each of the entries 344a-344f, 346a-346f, and 348a-348f may store similar information, such as status, trace history, bus event statistics, and timestamp information,” wherein the trace information stored in the “entries” is representative of the packetized information as taught above in Sultana. [0066] “The time delta field 426 may store a timestamp value measuring a time duration.”).
Claim 3:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1, and Gulati further teaches:
wherein the at least one instruction tracer circuitry is further configured to retrieve a memory address within the memory region from the intercepted store instruction, and to add the retrieved memory address to the logging packet ([0059] “Referring to FIG. 4, a generalized block diagram illustrating one embodiment of trace data storage allocations 330 is shown.” [0060] “The trace buffer 340 may be partitioned on a bus basis… Each of the entries 344a-344f, 346a-346f, and 348a-348f may store similar information, such as status, trace history, bus event statistics, and timestamp information,” wherein the trace information stored in the “entries” is representative of the packetized information as taught above in Sultana. [0066] “The address field 418 may include an address corresponding to a cache block with a requested cache coherence state.”).
Claim 4:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1. Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches:
wherein the at least one instruction tracer circuitry is further configured to interrupt and/or initiate the generating of logging packets based on the logging data ([0060] “the packet generator circuit 703 can perform operations of the packet generation logic 311 in the trace module 109, as shown in FIG. 3. The packet generator circuit 703 can work in concert with the instruction tracer 707 of the retirement unit 706 to generate a processor trace packets that describe the traced instructions,” wherein a “trace packet” is a “logging packet” and further wherein the “packet generator circuit” is configured to “initiate the generating of logging packets based on the logging data”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the generation of a logging packet as taught by Sultana in order to “facilitate the development of real-time, low overhead, and efficient security solutions able to defend against advanced security attacks” (Sultana [0013]).
Claim 5:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1. Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches:
further comprising at least one debugging buffer circuitry configured to store the logging packet, and wherein the at least one instruction tracer circuitry is further configured to forward the logging packet to the at least one debugging buffer circuitry ([0047] “Trace packets 315 that are configured to be captured can be written to the output buffer 313 before being output to the trace data area 206 in the memory device 120,” wherein the “output buffer 313” is the “at least one debugging buffer circuitry”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the buffer circuitry as taught by Sultana since the use of buffers is well-known in the art to enable efficient transmission of data from one location to another.
Claim 6:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 5. Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches:
wherein the at least one instruction tracer circuitry is further configured to interrupt and/or initiate the forwarding and/or storing of logging packets based on the logging data ([0029] “the trace module can be used to enable or disable (e.g., filter) the output or recording of specific types of trace packets.” [0085] “the processor trace module is to selectively output the processor trace packet based on a type of processor trace packet to be output. In one embodiment the type of processor trace packet to be output is selected from a set of processor trace packets including: a first processor trace packet to indicate whether a conditional branch is taken. The computing system may also include a second processor trace packet to indicate a target address of an indirect branch. The computing system may also include instruction; and a third processor trace packet to indicate a source address for an asynchronous event,” wherein initiating the forwarding and/or storing of a “trace packet” in Sultana is based on “a type of processor trace packet,” i.e. “based on the logging data.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the selective handling of packets based on the logging information as taught by Sultana in order “To enhance the functionality of the exploit and attack monitoring techniques” (Sultana [0029]).
Claim 7:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 5. Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches:
wherein the at least one instruction tracer circuitry is a plurality of instruction tracer circuitries (Fig. 3: Trace Module 109, i.e. “instruction tracer circuitry”, comprising Filter Logic 302, Entry Storage Logic 305, Comparison Logic 307, Packet Generation Logic 311 and History Buffer 309, i.e. “a plurality of instruction tracer circuitries.” [0046] “Processor trace packets generated by processor trace circuitry within the trace module 109 may be stored temporarily by the circuitry and then be provided to memory and/or other storage for analysis.” [0075] “Various embodiments may include various processes. These processes may be performed by hardware components or … logic circuits programmed with the instructions to perform the processes.”) and
wherein the at least one debugging buffer circuitry is further configured to store logging packets that are forwarded by the plurality of instruction tracer circuitries ([0047] “Trace packets 315 that are configured to be captured can be written to the output buffer 313 before being output to the trace data area 206 in the memory device 120.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the plurality of instruction tracer circuitries as taught by Sultana in order to “facilitate the development of real-time, low overhead, and efficient security solutions able to defend against advanced security attacks” (Sultana [0013]).
Claim 8:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 5. Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches:
further comprising at least one peripheral circuitry for outputting data from the integrated circuit ([0021] “the processor 102 (or processors) include an integrated memory controller 116… The memory controller 116 facilitates communication between a memory device and other components of the system 100,” wherein the “integrated memory controller 116” is the “at least one peripheral circuitry”. [0033] “The processor trace module 204 may include, invoke, or otherwise use the trace module 109 of the processor 102 to generate part or all of the trace data...The trace data may be stored in a trace data area 206 in the memory device 120.”), and
wherein the at least one instruction tracer circuitry and/or the at least one debugging buffer circuitry are further configured to forward the logging packet to the at least one peripheral circuitry ([0047] “Trace packets 315 that are configured to be captured can be written to the output buffer 313 before being output to the trace data area 206 in the memory device 120,” wherein the “trace packets 315” are forwarded by the “output buffer 313” to the “integrated memory controller 116” since the “integrated memory controller 116” has been disclosed as enabling the transfer of the “trace packets 315” to the “memory device 120”, as discussed above with regard to Sultana [0021].).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the peripheral circuitry as taught by Sultana in order to “[facilitate] communication between a memory device and other components of the system” (Sultana [0021]).
Claim 9:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1. Gulati in view of Ableidinger and Das does not teach the following, however, Sultana teaches:
wherein the memory region has at least one configurable address range ([0011] “Processors described herein include instruction trace circuitry that can be configured to capture information related to … selected memory ranges.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Das with the generation of a logging packet as taught by Sultana in order “to provide efficient monitoring for control flow exploits including return-oriented programming and jump-oriented programming exploits, as well as data-oriented programming (DOP) attacks without modifying client software” (Sultana [0029]).
Claim 12:
With regard to Claim 12, this claim is equivalent in scope to Claim 1 rejected above, merely having a different independent claim type, and as such Claim 12 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 1.
Claim 16: (New)
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1. Gulati in view of Ableidinger and Sultana does not teach the following, however, Das teaches wherein the at least one instruction tracer circuitry is configured to:
determine a memory adress at which the store instruction instructs to store the logging data; and intercept the at least one store instruction in response to the memory address being within the memory region associated with the at least one computer program ([0233] “the commit module 1904 may send a logical identifier (e.g., a range of one or more LBAs or the like), a physical address, or the like for the one or more transaction log entries to be stored in the non-volatile storage device 121.” [0212] “the log module 1902 may be configured to intercept… database log entries… according to one or more characteristics. For example, the log module 1902 may intercept… each transaction log record from one or more selected storage clients 116… destined and/or addressed for a selected location (e.g., for the non-volatile storage device 121, for the non-volatile storage medium 122, for a range of one or more logical addresses, or the like).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger and Sultana with the interception of a store instruction based on a memory address as taught by Das in order to “accelerate storage of a transaction log, operation of a storage client 116, or the like transparently, with little or no cooperation from the storage client 116 itself” (Das [0062]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gulati in view of Ableidinger, Das and Sultana as applied to Claim 1 above, and further in view of Mehra et al. (US PGPUB 2004/0148360; hereinafter “Mehra”).
Claim 10.
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1, and Gulati further teaches:
further comprising a memory including the memory region (Fig. 1: Caches 114a-11b coupled to Processors 150a-150d. [0054] “another bus event filter may be assigned to a bus class that includes memory access request bus 240a and memory response bus 234a.” [0049] “The bus traffic may also include asynchronous memory access requests 240a-240b from the multiple IC designs on the SOC and corresponding memory responses 234a-234b from the memory interface that includes the memory controllers 112a-112b and the memory caches 114a-114b,” wherein the “caches 114a-114b” are the “memory” which comprise the “memory region”.);
With further regard to Claim 10, Gulati in view of Ableidinger, Das and Sultana does not teach the following, however, Mehra teaches:
wherein the memory is directly coupled to the at least one processing unit with a guaranteed access time ([0002] “System memory is generally connected to a processor through a system bus where such memory is relatively fast with guaranteed access times measured in tens of nanoseconds. Moreover, system memory can be directly accessed with byte-level granularity.” [0003] “Prior art systems have used battery-backed dynamic random access memory (BBDRAM).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger, Das and Sultana with the directly coupled memory having a guaranteed access time as taught by Mehra since “BBDRAM, for example, may have some performance advantages over true persistent memory” (Mehra [0003]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gulati in view of Ableidinger, Das and Sultana as applied to Claim 1 above, and further in view of Cruickshank et al. (US PGPUB 2006/0259825; hereinafter “Cruickshank”).
Claim 11:
Gulati in view of Ableidinger, Das and Sultana teaches all the limitations of claim 1 as described above. Gulati in view of Ableidinger, Das and Sultana does not teach the following, however, Cruickshank teaches:
wherein the memory region is unallocated ([0002] “The trace data may comprise data such as the sequence of addresses executed by the processor, values of various processor registers at each executed instruction, and information in log files written by the traced program.” [0003] “a method and system of profiling applications that use virtual memory.” [0004] “Other illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of tasks, each task using a different virtual to physical memory mapping), obtaining values indicative of a plurality of states of virtual to physical memory mapping used by a memory management unit associated with a processor of a target system.” wherein the “memory region” in Cruickshank is “virtual memory,” and wherein “virtual memory” is “unallocated” as indicated by the Applicant’s specification Paragraph [0054].).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger, Das and Sultana with the tracing of an unallocated memory region as taught by Cruickshank as this “enables the debug-trace program to identify which tasks were executed” (Cruickshank [0026]).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Gulati in view of Ableidinger, Das and Sultana as applied to Claim 1 above, and further in view of Matsumoto (US PGPUB 2020/0278917; hereinafter “Matsumoto”).
Claim 13:
Gulati in view of Ableidinger, Das and Sultana teaches the integrated circuit of claim 1, and Gulati further teaches:
the computer program code comprising at least one logging code portion for logging the logging data; the method comprising: - detecting the at least one logging code portion in the computer program code ([0058] “Trace information is stored in the physical partitions of the trace buffer according to the assignments and the type of trace instruction.” [0069] “multiple instruction types, such as at least Clear, Arm, Start, Pause, and End.” [0071] “The Start instruction may place the trace unit in a Started status state and trace history, bus event statistics, or both may be collected.” [0072] “The End instruction may place the trace unit in an Ended status state causing the collection of trace history, bus event statistics, or both to stop,” see also Gulati Claims 8-9 which also disclose the execution of a “trace start instruction” and a “trace end instruction”.);
With further regard to Claim 13, Gulati in view of Ableidinger, Das and Sultana does not teach the following, however, Matsumoto teaches:
compiling the detected logging code portion to the at least one store instruction to store the logging data within the memory region ([0007] “The program editor includes: a program editing unit capable of setting a pair of a trace start position and a trace end position in the sequence program; and a compile unit that analyzes an address of an instruction between the trace start positron and the trace end position set by the program editing unit, inserts a transfer instruction about transferring a signal value to a tracing memory, and sets the analyzed address in a sampling address table.” [0030] “When analyzing the address of the instruction between the trace start position and the trace end position, the compile unit 13 sets the analyzed address in a sampling address table.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger, Das and Sultana with the compiling of logging code as taught by Matsumoto for purposes of “converting the sequence program to the object code of the sequence program containing an execution program and the sampling address table” (Matsumoto [0007]).
Claim 14:
Gulati in view of Ableidinger, Das, Sultana and Matsumoto teaches the method of claim 13. Gulati further teaches:
wherein the store instruction comprises a memory address within the memory region that is associated with the computer program code ([0059] “Referring to FIG. 4, a generalized block diagram illustrating one embodiment of trace data storage allocations 330 is shown.” [0060] “The trace buffer 340 may be partitioned on a bus basis… Each of the entries 344a-344f, 346a-346f, and 348a-348f may store similar information, such as status, trace history, bus event statistics, and timestamp information,” wherein the trace information stored in the “entries” is representative of the packetized information as taught above in Sultana. [0066] “The address field 418 may include an address corresponding to a cache block with a requested cache coherence state.”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gulati in view of Ableidinger, Das, Sultana and Matsumoto as applied to Claim 13 above, and further in view of Horley et al. (US PGPUB 2013/0055032; hereinafter “Horley”).
Claim 15:
Gulati in view of Ableidinger, Das, Sultana and Matsumoto teaches all the limitations of claim 13 as described above. Gulati in view of Ableidinger, Das, Sultana and Matsumoto does not teach the following, however, Horley teaches:
wherein the store instruction comprises a memory address within the memory region that is associated with a logging level ([0017] “The plurality of memory addresses may be arranged such that writes to different memory addresses are used to associate different priority levels with trace data received by the trace output device.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the integrated circuit as disclosed by Gulati in view of Ableidinger, Das, Sultana and Matsumoto with the logging levels as taught by Horley in order “to effectively reduce the level of priority associated with data received by the trace output device in a manner which can avoid that data stalling processing in an undesirable manner” (Horley [0019]).
Response to Arguments
Applicant's arguments, see Pages 6-11 of the Remarks filed November 7, 2025, with respect to the rejections under 35 U.S.C. 103 of Claims 1-15, and the subject matter of newly added Claim 16, have been fully considered but they are not persuasive.
With respect to the Applicant’s argument, Pages 9-10 of the Remarks, that the previously cited Das reference does not teach the newly amended language of Independent Claims 1 and 12, the Office respectfully disagrees. The Office contends that the previously cited Das (US PGPUB 2018/0278714) reference does teach the newly amended language recited in Independent Claims 1 and 12. The Office respectfully directs the Applicant’s attention to the newly modified rejections of claims 1 and 12 above for further explanation regarding how the Das reference has been interpreted as teaching the newly amended language of independent claims 1 and 12.
With respect to the Applicant’s further arguments, Pages 9-10 of the Remarks, that the features of the remaining claims are not taught by the cited prior art, the Office respectfully disagrees. These arguments rely upon the arguments as presented in relation to claims discussed above, and as such the Office directs the Applicant to the responses above regarding these arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Feather, JR. et al. (US PGPUB 2004/0139134) discloses a method of filtering commands which comprises receiving a command directed to a first device, dynamically determining state of the first device, and selectively directing the command to the first device or to a second device based on the determined first device state, wherein the filtered commands include commands comprising log data.
Woodruff et al. (“MultiLog: a tool for the control and output merging of multiple logging applications,” 2016) discusses a logging tool that controls, gathers, and combines the output, on-the-fly, from existing research and commercial logging applications.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.G.M/Examiner, Art Unit 2197
/BRADLEY A TEETS/Supervisory Patent Examiner, Art Unit 2197