DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed January 19th, 2023. Claims 1-20 are pending, of which claims 1-20 are currently rejected.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/19/2023 are in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 6-8 are objected to because of the following informalities:
Claim 6 Line 9 “a obtained quantity” should be “an obtained quantity”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “a first level state” on line 9. It is unclear if this mention of “a first level state” is the first level state as recited in claim 1 or some other first level state. For examination purposes, the first level state of claim 3 will be construed to be the first level state of claim 1. Appropriate correction is required.
Because claims 4-5 depend upon claim 3, claims 4-5 are additionally rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 4 recites the limitation “a second level state” on line 2. It is unclear if this mention of “a second level state” is the second level state as recited in claim 1 or some other second level state. For examination purposes, the second level state of claim 4 will be construed to be the second level state of claim 1. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Double Patenting Rejection #1
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claims 1, 2, 6, and 11 of U.S. Patent No. 12,260,900 (hereinafter “the ‘900 patent”). Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claims … of the ‘900 patent overlaps and encompasses the claimed subject matter as in claim 1 of the current application.
Current Application: 18/156,552
U.S. Patent No. 12,260,900
Claim 1:
An in-memory computing method, applied to an in-memory computing circuit, the in-memory computing circuit comprising a plurality of first memory cells, a plurality of second memory cells, and a sense amplifier, the first memory cells having the same quantity as the second memory cells, the method comprising:
performing level state control on the plurality of first memory cells according to first data to output a first voltage; and performing level state control on the plurality of second memory cells according to second data to output a second voltage; and
After receiving a predetermined operation instruction, receiving, by the sense amplifier, the first voltage and the second voltage, comparing the first voltage with the second voltage, and determining a comparison result of the first data and the second data according to a comparison result of the first voltage and the second voltage.
Claim 1: An in-memory computing circuit, comprising:
An initial computing circuit, configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result; and
A target computing circuit, configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result; wherein
The initial computing circuit comprises a first operational circuit and a second operational circuit,
The first operational circuit is configured to perform the first operation processing on the first data and the second data to output the first operation result; and
The second operational circuit is configured to perform the second operation processing on the first data and the second data to output the second operation result,
(claim 2: wherein the first operational circuit comprises a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sense amplifier, a word line control circuit, a plurality of first memory cells and a plurality of second memory cells)
(claim 2: wherein the word line control circuit is configured to, after a target first word line is determined, change a level state of the target first word line, and control level states of remaining first word lines except the target first word line according to the first data to obtain the level states of the plurality of first word lines; the first bit line is configured to determine a level state of the first bit line according to the first data; the plurality of first memory cells are configured to determine level states of the plurality of first memory cells according to the level states of the plurality of first word lines and the level state of the first bit line; the word line control circuit is further configured to control level states of the plurality of second word lines according to the second data to obtain the level states of the plurality of second word lines; the second bit line is configured to determine a level state of the second bit line according to the second data; the plurality of second memory cells are configured to determine level states of the plurality of second memory cells according to the level states of the plurality of second word lines and the level state of the second bit line; and the sense amplifier is configured to output the first operation result according to the level states of the plurality of first memory cells and the level states of the plurality of second memory cells.)
(claim 11: … first voltage provided by the plurality of first memory cells and second voltage provided by the plurality of second memory cells…)
(claim 6: the sense amplifier is configured to, after receiving a preset comparison instruction, read first voltage provided by the plurality of first memory cells and second voltage provided by the plurality of second memory cells, and perform comparison operation on the first data and the second data according to the first voltage and the second voltage to output the first operation result
wherein if the first voltage is higher than the second voltage, the first operation result output by the sense amplifier is a first result value; or, if the first voltage is lower than the second voltage, the first operation result output by the sense amplifier is a second result value.)
Claims 1, 2, 6, and 11 of the ‘900 patent fully anticipates claim 1 of the instant application. All the limitations contained within Claim 1 of the instant application are found identically within claims 1, 3, and 7 of the ‘900 patent as shown in the table above.
This is a nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-6 and 9-19 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wheeler et al. (US 2017/0053693 A1) included in the IDS filed January 19th, 2023 (hereinafter “Wheeler”).
Regarding claim 1, Wheeler teaches:
An in-memory computing method, applied to an in-memory computing circuit, the in-memory computing circuit (Wheeler: Abstract comparisons in memory) comprising a plurality of first memory cells, a plurality of second memory cells (Wheeler: Fig. 2E explained in ¶ 0123 - ¶ 0127 each MC is a plurality of memory cells, 270-0 first plurality 270-1 second plurality), and a sense amplifier (Wheeler: Fig. 2E element 268 as sense amplifier), the first memory cells having the same quantity as the second memory cells (Wheeler: Abstract memory cells in memory array, same number of memory cells for each plurality (each plurality as demonstrated in Fig. 2A, pluralities connected together as shown in Fig. 2E)), the method comprising:
performing level state control on the plurality of first memory cells according to first data to output a first voltage; and performing level state control on the plurality of second memory cells according to second data to output a second voltage (Wheeler: Figs. 2B-2D2 show level state control occurring for plurality of memory cells, which occurs respectively for each plurality of memory cells in order to store a value (voltage), also discussed in Abstract); and
after receiving a predetermined operation instruction, receiving, by the sense amplifier, the first voltage and the second voltage (Wheeler: all operations of device occur after an instruction such as for a SHIFT or OR operation is executed such as is seen in ¶ 0270-0275, and as discussed in ¶ 0005 where instructions are received and after which values are stored and compared in memory array), comparing the first voltage with the second voltage (Wheeler: Fig. 2E explained in ¶ 0123-0127 sense amplifier 268 receives values i.e., voltage from each of the plurality of memory cells), and determining a comparison result of the first data and the second data according to a comparison result of the first voltage and the second voltage (Wheeler: Fig. 2E explained in ¶ 0123-0127 comparison of values i.e., voltages is carried out; ¶ 0320 comparison of values and outputting a result to reflect which value is greater).
Regarding claim 2, Wheeler teaches:
The in-memory computing method of claim 1, wherein the performing level state control on the plurality of first memory cells according to first data to output a first voltage (Wheeler: ¶ 0032-0033 first value stored in first plurality of cells for comparison ¶ 0123-0127); and performing level state control on the plurality of second memory cells according to second data to output a second voltage (Wheeler: ¶ 0032-0033 first value stored in first plurality of cells for comparison ¶ 0123-0127) comprises:
after receiving a preset zero clearing instruction, controlling the plurality of first memory cells and the plurality of second memory cells to be in a first level state (Wheeler: ¶ 0064 zero clearing so cells are at first level state '0');
computing the first data and the second data respectively based on a preset bit algorithm to obtain a first quantity and a second quantity (Wheeler: ¶ 0041 row decoder and column decoder determine address values i.e., first and second values that are to be stored in plurality of memory cells, having certain quantity of 1s to be stored in memory array, Fig 3M for example shows 304-0 with value 10000 so there is a quantity of 1 memory cell that would need to be switched to a second level state out of the plurality of memory cells, this is done for each respective plurality of memory cells); and
after receiving a preset write instruction, controlling the first quantity of first memory cells to be adjusted from the first level state to a second level state, and controlling the second quantity of second memory cells to be adjusted from the first level state to the second level state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’; ¶ 0074 describes the order of instructions to be carried out for comparison of voltages to be carried out, starting with a clear instruction followed by write instruction and later a read instruction for sensing circuitry i.e., sense amplifier).
Regarding claim 3, Wheeler teaches:
The in-memory computing method of claim 2, wherein the in-memory computing circuit further comprises a plurality of first word lines, a plurality of second word lines, a word-line position control circuit, a first bit line, and a second bit line, the plurality of first word lines being connected to the plurality of first memory cells one by one, the plurality of second word lines being connected to the plurality of second memory cells one by one, the plurality of first memory cells being jointly connected to the first bit line, and the plurality of second memory cells being jointly connected to the second bit line (Wheeler: Fig. 2A memory cells 270-0 thru 270-N memory cells coupled to select lines i.e., word lines ¶ 0040 element 204-0 thru 204-N in Fig. 2A and coupled to sense lines i.e., digit or bit lines ¶ 0040 element 205-0 205-1 in Fig. 2A; ¶ 0044 control circuitry 140 as word line position control circuitry);
wherein the controlling the plurality of first memory cells and the plurality of second memory cells to be in a first level state comprises:
controlling, by the word-line position control circuit, the plurality of first word lines and the plurality of second word lines to be in an activated state, so that the plurality of first memory cells and the plurality of second memory cells are in a conducting state (Wheeler: ¶ 0091 describes the sense lines being activated through an equilibration signal deactivation via the word lines in order to put the word cells in an activated conducting state); and
performing, by the first bit line, zero clearing processing on the plurality of first memory cells in the conducting state, and performing, by the second bit line, zero clearing processing on the plurality of second memory cells in the conducting state, so that the plurality of first memory cells and the plurality of second memory cells are in the first level state (Wheeler: ¶ 0064 clearing of memory cells before and between comparison operation is executed; ¶ 0043 by sense lines i.e., digit lines and select lines i.e., word lines values are decoded and set at memory cells, including clearing of values which is done by setting of values to first level state ‘0’ as discussed in ¶ 0080).
Regarding claim 4, Wheeler teaches:
The in-memory computing method of claim 3, wherein the controlling the first quantity of first memory cells to be adjusted from the first level state to a second level state, and controlling the second quantity of second memory cells to be adjusted from the first level state to the second level state comprises:
controlling, by the word-line position control circuit (Wheeler: ¶ 0044 control circuitry 140 as word-line position control circuit, that provides instructions and enable signals for write operations and clearing instructions for example), the first quantity of first word lines to be in the activated state, and controlling the first bit line to perform write processing on the first memory cells connected to the first word lines in the activated state, so that the first quantity of first memory cells are adjusted from the first level state to the second level state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’); and
controlling, by the word-line position control circuit, the second quantity of second word lines to be in the activated state, and controlling the second bit line to perform write processing on the second memory cells connected to the second word lines in the activated state, so that the second quantity of second memory cells are adjusted from the first level state to the second level state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’).
Regarding claim 5, Wheeler teaches:
The in-memory computing method of claim 3, wherein the receiving, by the sense amplifier, the first voltage and the second voltage comprises:
controlling, by the word-line position control circuit (Wheeler: ¶ 0044 control circuitry 140 as word-line position control circuit, that provides instructions and enable signals for write operations and clearing instructions for example), the plurality of first word lines and the plurality of second word lines to be in the activated state, so that the plurality of first memory cells and the plurality of second memory cells are in the conducting state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’; ¶ 0091 describes the sense lines being activated through an equilibration signal deactivation via the word lines in order to put the word cells in an activated conductance state); and
controlling the sense amplifier to perform read processing on the plurality of first memory cells and the plurality of second memory cells in the conducting state, receive, through the first bit line, the first voltage output by the plurality of first memory cells, and receive, through the second bit line, the second voltage output by the plurality of second memory cells (Wheeler: ¶ 0041 reading through sensing circuitry i.e., sense amplifier the voltages from the various bit lines; Fig. 2E shows SSA 268 receiving voltages from primary sense amplifiers that receive voltages from plurality of memory cells and as discussed ¶ 0268 receives voltages from sense lines i.e., bit lines).
Regarding claim 6, Wheeler teaches:
The in-memory computing method of claim 2, wherein the computing the first data and the second data respectively based on a preset bit algorithm to obtain a first quantity and a second quantity comprises:
determining values of data to be processed at different data bits (Wheeler: Fig. 3A shows different values of bits being processed at each row and every three rows shows additional processing in order to determine a value);
when a value of the data to be processed at an i-th data bit is a predetermined value (Wheeler: Fig. 3A each bit position has a predetermined value, from least significant to most significant would be 1, 2, 4), determining a quantity corresponding to the i-th data bit as mi (Wheeler: Fig. 3A for example at 304-0 in the first column the least significant bit is a 1 so it’d have a value of 1, the next bit is also a 1 so it’d have a value of 2, and the most significant bit is a 0 so the value would be 0.); wherein i is a positive integer and mi is a positive integer (Wheeler: Fig. 3A as discussed with the previous example the bit position/index i is 1 which is a positive integer, and the value mi of the bit position/index of 1 is 2 which is also a positive integer);
performing a summation operation on a quantity corresponding to each of the data bits to obtain a quantity corresponding to the data to be processed (Wheeler: Fig. 3A the first column at 304-0 the values of the bits were 1+2+0=3 320-0 shows the summation of the value of bits as 3); and
determining the first quantity according to a obtained quantity when the data to be processed is the first data (Wheeler: Fig. 3A the operation as shown is carried out for each of the quantities of respective first and second pluralities of memory cells in the memory array in order to carry out comparison of values and voltages); and determining the second quantity according to the obtained quantity when the data to be processed is the second data (Wheeler:: Fig. 3A the operation as shown is carried out for each of the quantities of respective first and second pluralities of memory cells in the memory array in order to carry out comparison of values and voltages).
Regarding claim 9, Wheeler teaches:
The in-memory computing method of claim 1, wherein the first level state is a low level state and the second level state is a high level state (Wheeler: ¶ 0041 a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ or low level state to a second level state ‘1’ or high level state);
correspondingly, wherein the determining a comparison result of the first data and the second data according to a comparison result of the first voltage and the second voltage (Wheeler: ¶ 0320 comparison of values and yielding of result of which value is greater) comprises:
in a case where the first voltage is higher than the second voltage, outputting, by the sense amplifier, a first result value; wherein the first result value indicates that the first data is greater than or equal to the second data (Wheeler: ¶ 0320 comparison of values and yielding of result of which value is greater); and
in a case where the first voltage is less than the second voltage, outputting, by the sense amplifier, a second result value; wherein the second result value indicates that the first data is less than the second data (Wheeler: ¶ 0320 comparison of values and yielding of result of which value is greater).
Claims 10, 12, and 15 recite the in-memory computing circuit performed by the elements of the method recited in claims 1, 3, and 9 respectively and are therefore rejected for the same reasons therein.
Regarding claim 11, Wheeler teaches:
The in-memory computing circuit of claim 10, wherein, the plurality of first memory cells are specifically configured to control a first quantity of first memory cells to be in a second level state and control other first memory cells other than the first quantity to be in a first level state (Wheeler: ¶ 0041 to store values depending on the bit values a ‘0’ first level state or ‘1’ second level state is stored in each of the cells of the plurality of cells, the first quantity of memory cells being controlled to be ‘1’ while a quantity other than the first quantity is controlled to be ‘0’);
the plurality of second memory cells are specifically configured to control a second quantity of second memory cells to be in the second level state and control other second memory cells other than the second quantity to be in the first level state (Wheeler: ¶ 0041 to store values depending on the bit values a ‘0’ first level state or ‘1’ second level state is stored in each of the cells of the plurality of cells, the second quantity of memory cells being controlled to be ‘1’ while a quantity other than the second quantity is controlled to be ‘0’);
wherein the first quantity is determined according to the first data, and the second quantity is determined according to the second data (Wheeler: ¶ 0041 row decoder and column decoder determine address values i.e., first and second values that are to be stored in plurality of memory cells, having certain quantity of 1s to be stored in memory array, Fig 3M for example shows 304-0 with value 10000 so there is a quantity of 1 memory cell that would need to be switched to a second level state out of the plurality of memory cells, this is done for each respective plurality of memory cells).
Regarding claim 13, Wheeler teaches:
The in-memory computing circuit of claim 12,
wherein the word-line position control circuit is further configured to after receiving a preset write instruction, control the first quantity of first word lines to be in the activated state, and control the second quantity of second word lines to be in the activated state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’; ¶ 0091 describes the sense lines being activated through an equilibration signal deactivation via the word lines in order to put the word cells in an activated conductance state);
the first bit line is further configured to perform write processing on the first memory cells connected to the first word lines in the activated state, so that the first quantity of first memory cells are adjusted from the first level state to the second level state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’; ¶ 0091 describes the sense lines being activated through an equilibration signal deactivation via the word lines in order to put the word cells in an activated conductance state); and
the second bit line is further configured to perform write processing on the second memory cells connected to the second word lines in the activated state, so that the second quantity of second memory cells are adjusted from the first level state to the second level state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’; ¶ 0091 describes the sense lines being activated through an equilibration signal deactivation via the word lines in order to put the word cells in an activated conductance state).
Regarding claim 14, Wheeler teaches:
The in-memory computing circuit of claim 12, wherein, the word-line position control circuit is further configured to control (Wheeler: ¶ 0044 control circuitry 140 as word-line position control circuit, that provides instructions and enable signals for write operations and clearing instructions for example; ¶ 0074 discusses how a comparison operation i.e., instruction would need to be performed via other instructions such as read or write operations), after receiving a preset comparison instruction, the plurality of first word lines and the plurality of second word lines to be in the activated state, so that the plurality of first memory cells and the plurality of second memory cells are in the conducting state (Wheeler: ¶ 0041 describes after a clearing operation i.e., instruction is executed, a write operation i.e., write instruction is executed in order to write first and second values to the first and second quantity of writing cells in respective first and second plurality of memory cells from a first level state ‘0’ to a second level state ‘1’; ¶ 0091 describes the sense lines being activated through an equilibration signal deactivation via the word lines in order to put the word cells in an activated conductance state); and
the sense amplifier is further configured to after receiving the preset comparison instruction, perform read processing on the plurality of first memory cells and the plurality of second memory cells in the conducting state, receive the first voltage output by the plurality of first memory cells through the first bit line, and receive the second voltage output by the plurality of second memory cells through the second bit line (Wheeler: ¶ 0041 reading through sensing circuitry i.e., sense amplifier the voltages from the various bit lines; Fig. 2E shows SSA 268 receiving voltages from primary sense amplifiers that receive voltages from plurality of memory cells and as discussed ¶ 0268 receives voltages from sense lines i.e., bit lines; a sense amplifier would receive voltages to compare after read and writing instructions occur, so after a present comparison instruction is received as well).
Regarding claim 16, Wheeler teaches:
The in-memory computing circuit of claim 10, wherein the sense amplifier comprises a first terminal and a second terminal (Wheeler: Fig. 2E SSA 268 has first and second terminal), and each of the plurality of first memory cells and each of the plurality of second memory cells comprises a memory switch transistor (Wheeler: ¶ 0059-0060 each plurality of cells comprises a pass transistor i.e., memory switch transistor, having drain region coupled to SSA); and
the first terminal of the sense amplifier is connected to a drain terminal of the memory switch transistor in the plurality of first memory cells through the first bit line, and the second terminal of the sense amplifier is connected to a drain terminal of the memory switch transistor in the plurality of second memory cells through the second bit line (Wheeler: ¶ 0059-0060 each plurality of cells comprises a pass transistor i.e., memory switch transistor, having drain region coupled to SSA).
Regarding claim 17, Wheeler teaches:
The in-memory computing circuit of claim 16, wherein the in-memory computing circuit further comprises a plurality of first adjacent memory cells, a plurality of second adjacent memory cells, a first adjacent bit line, a second adjacent bit line, and an adjacent sense amplifier, the plurality of first adjacent memory cells being connected to the adjacent sense amplifier through the first adjacent bit line (Wheeler: Fig. 2E shows adjacent memory cells 270-0 first adjacent memory cells thru 270-F second adjacent memory cells, 205-0 thru 205-M as adjacent bit lines, and adjacent sense amplifiers 206-1 thru 206-P), and the plurality of second adjacent memory cells being connected to the adjacent sense amplifier through the second adjacent bit line (Wheeler: Fig. 2E shows adjacent memory cells 270-0 first adjacent memory cells thru 270-F second adjacent memory cells, 205-0 thru 205-M as adjacent bit lines, and adjacent sense amplifiers 206-1 thru 206-P);
the in-memory computing circuit further comprises a plurality of first isolation switch transistors and a plurality of second isolation switch transistors (Fig. 2E shows first isolation switch transistors and second isolation switch transistors for each corresponding plurality of memory cells 270-0 thru 270-F and discusses these transistors being selectively activated at ¶ 0124);
an a-th first isolation switch transistor is arranged between an a-th first adjacent memory cell and an a-th first memory cell that are located on a same first word line (Wheeler: ¶ 0125 discusses that the isolation switch transistors are arranged between the first adjacent memory cell, or the first memory cell, based on what data is being transferred to the sense amplifier and from which memory cell this information will be taken from, element 264 is either activated or deactivated and the corresponding transistor is also activated);
a b-th second isolation switch transistor is arranged between a b-th second adjacent memory cell and a b-th second memory cell that are located on a same second word line (¶ 0125 discusses that the isolation switch transistors are arranged between the first adjacent memory cell, or the first memory cell, based on what data is being transferred to the sense amplifier and from which memory cell this information will be taken from, element 264 is either activated or deactivated and the corresponding transistor is also activated);
wherein both a and b are positive integers (Wheeler: Fig. 2E in this case there are two transistors for each adjacent memory cell, therefore a and b would be 1 and 2 correspondingly).
Regarding claim 18, Wheeler teaches:
The in-memory computing circuit of claim 17, wherein each of the plurality of first adjacent memory cells and each of the plurality of second adjacent memory cells comprises a memory switch transistor (Wheeler: ¶ 0059-0060 each plurality of cells comprises a pass transistor i.e., memory switch transistor, having drain region coupled to SSA, in Fig. 2A these transistors would be 207 and 208);
a drain terminal of the a-th first isolation switch transistor is connected to a gate terminal of a memory switch transistor in the a-th first memory cell through the first word line, and a source terminal of the a-th first isolation switch transistor is connected to a gate terminal of a memory switch transistor in the a-th first adjacent memory cell through the first word line (Wheeler: all of Fig. 2A is represented by MC in Fig. 2E, the transistors of Fig. 2A i.e., switch transistors are coupled through the SA’s to the isolation switch transistors 218); and
a drain terminal of the b-th second isolation switch transistor is connected to a gate terminal of a memory switch transistor in the b-th second memory cell through the second word line, and a source terminal of the b-th second isolation switch transistor is connected to a gate terminal of a memory switch transistor in the b-th second adjacent memory cell through the second word line (Wheeler: all of Fig. 2A is represented by MC in Fig. 2E, the transistors of Fig. 2A i.e., switch transistors are coupled through the SA’s to the isolation switch transistors 218).
Regarding claim 19, Wheeler teaches:
A semiconductor memory, comprising the in-memory computing circuit of claim 10 (Wheeler: ¶ 0002 teaches the apparatus being taught as a semiconductor device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wheeler in view of Bedeschi (US 11646070) (hereinafter “Bedeschi”).
Regarding claim 7, while Wheeler teaches determining a first and second quantity and whichever quantity is greater (Wheeler: Fig. 3A the operation as shown is carried out for each of the quantities of respective first and second pluralities of memory cells in the memory array in order to carry out comparison of values and voltages; ¶ 0132 comparison operation between values), as well as the first quantity being less than the second quantity when the first data is less than the second data and vice versa (Wheeler: Fig. 3M for example, depending on the value of the first data “110” the value of which is 3 or second data “000” the value of which is 0 of first and second columns correspondingly, is the first quantity of “1” bits which is 2 or the second quantity of “1” bits which is 0; the first quantity and first value correspond as do the second quantity and second value so if the first data is greater than the second data, the first quantity will be greater than the second data, and if the first data is less than the second data, the first quantity will be lesser than the second data) Wheeler does not explicitly teach adding one to an obtained quantity if the obtained quantity is the first quantity.
However, Bedeschi teaches adding one to an obtained quantity if the quantity obtained is the first quantity (Bedeschi: Col. 11 Lines 58-63).
It would be obvious before the effective filing date of the claimed invention to combine the adding of 1 to a quantity of bits as taught by Bedeschi with the in-memory computing circuit as taught by Wheeler as both teachings are directed towards in-memory computing using a memory array. One with ordinary skill in the art would be motivated to combine the teachings because this would help balance codewords which increases efficiency in encoding or decoding (Bedeschi: Col. 11 Lines 58-63).
Regarding claim 20, while Wheeler teaches the semiconductor memory as recited in claim 19 as well as a comparison result based on the first data and second data and obtaining the comparison result, Wheeler does not explicitly teach weight processing.
However, Bedeschi teaches weight processing being carried out with respect to respective values (Bedeschi: Col. 11 Lines 58-67).
It would be obvious before the effective filing date of the claimed invention to combine the weight processing as taught by Bedeschi with the semiconductor memory as taught by Wheeler because both teachings are directed towards in-memory computing. One with ordinary skill in the art would be motivated to combine the teachings because it would be more efficient to carry out weight processing within memory itself rather than in the processor (Bedeschi: Col. 13 Lines 58-67).
Claim 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wheeler in view of Bodiga et al. (US 2021/0051503 A1) (hereinafter “Bodiga”).
While Wheeler teaches the in-memory computing method of claim 6, Wheeler does not teach mi being a (i+1)th power of 2.
However, Bodiga teaches assigning power-of-two numbers mi that correspond to different bit positions i in a binary word, which can include mi being a (i+1)th power of 2 (Bodiga: ¶ 0077).
It would be obvious before the effective filing date of the claimed invention to combine the computing method as taught by Wheeler with the assigning of power-of-two numbers that correspond to different bit positions because both teachings are directed towards storing of data in memory. One with ordinary skill in the art would be motivated to combine the teachings because this would allow for more management of computation on the binary words (Bodiga: ¶ 0077).
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sugimoto (US 2018/0096725 A1) teaches a semiconductor storage device having N word lines, M bit lines and an array of memory cells used for storing binary data and in-memory computing.
Perner (US 2006/0050582 A1) teaches receiving by a sense amplifier a voltage in order to compare to a reference voltage and output a state indicate of which voltage is greater.
Kota et al. (US 11164610) teaches a memory device with various sense amplifiers, various comparators and a memory array for a redundant in-memory computing circuit.
Boniardi et al. (US 11037613) a memory device for storing data in an array of memory cells and having data stored in various portions of the memory array as well as sense circuitry coupled to the array in order to determine values of data at various portions of the memory array.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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