Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reissue Applications
Applicants arguments dated September 23, 2025 have been considered and are persuasive. However a new ground of rejection appears below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9-12, and 14-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khotimsky et al. (ITU-T G.987.3 “XP-PON Transmission Convergence Layer Specification”; Motorola, Huawei, Mitsubishi; Geneva 31 May-11 June 2010) (cited by Applicant in IDS) (hereinafter PON).
As to claim 1, PON teaches method comprising: generating a raw data frame (p. 43, section 10.1 “downstream PHY frame”), wherein the raw data frame comprises a physical synchronization block (PSB) (Fig. 10-1 shows PSHd; also see 10.1.1) and raw data (FEC data/codewords); generating a preload pattern based on a target bit wherein the target bit is a part of bits in a superframe counter (SFC) value corresponding to the raw data frame (p 50, lines 16-17; 58-bit preload value derived by inserting 1 bit every 7 bits, the inserted bit value is the inverse of the superframe counter bit prior to it); and scrambling the raw data based on the preload pattern to obtain target data (section 10.4.1 and 10.4.2 and Fig. 10-8, upstream PHY burst is scrambled) wherein a difference between a number of bits whose values are 0 and a number of bits whose values are 1 in the preload pattern is less than a preset value (the difference between the number of ones and zeroes in the 58-bit reload pattern is at most 51-7=44).
As to claim 3, PON discloses scrambling the raw data based on the preload pattern to obtain the target data comprises: performing an operation on the preload pattern according to a polynomial operation rule preset in a scrambler to generate a target pattern, and performing an exclusive OR operation on each bit of the raw data based on the target pattern to obtain the target data (p. 50 lines 11-12 and Fig 10-8; the LFSR shown implements the polynomial equation X58 + x39 + 1 and XOR’s the bit with a corresponding LFSR bit.
As to claim 4, PON discloses the length of the preload pattern is M bits, M being an integer greater than 1 (i.e. 58-bit preload pattern M = 8), wherein the target bit comprises N least significant bits in the SFC value (at least the last bit of the SFC value is a target bit), and wherein M is greater than or equal to 2 times of N (58>2*1).
Claims 5 and 6 are rejected for similar reasons as stated above. PON shows wherein generating the preload pattern based on the target bit comprises: determining an opposite value of a value of each bit in the target bit; and arranging the value of each bit in the target bit and the opposite value (i.e. inverse) of the value of each bit in the target bit to obtain the preload pattern.
Claims 7, 9-11 are rejected for similar reasons as stated above. Furthermore it is inherent that one would have to descramble the scrambled signal in order to utilize the data contained in it.
Claims 12, 14-17 are rejected for similar reasons as stated above. Furthermore PON discloses an optical transceiver (p. 1 line 4).
As to claim 18, PON discloses the at least one processor is further configured to generate the preload pattern based on the target bit and a preset data pattern (section 10.4.1 shows the preload value is derived by inserting 1 bit between every 7 bits of the superframe counter, which is the inverse value of the counter bit prior to it).
As to claim 19, PON discloses the at least one processor is further configured to send a target data frame comprising the target data and the PSB (fig. 10-8 “scrambled data out”).
Claims 20-23 are rejected for similar reasons as stated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph E Avellino whose telephone number is (571)272-3905. The examiner can normally be reached Monday-Friday 7:00am-3:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JOSEPH E. AVELLINO
Supervisory Patent Examiner
Art Unit 2478
/JOSEPH E AVELLINO/Supervisory Patent Examiner, Art Unit 2478
Prosecution Insights