DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 1-19 allowed.
The following is an examiner’s statement of reasons for allowance: Prior art does not teach or render obvious “a circuit that generates first histogram data and second histogram data in the memory based on the generated signals during first and second collection subframes of a frame respectively using first and second mappings of time to bins respectively, wherein the second mapping of time to bins for the second collection subframe exhibits shorter bin widths than the first mapping of time to bins for the first collection subframe; and wherein a range to a target in in the field of view is resolvable in the event of a pile-up condition for the photodetector based on (1) data indicative of a coarse range estimate derived from the first histogram data and (2) data indicative of a range adjustment derived from the second histogram data”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by D1 EP 3370078 A1.
Regarding claims 20 D1 teaches
a photodetector having a field of view, wherein the photodetector generates signals in response to incident light over time;(5a)
a memory comprising a plurality of bins;(implicit)
a circuit that maps the signals to bins within the memory during a frame acquisition period, wherein the frame acquisition period includes a diffuse acquisition phase(543) and a retroreflector resolution phase(541), wherein the diffuse acquisition phase encompasses a first plurality of light pulse cycles, wherein the retroreflector resolution phase encompasses a second plurality of light pulse cycles;(implicit data collected during both phases)
wherein the circuit, for the diffuse acquisition phase, maps signals to bins within a first set of the bins according to a first map that relates the bins within the first set to time to generate first histogram data;(fig. 5B)
wherein the circuit, for the retroreflector resolution phase, maps signals to bins within a second set of the bins according to a second map that relates the bins within the second set to time to generate second histogram data;(fig. 5B)
wherein the first histogram data can be processed to detect a pileup condition based on defined criteria; (fig. 2A 201)and
wherein the second histogram data can be processed to resolve a range to an object in the field of view in the event the pileup condition is detected.(207)
Conclusion
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/HOVHANNES BAGHDASARYAN/Examiner, Art Unit 3645