Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This final action is responsive to amendment filed on 06/03/2026. In this amendment, claims 1, 24 and 29 have been amended. Claims 1, 2, 4, 8, 11, and 24-33 are pending, with claims 1, 24 and 29 being independent.
Priority
This application claims the benefit of US Provisional Patent Application No. 63/477,584, filed December 29, 2022.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 1, 24 and 29 are objected to because of the following informalities:
There are two periods (.) in each of the claims.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4, 8, 11, and 24-33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “generate, using forest of random subsets (FORS) tree circuitry. a second public key root and return an indicator of a successful signature verification in response to the first public key root matching the second public key root.” The specification does not describe or indicate that these steps performed by the FORS tree circuitry. The specification indicates that these steps performed by the hypertree verification circuitry, not by the FORS tree circuitry as claimed.
Claim 24 has the same issue as claim 1 and is rejected for the same reasons as detailed above.
Dependent claims 2, 4, 8, 11, and 25-33 are rejected for the same reasons as detailed above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 11, 24-26, 28-31, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (US 2017/0357496) in view of Lablans (US 2016/0366109) and further in view of Amiet et al. (npl: FPGA-based SPHINCS+ Implementations, published 2020).
In regard to claim 1, Smith disclosed an apparatus comprising:
a signature verification memory to store verification input data; and (Smith Figure 1, memory 128)
processing circuitry to:
read input data from the signature verification memory, (Smith [0083])
perform a Secure Hash Algorithm (SHA) operation to generate output data, and write the output data to the signature verification memory, the reading, performing, and writing being executed substantially in parallel;
compute a message representative of the input data, wherein the message includes a first public key root; and (Smith [0083])
generate a second public key root and return an indicator of a successful signature verification in response to the first public key root matching the second public key root. (Smith [0083])
Smith failed to disclose perform a Secure Hash Algorithm (SHA) operation to generate output data, and write the output data to the signature verification memory, the reading, performing, and writing being executed substantially in parallel, and generate, using forest of random subsets (FORS) tree circuitry. the second public key root and return the indicator.
However, Lablans disclosed perform a Secure Hash Algorithm (SHA) operation to generate output data, and write the output data to the signature verification memory, the reading, performing, and writing being executed substantially in parallel. Lablans disclosed a SHA operation in at least Lablans [0104], [0121], [0145]. Lablans disclosed the reading, performing, and writing being executed substantially in parallel in at least Lablans [0209]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a SHA hash function with Smith to provide enhanced security to the system of Smith. Smith used a hash function in at least Smith [0083]. It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform operations in parallel in order to speed up performance in the Smith system.
Smith in view of Lablans disclosed generate the second public key root and return the indicator, but does not explicitly disclose generate the second public key root and return the indicator using forest of random subsets (FORS) tree circuitry.
Amiet teaches forest of random subsets (FORS) tree circuitry (Amiet pg. 231, SPHINCS+ finally is a combination of FORS and a large fractal Merkle tree… This section describes our FPGA-based hardware architecture for the SPHINCS+ scheme).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the FPGA-based hardware architecture for the SPHINCS+ scheme and a component for generating the second public key root and returning the indicator because in combination, each element merely performs the same function as it does separately and the combination would yield the predictable results of using the FPGA-based hardware architecture to generate the second public key root and return the indicator.
In regard to claim 2, Smith disclosed wherein the signature verification memory is configured to store one or more of the input data, the message, public keys, or signatures. Smith Figure 1, item 126
In regard to claim 4, Lablans disclosed wherein the SHA operation is based on a SHAKE256 hash function. Lablans [0185]
In regard to claim 11, Smith disclosed wherein the processing circuitry comprises one or more of application processing circuitry or graphics processing circuitry. Smith, Figure 1, item 120
Claim 24 is rejected for substantially the same reasons as claim 1.
Claim 25 is rejected for substantially the same reasons as claim 2.
Claim 26 is rejected for substantially the same reasons as claim 4.
Claim 28 is rejected for substantially the same reasons as claim 11.
Claim 29 is rejected for substantially the same reasons as claim 1.
Claim 30 is rejected for substantially the same reasons as claim 2.
Claim 31 is rejected for substantially the same reasons as claim 4.
Claim 33 is rejected for substantially the same reasons as claim 11.
Claims 8, 27, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Lablans as applied to claims 1, 24 and 29 above, in view of Amiet et al. (npl: FPGA-based SPHINCS+ Implementations, published 2020), and further in view of Kuo et al. (US 2024/0126928).
In regard to claim 8, Smith in view of Lablans in view of Amiet failed to disclose wherein the processing circuitry is further configured to divide the message into message blocks and concatenate the message blocks into a data item such that the SHA operation is performed on the data item to contribute to the output data.
However, Kuo disclosed wherein the processing circuitry is further configured to divide the message into message blocks and concatenate the message blocks into a data item such that the SHA operation is performed on the data item to contribute to the output data. Kuo [0060]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to divide a message in Smith into multiple data blocks as in Kuo when performing a SHA hash operation, in order to verify the signature present in Smith / Lablans.
Claim 27 is rejected for substantially the same reasons as claim 8.
Claim 32 is rejected for substantially the same reasons as claim 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11362835 B2; Efficient Post-quantum Anonymous Attestation With Signature-based Join Protocol And Unlimited Signatures
Subject matter described herein relates generally to the field of computer security and more particularly to attestation schemes for post-quantum cryptography using secure hash-based signing and verification.
US 20190319804 A1; Unified Accelerator For Classical And Post-Quantum Digital Signature Schemes In Computing Environments
Embodiments described herein relate generally to data processing and more particularly to facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments.
US 11722313 B2; State Synchronization For Post-quantum Signing Facilities
Subject matter described herein relates generally to the field of computer security and more particularly to code signing facilities for post-quantum cryptography secure hash-based signatures, including but not limited to the Extended Merkle Signature Scheme (XMSS) and Leighton/Micali Signature (LMS) hash-based signing and verification algorithms.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KHANG DO/Primary Examiner, Art Unit 2492
