DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of claims 1-8 in the reply filed on 09/09/2026 is acknowledged.
Claims 9-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/09/2026.
Information Disclosure Statement
The Information disclosure statements (IDS) filed on 01/20/2023 and 12/01/2025 has/have been acknowledged.
Claim Objections
Claims 2-7 are objected to because of the following informalities:
· “a state of generating higher leakage current” in claims 2, 3, 4, 5, 6, and 7 should read as -- the state of generating higher leakage current --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 8 line 1-3 recites the limitation “wherein the higher leakage current is equal to or higher than a value obtained by multiplying an area of a piezoelectric element by 0.1 A”. However, in this mathematical expression, the unit of the area of the piezoelectric element is not specified, therefore depending on the units used for the area, the calculated values for leakage current can vary wildly; Further, it is understood by the examiner that the leakage current would also depend on a variety of different variables such as voltage applied, poling temperature, the type of TFT, the materials, thicknesses, and size of the components of the TFT, etc., theretofore changing one or more of these variables would also result in different leakage currents, thereby rendering the claim indefinite as the metes and bounds of the claim are not sufficiently clear. Furthermore, the specification, the drawings, and the claims as originally filed lack any explanation of the leakage current being equal to or higher than a value obtained by multiplying an area of a piezoelectric element by 0.1 A or any potential benefits of the leakage current specifically being equal to or higher than the claimed value obtained by multiplying an area of a piezoelectric element by 0.1 A; therefore this limitation lack criticality for the claimed invention. For the purpose of examination, the examiner interprets this limitation to mean that the higher leakage current is higher than a leakage current of the thin-film transistor before the poling process.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 8 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by JP 2009-300941 to Suzuki (translation provided by examiner).
As per claim 1, Suzuki discloses a method of manufacturing a piezoelectric element array board, comprising:
fabricating a plurality of piezoelectric element control circuits including one or more thin-film transistors (see multiple TFTs represented by gates 26, gate insulating films 24, source/drain regions 22, and base film 20; also see TFT circuit layer 44 in Fig 2) on a substrate (see substrate 10 in Fig 1);
fabricating a piezoelectric element (see piezoelectric layer 16 in Fig 1) on the substrate; and
poling a piezoelectric material by applying an electric field (see Fig 1C and 4; see translation Page 7-9) to a piezoelectric material layer (see piezoelectric layer 16 in Fig 1 and 4; also see piezoelectric layer 42 in Fig 2) of the piezoelectric element while maintaining the one or more thin-film transistors in a state of generating higher leakage current (the specification of the current application confirms that elevated temperatures generate higher leakage currents in TFTs, therefore since translation Page 8 discloses that a poling temperature of 200 °C is used for the poling operation, the temperature of the TFTs would be at the poling temperature and therefore would generate higher leakage current during the poling operation as claimed), after fabricating the plurality of piezoelectric elements and the plurality of piezoelectric element control circuits (see Fig 1-2 and 4; see translation Page 7-9).
As per claim 2, Suzuki discloses the elements of the current invention as detailed above with respect to claim 1. Suzuki further discloses that the maintaining the one or more thin-film transistors in a state of generating higher leakage current includes heating the piezoelectric element array board (see translation Page 8 that discloses heating the TFTs and the piezoelectric element array board to a poling temperature of 200 °C).
As per claim 8, Suzuki discloses the elements of the current invention as detailed above with respect to claim 1. As best understood, Suzuki further discloses the following from claim 8: the higher leakage current of the TFT during the poling process is higher than a leakage current of the thin-film transistor before the poling process (the specification of the current application confirms that elevated temperatures generate higher leakage currents in TFTs, therefore since translation Page 8 discloses that a poling temperature of 200 °C is used for the poling operation, the leakage current of the TFTs would be higher during poling than before poling).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under AIA 35 U.S.C. 103 as being unpatentable over JP 2009-300941 to Suzuki (translation provided by examiner) in view of US 2008/0033298 to Habu.
As per claims 3-4, Suzuki discloses the elements of the current invention as detailed above with respect to claim 2, but Suzuki does not disclose maintaining the piezoelectric element board in a state of not less than 60° C. and not more than 100° C during the poling from claim 3 or not less than 70° C. and not more than 90° C during the poling from claim 4. However, discovering the optimum or workable ranges of temperature involves only ordinary skill in the art and therefore it would have been an obvious design choice for one of ordinary skill in the art to modify the temperature of the poling operation depending on a particular application of the invention.
Habu discloses a similar process for poling/polarizing a piezoelectric element (see piezoelectric element 1 in Fig 3) wherein the piezoelectric element is maintained at a temperature preferably between 60-200° C (see Para 0066) in order to effectively polarize the piezoelectric element (Para 0063-0066).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to have modified the poling temperature of Suzuki which the piezoelectric element array board is maintained during poling to be not less than 60° C. and not more than 100° C and/or not less than 70° C and not more than 90° C as taught by Habu. One of ordinary skill in the art would have recognized that discovering the optimum or workable ranges of temperatures of operations such as poling involves only ordinary skill in the art, and that Habu involves process for poling/polarizing piezoelectric elements similar to Suzuki and consequently it would have been obvious to one of ordinary skill in the art to look Habu for improvements, therefore it would have been an obvious design choice for one of ordinary skill in the art to modify the poling temperature to be between 70° C and 90° C as taught by Habu based on a particular intended application of the invention, the obvious advantages being that the poling temperature would help enable the poling/polarizing of the piezoelectric element as would be generally understood by one of ordinary skill in the art.
Potentially Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5-7 are directed towards a method of manufacturing a piezoelectric element array board dependent upon independent claim 1. The prior art fails to disclose or render obvious all of the limitations of claims 5-7; specifically the prior art fails to disclose the following limitations in combination with the other limitations of claims 5-7 respectively:
poling a piezoelectric material layer of a piezoelectric element array board comprising one or more thin-film transistors, wherein the poling includes applying an electric field to the piezoelectric material layer while maintaining the one or more thin-film transistors in a state of generating higher leakage current by irradiating the one or more thin-film transistors with light.
JP 2009-300941 to Suzuki and US 2008/0033298 to Habu used in the above office action disclose methods of poling a piezoelectric material, but neither Suzuki nor Habu disclose or render obvious that during the poling operation thin-film transistor is irradiated with light to generate higher leakage current during the poling operation after fabricating the thin-film transistors and the piezoelectric material.
US 2021/0036215, US 2018/0198055, US 2017/0310087, and US 2021/0266678 also disclose methods for poling a piezoelectric material, but also fail to disclose or render obvious that during the poling operation thin-film transistor is irradiated with light to generate higher leakage current during the poling operation after fabricating the thin-film transistors and the piezoelectric material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua D. Anderson, whose telephone number is (571) 270-0157. The examiner can normally be reached from Monday to Friday between 7 AM and 2 PM Arizona time.
If any attempt to reach the examiner by telephone is unsuccessful, the examiner’s supervisor, Thomas Hong, can be reached at (571) 272-0993.
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Applicants are invited to contact the Office to schedule an in-person interview to discuss and resolve the issues set forth in this Office Action. Although an interview is not required, the Office believes that an interview can be of use to resolve any issues related to a patent application in an efficient and prompt manner.
/JOSHUA D ANDERSON/
Examiner, Art Unit 3729
/JEFFREY T CARLEY/Primary Examiner, Art Unit 3729
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