DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataraman et al. 20220308770 herein Venkataraman and Gray et al 10802762 herein Gray in view of Lindemann et al. 20040028232 herein Lindemann.
Per claim 1, Venkataraman discloses: a controller circuit; a first compute function of a first application; a second compute function of the first application; a common memory area; and a persistent storage device, (fig. 8 ;the examiner notes that the compute functions are merely r/w/ permission as seen in applicant fig. 3B) the controller circuit being configured: to receive a first request from a host, the first request defining a first allocated function data memory region, for the first compute function, and granting the first compute function read permission and write permission within the first allocated function data memory region; (¶0055 and ¶0073; a first application 802 is associated with an owner read write privilege for a first address space 806. Thus, the controller 106 may grant read and write requests directed to the first address space 806 from the first application 802. A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804) to receive a first memory access request, from the first compute function, for a first memory location in the common memory area and outside the first allocated function data memory region; and to deny the first memory access request in response to the first compute function lacking read or write permission for the first memory location(¶0074; the controller 106 may deny a write request from the second application 804 directed to the first address space 806 in response to determining that the second application 804 is granted read access but not write access to the first address space 806. Similarly, the controller 106 may deny requests to access the second address space 808 from the first application 802. Further, the first application 802 may lack page information associated with the second address space 808).
Venkataraman does not specifically disclose: the first request including a payload and a batch request, the batch request comprising a request to perform one or more operations on one or more data sets.
However, Gray discloses: the first request including a payload and a batch request, (col. 4; As shown in FIG. 2, asynchronous storage system 210 may group (at 3 and 3′) data from different mutually exclusive sets of the plurality of received synchronous write requests until the write threshold, that is dynamically determined by asynchronous storage system 210 for a targeted storage device 220, is satisfied. In grouping the data from different sets of write requests, asynchronous storage system 210 may reorder and combine execution of the synchronous write requests into fewer write operations. For instance, asynchronous storage system 210 may coalesce and/or batch together data from non-consecutive synchronous write requests issued by a particular client device 110 and/or the data from non-consecutive synchronous write requests that contain different data for the same file.; the examiner notes that the payload is merely the data from the requests).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Venkataraman and Gray to combine write request into fewer operations. Gray improves the write performance (col. 3 lines 60-64).
The combined teachings of Venkataraman and Gray discloses batching multiple requests but do not specifically disclose: the first request including a payload and a batch request, the batch request being a single command comprising a request to perform one or more operations on one or more data sets.
However, Lindemann discloses: the first request including a payload and a batch request, the batch request being a single command comprising a request to perform one or more operations on one or more data sets (¶0009).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Venkataraman, Gray and Lindemann to combine write request into fewer operations. Lindemann improves operation throughput. (¶0012).
Per claim 2, Venkataraman discloses: wherein: the first allocated function data memory region is for read operations; and the first memory access request is a read access request (¶0073; a first application 802 is associated with an owner read write privilege for a first address space 806. Thus, the controller 106 may grant read and write requests directed to the first address space 806 from the first application 802).
Per claim 3, Venkataraman discloses: wherein the first request further defines a second allocated function data memory region, for the first compute function, for write operations (¶0073; a first application 802 is associated with an owner read write privilege for a first address space 806. Thus, the controller 106 may grant read and write requests directed to the first address space 806 from the first application 802.).
Per claim 4, Venkataraman discloses: wherein the controller circuit is configured: to receive a second memory access request, from the first compute function, for a second memory location in the common memory area and outside the first allocated function data memory region; and to approve the second memory access request (¶0073; A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804).
Per claim 5, Venkataraman discloses: wherein: the second memory access request is a write access request, and the second memory location is within the second allocated function data memory region (¶0073; A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804).
Per claim 6, Venkataraman discloses: wherein: the first request further defines a third allocated function data memory region, for the second compute function, for read operations; and the third allocated function data memory region overlaps the second allocated function data memory region in an overlapping portion of the third allocated function data memory region (¶0073; A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804).
Per claim 7, Venkataraman discloses: wherein the controller circuit is further configured: to receive a third memory access request, from the first compute function, for a third memory location in the overlapping portion of the third allocated function data memory region; and to approve the third memory access request, wherein the third memory access request is a write access request (¶0073; A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804; the examiner notes that the overlap is a function of the compute function in this case the group privilege).
Per claim 8, Venkataraman discloses: wherein the controller circuit is further configured: to receive a fourth memory access request, from the second compute function, for a fourth memory location in the overlapping portion of the third allocated function data memory region; and to approve the fourth memory access request, wherein the fourth memory access request is a read access request (¶0073; A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804; the examiner notes that the overlap is a function of the compute function in this case the group privilege).
Per claim 9, Venkataraman discloses: wherein the controller circuit is further configured: to receive a fifth memory access request, from the second compute function, for a fifth memory location in the overlapping portion of the third allocated function data memory region; and to deny the fifth memory access request, wherein the fifth memory access request is a write access request (¶0073; A second application 804 is associated with a group read privilege for the first address space 806. Accordingly, the controller 106 may grant read requests directed to the first address space 806 from the second application 804. The second application 804 is further associated with an owner read write privilege for a second address space 808. Thus, the controller 106 may grant read and write requests directed to the second address space 808 from the second application 804; ¶0074; the controller 106 may deny a write request from the second application 804 directed to the first address space 806 in response to determining that the second application 804 is granted read access but not write access to the first address space 806. Similarly, the controller 106 may deny requests to access the second address space 808 from the first application 802.).
Per claim 10, Venkataraman discloses: wherein the controller circuit is configured to maintain a table of access permissions, the table including read and write access permissions for the first compute function (fig. 10, ¶0079; a table 1000 showing examples of privileges (e.g., the first application privileges 304) associated with an application is shown).
Per claim 11, Venkataraman discloses: wherein the controller circuit is further configured to receive an identifying tag from the host, and to acknowledge receipt of the identifying tag (fig. 5A, ¶0055; FIG. 5A, the host 102 sends a command 502 to grant a first application 506 access to the first data 126 on the storage medium 124. The command 502 may correspond to the command 302. The command 502 may include an identifier of a namespace, a location (e.g., LBA, LBA range, etc.), a page, a key, some other identifier associated with the first data 126, or a combination thereof. In addition, the command may include an access type identifier (e.g., read access, write access, or execute access).
Claims 14-19 are the device claims corresponding to the method claim 1-11 and are rejected under the same reasons set forth in connection with the rejection of claims 1-11.
Claim 20 is the device claim corresponding to the device claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Venkataraman et al. 20220308770 herein Venkataraman, Gray et al 10802762 herein Gray and Lindemann in view of Arzola et al. 10740035 herein Arzola.
Per claim 12, Venkataraman, Gray and Lindemann do not specifically disclose: wherein the controller circuit is further configured: to compare a subset of a plurality of bits of a logical block address of the first request to the identifying tag; and to determine that the subset of the plurality of bits matches the identifying tag.
However, Arzola discloses: wherein the controller circuit is further configured: to compare a subset of a plurality of bits of a logical block address of the first request to the identifying tag; and to determine that the subset of the plurality of bits matches the identifying tag (col. 2 lines 15-20; determining, by the device driver or the particular device, that i) the cached unique identifier matches a current unique identifier for the particular device and ii) the cached firmware version matches a current firmware version for the particular device; and in response to the matching, completing the management command at the particular device).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Venkataraman, Gray, Lindemann and Arzola to authenticate a device driver. Arzola authentication prevent incorrect erasure of data (col 9 lines 22-32).
Per claim 13, Arzola discloses: wherein the controller circuit is further configured: to receive a second request from the host; to compare a subset of a plurality of bits of a logical block address of the second request to the identifying tag; to determine that the subset of the plurality of bits does not match the identifying tag; and to return an error code to the host (col. 2 lines 30-35; determining, by the device driver or the particular device, that the cached unique identifier does not match the current unique identifier for the particular device; and in response to determining that the cached unique identifier does not match the current unique identifier for the particular device, rejecting the management command at the particular device. Determining, by the device driver or the particular device, that the cached firmware version does not match the current firmware version for the particular device; and in response to determining that the cached firmware version does not match the current firmware version for the particular device, rejecting the management command at the particular device).
Response to Arguments
Applicant’s amendment and arguments, filed 2/05/26, with respect to the rejection(s) of claim(s) 1, 14 and 20 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lindemann.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wells 20170346875 discloses: API service 132 can receive a write request as part of a batch of write requests and decompose each request in the batch into a plurality of subqueries. Write optimizer 624 can analyze the subqueries generated for each write request to identify a subquery shared by each request in the batch and executed on the same cloud location 140. For an identified subquery, write optimizer 624 can coalesce the subqueries from each request in the batch into a single subquery to write data for each request in the batch in a single operation executed on a cloud location 140.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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