DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-18 are pending in this application.
Information Disclosure Statement
The IDS filed on 01/23/2023 has been considered.
Drawings
The drawings are objected to as failing to comply with 37 C.F.R. 1.84(q) as recited here: “Lead lines are those lines between the reference characters and the details referred to. Such lines may be straight or curved and should be as short as possible. They must originate in the immediate proximity of the reference character and extend to the feature indicated. Lead lines must not cross each other. Lead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed. Such a reference character must be underlined to make it clear that a lead line has not been left out by mistake. Lead lines must be executed in the same way as lines in the drawing. See paragraph (l) of this section.” Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a weight-sparse data generation unit”, “a weight data compression unit”, “an instruction scheduler,” “sparsity parallel processing architecture,” “an accumulator,” and “workload distributor” in claims 1-18.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The structure corresponding to “a weight-sparse data generation unit”, “a weight data compression unit”, “an instruction scheduler,” “sparsity parallel processing architecture,” “an accumulator,” and “workload distributor” is not provided in the specification.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
MPEP 2163 recites “To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention”, “possession may be shown by describing an actual reduction to practice of the claimed invention”, “A specification may describe an actual reduction to practice by showing that the inventor constructed an embodiment or performed a process that met all the limitations of the claim and determined that the invention would work for its intended purpose”. However, the claims fail to meet the written description requirement because the claims fail to work in a way that satisfy their intended purpose and therefore show lack of possession. There is a requirement “that the description be set forth "in such full, clear, concise, and exact terms" to show possession of the claimed invention” (MPEP 2163), but the specification fails to meet such a requirement. MPEP 2163 recites "[T]he ‘essential goal’ of the description of the invention requirement is to clearly convey the information that an applicant [inventor] has invented the subject matter which is claimed”. Claims 3, 4, 5, 6, and 7 recite unclear limitations and their language is copied directly from the specification. Therefore, claims 3, 4, 5, 6, and 7 are rejected for failing to meet the written description requirement.
Claims 8 and 9 are dependent claims of claim 7 and fail to resolve the deficiencies of claim 7, so they are rejected for the same reasons.
Claim limitations “a weight-sparse data generation unit”, “a weight data compression unit”, “an instruction scheduler,” “sparsity parallel processing architecture,” “an accumulator,” and “workload distributor” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification must disclose an computer with an appropriate algorithms to provide the structure for computer implemented 35 USC 112f limitations. However, that is not provided in the specification. Therefore, claims 1-18 are not supported and are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1 and 10 (line numbers refer to claim 1):
Line 3 recites “multi-agent reinforcement learning deep neural network learning” and it is unclear if this refers to “multi-agent reinforcement learning” in line 1 or not.
Line 6 recites “actual workload” but it is unclear what this means (What is the difference between an actual workload versus a workload that is not an actual workload?).
Lines 13-14 recite “neural network learning” and it is unclear if this refers to “multi-agent reinforcement learning deep neural network learning”.
Line 18 recites “the layer” which lacks antecedent basis.
Line 18 recites “neural network learning” but it is unclear if this refers to ‘neural network learning” in lines 13-14.
Lines 19-20 recite “add results of pieces of the sparsity parallel processing architecture” but it is unclear what the pieces of the sparsity parallel processing architecture are.
Lines 22 and 23 recite “next layer” but it is unclear what it is subsequent to.
As per claims 3 and 12 (line numbers refer to claim 3):
Lines 2-4 recite “generates each input channel weight group matrix and each output channel weight group matrix with respect to a layer a sparsity of which is to be generated for weight grouping” but it is unclear what this means.
Lines 5-7 recite “finds maximum indices in data in the number of groups included in a column of the generated input channel weight group matrices and a row of the generated output channel weight group matrices” but it is unclear what this means.
Lines 8-10 recite “stores and then compares maximum value indices of a column the generated input channel weight group matrices and a row of the generated output channel weight group matrices” but it is unclear what is being compared.
As per claims 4 and 13 (line numbers refer to claim 4):
Lines 2-3 recite “the maximum value indices of the input channel weight group matrix an the output channel weight group matrix” and it is unclear what the antecedent basis for this limitation is since claim 3 recites “maximum value indices of a column the generated input channel weight group matrices and a row of the generated output channel weight group matrices”.
Lines 4-7 recite “generates an element of the sparsity vector as 1 when the maximum value indices are identical with each other, generates an element of the sparsity vector as 0 when the maximum value indices are not identical with each other” and it is unclear which element of the sparsity vector is 1 and which element of the sparsity vector is 0 since a vector can have many indices. Additionally, it is unclear if “the maximum value indices” refers to “maximum value indices of a column the generated input channel weight group matrices and a row of the generated output channel weight group matrices”.
Lines 8-9 recite “stores a location at which the maximum value indices are identical with each other and the number of maximum value indices” but it is unclear what this means.
As per claims 5 and 14 (line numbers refer to claim 5):
Line 3 recites “the maximum value index” but it is unclear what this refers to.
Line 3 recites “the rest” but it is unclear what this refers to.
Lines 6-7 recite “the layer the sparsity” but it is unclear what this means.
Lines 9 and 11 recite “corresponding weight” but it is unclear what this refers to.
Lines 9 and 11 recite “the value” but it is unclear what this refers to.
Lines 9-10 and 11-12 recite “the value of the weight mask matrix” but it is unclear what this means since a matrix has multiple columns and rows.
As per claims 6 and 15 (line numbers refer to claim 6):
Line 2 recites “a workload” and it is unclear if this refers to “a workload” in claim 1.
Lines 2-5 recite “schedules a workload by predicting that workloads are to constantly converge if cores having the same number of weight group matrix columns with respect to the input channel weight group matrix and the output channel weight group matrix generated by the weight-sparse data generation unit” but it is unclear what this means.
Line 6 recites “compresses an input and weight” but claim 1 already recites “compress values of the weights”. It is unclear if “compresses…weight” refers back to claim 1.
Line 7 recites “predicting the workload” and it is unclear if this refers to “predicting that workloads” in claim 6 or “predicting a workload” in claim 1.
Line 8 recites “the compressed…weight” and it is unclear if this refers back to line 6 of claim 6 or claim 1.
As per claims 7 and 16 (line numbers refer to claim 7):
Line 5 recites “a workload” and it unclear if this refers to “a workload” in claim 1.
Line 6 recites “an actual workload” and it is unclear if this refers to “an actual workload” in claim 1. Additionally, it is unclear what the difference between an actual workload and workload is.
Lines 5-7 recite “distributes a workload by minimizing a fixed connection between VPUs through the VPU because an actual workload is different for each column of the weight mask matrix” but it is unclear what it means to minimize a fixed connection between VPUs through the VPU. Also it is unclear what “the VPU” refers to. Additionally, the metes and bounds of this limitation is unclear due to the word “because”.
As per claims 8 and 17 (line numbers refer to claim 8):
Line 1 recites “the VPU” but it is unclear what this refers to.
Line 3 recites “an input” but it is unclear if this refers to “an input” in claim 1.
Line 3 recites “a corresponding weight” but it is unclear what this refers to.
Line 3 recites “an input” and “input data” but it is unclear what the difference is.
Line 4 recites “each weight” but it is unclear if each weight is one of the weights necessary for multi-agent reinforcement learning deep neural network learning recited in claim 1.
As per claims 9 and 18 (line numbers refer to claim 9):
Line 2 recites “an input” but it is unclear if this refers to “an input” in claim 1.
Line 2 recites “a corresponding weight” but it is unclear what this refers to.
Line 2 recites “the VPU” but it is unclear what this refers to.
Lines 5-6 recite “a plurality of weight mask matrices” and it is unclear if this refers to “a plurality of weight mask matrices” in claim 8.
Line 7 recites “an operation on a layer” and it is unclear if this refers to “an operation of one layer” in claim 1.
Claims 2-9 and 11-18 are dependent claims of claims 1 and 10, and fail to resolve the deficiencies of claims 1 and 10, so they are rejected for the same reasons.
Claim limitations “a weight-sparse data generation unit”, “a weight data compression unit”, “an instruction scheduler,” “sparsity parallel processing architecture,” “an accumulator,” and “workload distributor” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification must disclose an computer with an appropriate algorithms to provide the structure for computer implemented 35 USC 112f limitations. However, that is not provided in the specification. Therefore, claims 1-18 are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
As per claim 1, in step 1 of the 101 analysis, the examiner has determined that the claim
is directed to a system. Therefore, the claim is directed to one of the four statutory categories of
invention.
The limitation “for accelerating multi-agent reinforcement learning” has no patentable weight.
In step 2A prong 1 of the 101 analysis, the examiner has determined that the claim recites
a judicial exception. Specifically, the limitations of “configured to generate sparse data comprising a sparsity vector, a weight-sparse index, and an actual workload by using a weight grouping method when an epoch is started”, “configured to add results of pieces of the sparsity parallel processing architecture when an operation of one layer of the sparsity parallel processing architecture is finished”, and “by predicting a workload of the next layer” are mental processes. Generating sparse data is a mental process since humans can mentally come up with a sparsity vector, a weight-sparse index, and an actual workload. Adding results is a mental process since humans can make mental computations. Predicting a workload of the next layer is a mental process since humans can analyze information to make a prediction.
In step 2A prong 2 of the 101 analysis, the examiner has determined that the additional
elements, alone or in combination do not integrate the judicial exceptions into a practical
application for the following rationale:
The limitations "configured to initialize and store weights necessary for multi-agent reinforcement learning deep neural network learning and receive learning samples from a PCIe interface", “to store the generated sparse data in a row direction weight sparsity data memory”, “configured to fetch the weights from the weight memory, compress values of the weights based on a form of the generated sparse data, and transmit only the actual workload and the weight-sparse index to sparsity parallel processing architecture”, “configured to receive only the actual workload and the weight-sparse index”, and “configured to distribute an input of a next layer to each core” represent insignificant, extra-solution activities. The term "extra-solution activity" can be understood as "activities incidental to the primary process or product that are merely a nominal or tangential addition to the claim" (MPEP 2106.05(g)). The examiner has determined that the limitations "configured to initialize and store weights necessary for multi-agent reinforcement learning deep neural network learning and receive learning samples from a PCIe interface", “to store the generated sparse data in a row direction weight sparsity data memory”, “configured to fetch the weights from the weight memory, compress values of the weights based on a form of the generated sparse data, and transmit only the actual workload and the weight-sparse index to sparsity parallel processing architecture”, “configured to receive only the actual workload and the weight-sparse index”, and “configured to distribute an input of a next layer to each core” are directed to mere data gathering activities which is a category of insignificant extra-solution activities (MPEP 2106.05(g)).
The limitations "weight memory", "a weight-sparse data generation unit", “a weight data compression unit”, “an instruction scheduler”, “sparsity parallel processing architecture”, “an accumulator”, and “a workload distributor” apply judicial exceptions on a generic computer. "Alappat 's rationale that an otherwise ineligible algorithm or software could be made patent-eligible by merely adding a generic computer to the claim was superseded by the Supreme Court's Bilski and Alice Corp. decisions" so therefore applying judicial exceptions on "weight memory", "a weight-sparse data generation unit", “a weight data compression unit”, “an instruction scheduler”, “sparsity parallel processing architecture”, “an accumulator”, and “a workload distributor” which are generic computers does not integrate the judicial exceptions into a practical application (MPEP 2106.05(b)).
The limitations “configured to control an entire process of neural network learning comprising weight grouping, forward propagation, backward propagation, and weight update operations” and “perform parallel processing within the layer in the entire process of neural network learning” recite mere instructions to apply a judicial exception. This limitation recites a result- oriented outcome without the necessary details about the steps taken to control the entire process of neural network learning and perform parallel processing (see MPEP 2106.05(f) "The court thus held the claims ineligible, because the additional limitations provided only a result-oriented solution and lacked details as to how the computer performed the modifications, which was equivalent to the words "apply it""). Thus, these limitations do not integrate a judicial exception into a practical application.
In step 2B of the 101 analysis, the examiner has determined that the additional elements, alone or in combination do not recite significantly more than the abstract ideas identified above for the following rationale:
The limitations "configured to initialize and store weights necessary for multi-agent reinforcement learning deep neural network learning and receive learning samples from a PCIe interface", “to store the generated sparse data in a row direction weight sparsity data memory”, “configured to fetch the weights from the weight memory, compress values of the weights based on a form of the generated sparse data, and transmit only the actual workload and the weight-sparse index to sparsity parallel processing architecture”, “configured to receive only the actual workload and the weight-sparse index”, and “configured to distribute an input of a next layer to each core” represent insignificant, extra-solution activities. The limitations "configured to initialize and store weights necessary for multi-agent reinforcement learning deep neural network learning and receive learning samples from a PCIe interface", “to store the generated sparse data in a row direction weight sparsity data memory”, “configured to fetch the weights from the weight memory, compress values of the weights based on a form of the generated sparse data, and transmit only the actual workload and the weight-sparse index to sparsity parallel processing architecture”, “configured to receive only the actual workload and the weight-sparse index”, and “configured to distribute an input of a next layer to each core” are well-understood, routine, or conventional because they are directed to "receiving or transmitting data" or “storing and retrieving information in memory” (MPEP 2106.05(d)). These are additional elements that the courts have recognized as well understood, routine, or conventional (MPEP 2106.05(d)). The citation of court cases in the MPEP meets the Berkheimer evidentiary burden since citation of a court case in the MPEP is one of the 4 types of evidentiary support that can be used to prove that the additional elements are well-understood, routine, or conventional (see 125 USPQ2d 1649 Berkheimer v. HP, Inc.). Thus, the limitations do not amount to significantly more than the abstract idea.
The limitations "weight memory", "a weight-sparse data generation unit", “a weight data compression unit”, “an instruction scheduler”, “sparsity parallel processing architecture”, “an accumulator”, and “a workload distributor” apply judicial exceptions on a generic computer and therefore do not provide significantly more.
The limitations “configured to control an entire process of neural network learning comprising weight grouping, forward propagation, backward propagation, and weight update operations” and “perform parallel processing within the layer in the entire process of neural network learning” mere instructions to apply a judicial exception which do not recite significantly more.
As per claim 10, it is a method claim of claim 1, so it is rejected for similar reasons.
As per claim 2 (and similarly for claim 11), it recites generic computing components, mental processes, and insignificant extra solution activities that are well understood, routine, or conventional because they are directed to "receiving or transmitting data" (MPEP 2106.05(d)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 3 (and similarly for claim 12), it recites generic computing components, mental processes, and insignificant extra solution activities that are well understood, routine, or conventional because they are directed to “storing and retrieving information in memory” (MPEP 2106.05(d)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 4 (and similarly for claim 13), it recites generic computing components, mental processes, and insignificant extra solution activities that are well understood, routine, or conventional because they are directed to “storing and retrieving information in memory” (MPEP 2106.05(d)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 5 (and similarly for claim 14), it recites generic computing components, mental processes, and mere instructions to apply a judicial exception. Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 6 (and similarly for claim 15), it recites generic computing components, mental processes, and insignificant extra solution activities that are well understood, routine, or conventional because they are directed to "receiving or transmitting data" (MPEP 2106.05(d)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 7 (and similarly for claim 16), it recites additional generic computing components and insignificant extra solution activities that are well understood, routine, or conventional because they are directed to "receiving or transmitting data" (MPEP 2106.05(d)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 8 (and similarly for claim 17), it recites generic computing components, mental processes, mere instructions to apply a judicial exception, and insignificant extra solution activities that are well understood, routine, or conventional because they are directed to "receiving or transmitting data" (MPEP 2106.05(d)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
As per claim 9 (and similarly for claim 18) it recites generic computing components, mental processes, and mere instructions to apply a judicial exception. Therefore, the additional elements do not integrate the judicial exceptions into a practical application nor recite significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20180046895 A1 hereinafter Xie), in view of Van Seijen et al. (US 20180165603 A1 hereinafter Van Seijen), in view of Buddhikot et al. (US 20240302488 A1 hereinafter Buddhikot), in view of Forero et al. (US 20230319163 A1 hereinafter Forero), and further in view of Bernat et al. (US 20210397999 A1 hereinafter Bernat).
As per claim 1, Xie teaches a system for accelerating learning, comprising: weight memory configured to initialize and store weights necessary for deep neural network learning and receive learning samples (Fig. 4; [0039] Accelerating Equation (5) is needed to accelerate compressed DNN; [0073] FIG. 4 shows memory layout for the relative indexed, indirect weighted and interleaved CCS format; [0094] A plurality of pointer reading units (Ptrread) are provided to read pointer information (or, address information) of a stored weight matrix W; [0048] EIE: Efficient Inference Engine on Compressed Deep Neural Network; [0007] Also, in recent years, the scale of ANNs is exploding. Large DNN models are very powerful but consume large amounts of energy because the model must be stored in external DRAM, and fetched every time for each image, word, or speech sample.);
a weight-sparse data generation unit configured to generate sparse data comprising a sparsity vector, a weight-sparse index, and an actual workload by using a weight grouping method and to store the generated sparse data in a row direction weight sparsity data memory ([0108] According to one embodiment of the present application, the proposed chip for ANN further comprises a leading zero detecting unit (not shown in FIG. 6) used for detecting non-zero values in input vectors; [0095] A plurality of sparse matrix reading units (SpmatRead) are provided to read non-zero values of a sparse matrix W of said neural network, said matrix W represents weights of a layer of said neural network; [0087] In EIE solution, only input vectors (to be more specific, non-zero values in input vectors) are broadcasted to PEs to achieve parallel computing; [0091] Input activation queue (Act) is provided for receiving a plurality of input activation, such as a plurality of input vectors a0, a1, . . . ; [0074] The relative row index: it indicates the number of zero-value weights between the present non-zero weight and the previous non-zero weight. [0075] The column pointer: the value by the present column pointer reducing the previous column pointer indicates the number of non-zero weights in this column. [0076] Thus, by referring to the index and pointer of FIG. 4, the non-zero weights can be accessed in the following manner: First, reading two consecutive column pointers and obtain the reduction value, said reduction value is the number of non-zero weights in this column. Next, by referring to the row index, the row address of said non-zero weights can be obtained. In this way, both the row address and column address of a non-zero weight can be obtained; [0043] For each column Wj of matrix W, it stores a vector v that contains the non-zero weights, and a second, equal-length vector z that encodes the number of zeros before the corresponding entry in v. Each entry of v and z is represented by a four-bit value. If more than 15 zeros appear before a non-zero entry we add a zero in vector v. For example, it encodes the following column [0044] [0,0,1,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3]. [0045] As v=[1,2,0,3], z=[2,0,15,2]. v and z of all columns are stored in one large pair of arrays with a pointer vector p pointing to the beginning of the vector for each column; [0041] For a sparse matrix, it is desired to compress the matrix in order to reduce the memory requirements. It has been proposed to store sparse matrix by Compressed Row Storage (CRS));
a weight data compression unit configured to fetch the weights from the weight memory, compress values of the weights based on a form of the generated sparse data, and transmit only the actual workload and the weight-sparse index to sparsity parallel processing architecture ([0094] A plurality of pointer reading units (Ptrread) are provided to read pointer information (or, address information) of a stored weight matrix W; [0010] Since memory access is the bottleneck in large layers, compressing the neural network comes as a solution. Model compression might change a large ANN model into a sparse ANN model, which reduces both calculations and memory complexity; [0039] Accelerating Equation (5) is needed to accelerate compressed DNN. By performing the indexing S[I.sub.ij] and the multiply add only for those columns for which both W.sub.ij and a.sub.j are non-zero, both the sparsity of the matrix and the vector are exploited; [0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j; [0087] In EIE solution, only input vectors (to be more specific, non-zero values in input vectors) are broadcasted to PEs to achieve parallel computing; [0075] The column pointer: the value by the present column pointer reducing the previous column pointer indicates the number of non-zero weights in this column. [0076] Thus, by referring to the index and pointer of FIG. 4, the non-zero weights can be accessed in the following manner: First, reading two consecutive column pointers and obtain the reduction value, said reduction value is the number of non-zero weights in this column. Next, by referring to the row index, the row address of said non-zero weights can be obtained. In this way, both the row address and column address of a non-zero weight can be obtained; [0111] With the solution shown in FIGS. 6 and 7, it broadcasts both the input vectors and the matrix W, which exploit both the sparsity of input vectors and the sparsity of matrix W. It significantly reduce the memory access operations, and also reduces the number of on-chip buffers; [0066] With N PEs, PE.sub.k holds all rows W.sub.i, output activations bi, and input activations a.sub.i for which i (mod N)=k. The portion of column W.sub.j in PE.sub.k is stored in the CCS format described in Section 3.2 but with the zero counts referring only to zeros in the subset of the column in this PE. Each PE has its own v, x, and p arrays that encode its fraction of the sparse matrix.);
an instruction scheduler configured to control an entire process of neural network learning comprising weight grouping, forward propagation ([0100] The control unit also schedules the plurality of sparse matrix reading units to input a fraction W.sub.p of said matrix W to the j.sup.th PE of each group of PE; [0022] FIG. 2 shows an Efficient Inference Engine (EIE) used for a compressed deep neural network (DNN) in machine learning; [0059] Activation Read/Write. The Activation Read/Write Unit contains two activation register files that accommodate the source and destination activation values respectively during a single round of FC layer computation. The source and destination register files exchange their role for next layer. Thus no additional data transfer is needed to support multilayer feed-forward computation; [0013] control unit being configured to input a number of M input vectors a.sub.i to said M groups of PE, and input a fraction W.sub.p of said matrix W to the j.sup.th PE of each group of PE; [0100] The control unit also schedules the plurality of sparse matrix reading units to input a fraction W.sub.p of said matrix W to the j.sup.th PE of each group of PE);
sparsity parallel processing architecture configured to receive only the actual workload and the weight-sparse index and perform parallel processing within the layer in the entire process of neural network learning ([0095] A plurality of sparse matrix reading units (SpmatRead) are provided to read non-zero values of a sparse matrix W of said neural network, said matrix W represents weights of a layer of said neural network; [0087] In EIE solution, only input vectors (to be more specific, non-zero values in input vectors) are broadcasted to PEs to achieve parallel computing; [0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j; [0076] Thus, by referring to the index and pointer of FIG. 4, the non-zero weights can be accessed in the following manner: First, reading two consecutive column pointers and obtain the reduction value, said reduction value is the number of non-zero weights in this column. Next, by referring to the row index, the row address of said non-zero weights can be obtained. In this way, both the row address and column address of a non-zero weight can be obtained);
an accumulator configured to add results of pieces of the sparsity parallel processing architecture when an operation of one layer of the sparsity parallel processing architecture is finished ([0013] each of said PE perform calculations on the received input vector and the received fraction W.sub.p of the matrix W, and an outputting unit for outputting the sum of said calculation results to output a plurality of output vectors b.sub.0, b.sub.1, . . .; [0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j—accumulating the partial sums in accumulators for each element of the output activation vector b. In the CCS representation these non-zeros weights are stored contiguously so each PE simply walks through its v array from location p.sub.j to p.sub.j+1−1 to load the weights. To address the output accumulators, the row number i corresponding to each weight W.sub.ij is generated by keeping a running sum of the entries of the x array; [0104] Each of said PE perform calculations on the received input vector and the received fraction W.sub.p of the matrix W. [0105] Lastly, as shown in FIG. 6, an output buffer (ActBuf) is provided for outputting the sum of said calculation results; [0016] reading a sparse weight matrix W of said neural network, said matrix W represents weights of a layer of said neural network; [0088] In the present application, it broadcasts both input vectors and matrix W to groups of PEs, so as to achieve parallel computing); and
a workload distributor configured to distribute an input of a next layer to each core ([0145] In addition, it proposes a method of both distributed storage and distributed computation to parallelize a sparsified layer across multiple PEs; [0016] input vectors and matrix W to a plurality of processing elements PE.sub.xy)
Xie fails to teach a system for accelerating multi-agent reinforcement learning, comprising: store weights necessary for multi-agent reinforcement learning deep neural network learning and receive learning samples from a PCIe interface; a weight grouping method when an epoch is started; control an entire process of neural network learning comprising backward propagation, and weight update operations; and distribute an input of a next layer to each core by predicting a workload of the next layer.
However, Van Seijen teaches a system for accelerating multi-agent reinforcement learning, comprising: store weights necessary for multi-agent reinforcement learning deep neural network learning ([0150] In a multi-advisory model, a single-agent reinforcement learning task can be partitioned into a multi-agent problem (e.g., using a divide and conquer paradigm); [0332] The system memory 2404 may include one or more agents 2406 and training data 2407. The training data 2407 may include data used to train the agents 2406; claim 1 each of the sub-reward functions having an associated weight, wherein each sub-reward function depends on a subset of the state variables; and training a plurality of reinforcement-learning agents using the plurality of sub-reward functions; [0117] there is a framework of communicating agents based on deep neural networks to solve various complex tasks; [0260] By measuring error at the heads 2426 (e.g., rather than at the output 2428 as in the DQN network 2410), faster learning can occur.); control an entire process of neural network learning comprising backward propagation, and weight update operations ([0259] The DQN neural network 2410 can include an input layer 2412, one or more hidden layers 2414, and an output layer 2416 used to produce an output 2418. Backpropagation can be used to train the neural network 2410 based on error measured at the output 2418; [0262] For example, the weights of the network 2430 can be updated via backpropagation based on the error of the general value function).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie with the teachings of Van Seijen for improved machine learning performance and the ability to solve complex tasks (see Van Seijen [0071] Disclosed embodiments include agent configurations that decompose tasks in different ways. These agent configurations can reduce an overall state space and allow for improved machine learning performance by increasing a convergence speed, reducing the amount of processing and memory resources consumed, among other improvements to computer technology; [0117] In another technique, there is a framework of communicating agents based on deep neural networks to solve various complex tasks.).
Xie and Van Seijen fail to teach receive learning samples from a PCIe interface; a weight grouping method when an epoch is started; and distribute an input of a next layer to each core by predicting a workload of the next layer.
However, Buddhikot teaches receive learning samples from a PCIe interface ([0091] The on-board FPGA 364 transfers the captured (I, Q) samples over a high speed PCIe interface 345 to the on-board memory 344 (8 GB); [0098] FIG. 8 is an example method 800 to implement a deep-learning-based environmental sensing capability sensor design for the 3.5 GHz CBRS band, based on the example embodiments described herein. At 802, the method includes generating at least one sample).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie and Van Seijen with the teachings of Buddhikot since PCIe interfaces provide high speed data transfer.
Xie, Van Seijen, and Buddhikot fail to teach a weight grouping method when an epoch is started; and distribute an input of a next layer to each core by predicting a workload of the next layer.
However, Forero teaches a weight grouping method when an epoch is started ([0032] 2) Action Space: At the beginning of each decision epoch the agent selects the weights Wn (τ):={wn∈RD: wn,d≥0, wn,d=0 if qd,n (τ)=0, Σd=1 Dwn,d=1} which is a simplex set that assigns a zero weight to an empty queue.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie, Van Seijen, and Buddhikot with the teachings of Forero since it offers numerous benefits (see Forero [0008] It is an object to provide a queue management method for in-transit data inspired by weighted-fair queueing that offers numerous benefits).
Xie, Van Seijen, Buddhikot, and Forero fail to teach distribute an input of a next layer to each core by predicting a workload of the next layer.
However, Bernat teaches distribute an input of a next layer to each core by predicting a workload of the next layer ([0047] In examples disclosed herein, depending on the current available bandwidth from a first node (e.g., node 640) to the next level of aggregation (e.g., the remote node 650), the current load on the first node, the first node estimates how many layers are to be executed at the first node, and how many layers are to be executed at a remote node to optimize the power consumed locally; [0042] In some examples, layers deep within the machine learning model involve more resource intensive tasks than layers earlier in the machine learning model. To that end, it may be more efficient to perform such resource intensive tasks at the remote node than at an edge node. Separating execution of the machine learning model in such a manner may additionally be advantageous as compared to causing execution of the entire machine learning model at the remote node, as an amount of data passed between intermediate (e.g., inner) layers of the machine learning model (e.g., between the third layer 515 and the fourth layer 520) may be smaller in comparison to the input data to an earlier layer in the machine learning model (e.g., an input to the first layer 505). For example, in an image classification scenario where an input image is analyzed to determine if a vehicle is present, an input image may be ten megabytes and data passed between intermediate layers of the machine learning model may be expected to be five megabytes. Executing a first portion of the machine learning model locally and then transmitting the intermediate data (e.g., five megabytes)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie, Van Seijen, Buddhikot, and Forero with the teachings of Bernat to promote efficiency (see Bernat [0042] In some examples, layers deep within the machine learning model involve more resource intensive tasks than layers earlier in the machine learning model. To that end, it may be more efficient to perform such resource intensive tasks at the remote node than at an edge node.).
As per claim 7, Xie, Van Seijen, Buddhikot, Forero, and Bernat teach the system of claim 1. Xie teaches wherein the sparsity parallel processing architecture receives only the actual workload and the weight-sparse index ([0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j; [0087] In EIE solution, only input vectors (to be more specific, non-zero values in input vectors) are broadcasted to PEs to achieve parallel computing; [0075] The column pointer: the value by the present column pointer reducing the previous column pointer indicates the number of non-zero weights in this column. [0076] Thus, by referring to the index and pointer of FIG. 4, the non-zero weights can be accessed in the following manner: First, reading two consecutive column pointers and obtain the reduction value, said reduction value is the number of non-zero weights in this column. Next, by referring to the row index, the row address of said non-zero weights can be obtained. In this way, both the row address and column address of a non-zero weight can be obtained;), distributes the actual workload and the weight-sparse index to different VPUs based on a weight mask matrix generated by the weight-sparse data generation unit ([0039] Accelerating Equation (5) is needed to accelerate compressed DNN. By performing the indexing S[I.sub.ij] and the multiply add only for those columns for which both W.sub.ij and a.sub.j are non-zero, both the sparsity of the matrix and the vector are exploited; [0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j), and distributes a workload by minimizing a fixed connection between VPUs through the VPU because an actual workload is different for each column of the weight mask matrix ([0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j; [0067] In FIG. 3, it shows an example multiplying an input activation vector a (of length 8) by a 16×8 weight matrix W yielding an output activation vector b (of length 16) on N=4 PEs. The elements of a, b, and W are color coded with their PE assignments. Each PE owns 4 rows of W, 2 elements of a, and 4 elements of b.).
As per claim 10, it is an operating method claim of claim 1, so it is rejected for similar reasons.
As per claim 16, it is an operating method claim of claim 7, so it is rejected for similar reasons.
Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie, Van Seijen, Buddhikot, Forero, and Bernat, as applied to claims 1 and 10 above, in view of Jeon et al. (US 20210224655 A1 hereinafter Jeon).
As per claim 2, Xie, Van Seijen, Buddhikot, Forero, and Bernat teach the system of claim 1. Xie teaches wherein the system generates the sparse data through the weight-sparse data generation unit ([0039] Accelerating Equation (5) is needed to accelerate compressed DNN. By performing the indexing S[I.sub.ij] and the multiply add only for those columns for which both W.sub.ij and a.sub.j are non-zero, both the sparsity of the matrix and the vector are exploited), compresses the values of the weights through the weight data compression unit based on a form of the generated sparse data and transmits only the actual workload and the weight-sparse index to the sparsity parallel processing architecture ([0080] With weight sharing, it is possible to store only a short (4-bit) index for each weight. Thus, in such a solution, the compressed DNN is indexed with a codebook to exploit its sparsity; [0039] Accelerating Equation (5) is needed to accelerate compressed DNN. By performing the indexing S[I.sub.ij] and the multiply add only for those columns for which both W.sub.ij and a.sub.j are non-zero, both the sparsity of the matrix and the vector are exploited; [0087] In EIE solution, only input vectors (to be more specific, non-zero values in input vectors) are broadcasted to PEs to achieve parallel computing; [0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j), adds the results of the pieces of sparsity parallel processing architecture through the accumulator under the control of the instruction scheduler ([0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j—accumulating the partial sums in accumulators for each element of the output activation vector b. In the CCS representation these non-zeros weights are stored contiguously so each PE simply walks through its v array from location p.sub.j to p.sub.j+1−1 to load the weights. To address the output accumulators, the row number i corresponding to each weight W.sub.ij is generated by keeping a running sum of the entries of the x array).
Additionally, Van Seijen teaches updates a weight according to the results of the operation ([0262] For example, the weights of the network 2430 can be updated via backpropagation based on the error of the general value function).
Additionally, Bernat teaches repeats an operation method of predicting a workload of a next layer through the workload distributor and distributes the workload to each core ([0047] In examples disclosed herein, depending on the current available bandwidth from a first node (e.g., node 640) to the next level of aggregation (e.g., the remote node 650), the current load on the first node, the first node estimates how many layers are to be executed at the first node, and how many layers are to be executed at a remote node to optimize the power consumed locally; [0042] In some examples, layers deep within the machine learning model involve more resource intensive tasks than layers earlier in the machine learning model. To that end, it may be more efficient to perform such resource intensive tasks at the remote node than at an edge node. Separating execution of the machine learning model in such a manner may additionally be advantageous as compared to causing execution of the entire machine learning model at the remote node, as an amount of data passed between intermediate (e.g., inner) layers of the machine learning model (e.g., between the third layer 515 and the fourth layer 520) may be smaller in comparison to the input data to an earlier layer in the machine learning model (e.g., an input to the first layer 505). For example, in an image classification scenario where an input image is analyzed to determine if a vehicle is present, an input image may be ten megabytes and data passed between intermediate layers of the machine learning model may be expected to be five megabytes. Executing a first portion of the machine learning model locally and then transmitting the intermediate data (e.g., five megabytes)).
Xie, Van Seijen, Buddhikot, Forero, and Bernat fail to teach wherein the system generates the sparse data through the weight-sparse data generation unit during one epoch.
However, Jeon teaches wherein the system generates the sparse data through the weight-sparse data generation unit during one epoch ([0065] The processor 510 counts the number of weight updates for each epoch and removes n weights—where n represents the number of weights that have to be removed to satisfy a desired sparsity—with a small number of updates after training of a network is completed.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie, Van Seijen, Buddhikot, Forero, and Bernat with the teachings of Jeon to increase computational speed (see Jeon [0008] To solve the problem above, an object of the present disclosure is to provide a method for pruning capable of increasing computational speed in an efficient manner while maintaining accuracy of a neural network model and at the same time).
As per claim 11, it is an operating method claim of claim 2, so it is rejected for similar reasons.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Xie, Van Seijen, Buddhikot, Forero, and Bernat, as applied to claims 1 and 10 above, in view of Tang et al. (US 20230068450 A1 hereinafter Tang).
As per claim 6, Xie, Van Seijen, Buddhikot, Forero, and Bernat teach the system of claim 1. Xie teaches compresses an input and weight of a layer based on the scheduled workload, and transfers the compressed input and weight to the sparsity parallel processing architecture ([0042] In the present application, in order to exploit the sparsity of activations, we store our encoded sparse weight matrix W in a variation of compressed column storage (CCS) format; [0039] Accelerating Equation (5) is needed to accelerate compressed DNN. By performing the indexing S[I.sub.ij] and the multiply add only for those columns for which both W.sub.ij and a.sub.j are non-zero, both the sparsity of the matrix and the vector are exploited; [0061] Distributed Leading Non-Zero Detection. Input activations are hierarchically distributed to each PE. To take advantage of the input vector sparsity, we use leading non-zero detection logic to select the first positive result; [0087] In EIE solution, only input vectors (to be more specific, non-zero values in input vectors) are broadcasted to PEs to achieve parallel computing; [0088] In the present application, it broadcasts both input vectors and matrix W to groups of PEs, so as to achieve parallel computing in two dimensions.).
Additionally, Van Seijen teaches wherein the workload distributor schedules a workload by predicting that workloads are to constantly converge ([0136] These results also show that separating a task into multiple related sub-tasks can result in considerable speed-ups in convergence compared to flat agents; [0166] The multi-advisor models fall within SoC. and SoC distributes the responsibilities among several agents that may communicate and have complex relationships, such as master-servant or collaborators-as-equal relationships. The following section transcribes under the multi-advisor reinforcement learning notations the main theoretical result: the stability theorem ensuring, under conditions, that the advisors' training eventually converges.).
Additionally, Bernat teaches compresses after predicting the workload ([0060] the serialization of the data may include compression of the data to reduce a bandwidth requirement for transmitting the data to a remote location for execution; [0020] This implies that further factors such as power availability, weather conditions, and workload prediction, need to be considered when making decisions related to where execution of a machine learning model should take place; [0047] In examples disclosed herein, depending on the current available bandwidth from a first node (e.g., node 640) to the next level of aggregation (e.g., the remote node 650), the current load on the first node, the first node estimates how many layers are to be executed at the first node, and how many layers are to be executed at a remote node to optimize the power consumed locally; [0042] In some examples, layers deep within the machine learning model involve more resource intensive tasks than layers earlier in the machine learning model. To that end, it may be more efficient to perform such resource intensive tasks at the remote node than at an edge node. Separating execution of the machine learning model in such a manner may additionally be advantageous as compared to causing execution of the entire machine learning model at the remote node, as an amount of data passed between intermediate (e.g., inner) layers of the machine learning model (e.g., between the third layer 515 and the fourth layer 520) may be smaller in comparison to the input data to an earlier layer in the machine learning model (e.g., an input to the first layer 505). For example, in an image classification scenario where an input image is analyzed to determine if a vehicle is present, an input image may be ten megabytes and data passed between intermediate layers of the machine learning model may be expected to be five megabytes. Executing a first portion of the machine learning model locally and then transmitting the intermediate data (e.g., five megabytes); [0083] In examples disclosed herein, it is typically more efficient to perform initial processing of the input data at the local node, as those initial layers of machine learning models typically result in a significant reduction on the amount of data that must be transmitted to enable continuation of the execution of the machine learning model. In this manner, the offload controller circuitry 740 selects a first portion of the machine learning model for local execution, and a second portion of the machine learning model for remote execution. Note that in some examples, the second portion of the machine learning model may then later be re-segmented by the remote node (or other node) for execution at subsequent remote nodes. [0084] Having selected a first portion of the model for local execution, the example model executor circuitry 730 executes the layers included in the first portion of the model. (Block 930). The example serialization circuitry 741 then serializes the output of the final locally executed layer. (Block 935).).
Xie, Van Seijen, Buddhikot, Forero, and Bernat fail to teach workloads are to constantly converge if cores having the same number of weight group matrix columns with respect to the input channel weight group matrix and the output channel weight group matrix generated by the weight-sparse data generation unit.
However, Tang teaches workloads are to constantly converge if cores having the same number of weight group matrix columns with respect to the input channel weight group matrix and the output channel weight group matrix generated by the weight-sparse data generation unit ([0021] However, the disclosure provides a hardware-friendly sparsity method by grouping and accelerated hardware design, to facilitate convergence of the algorithm accuracy and provide a high sparse rate in the same algorithm accuracy; [0026] In a specific example, as illustrated in FIG. 5, when the PE array includes 8×8 PE units (that is, P=8, Q=8), a 64×64 weight matrix (that is, M=64, N=64) may be divided into (64/8)×(64/8)=64 unit blocks, namely the unit block 1 to the unit block 64 (each unit block is represented by a number in each box of the figure); [0027] As illustrated in FIG. 5, 8×8 units are included in each unit block among the divided unit blocks 1 . . . 64 (corresponding to the divided areas 1, 2 . . . 64), so that the entire 64×64 weight matrix is divided into 8×8 matrices; [0035] when the total number of effective weights in each group of unit blocks is more than (P×Q)/2, splitting the group into two groups evenly in the column direction of the sparse weight matrix; [0049] for a weight matrix of fully-connected computation, M=fo, N=fi, where fo is a number of channels for output features, and fi is a number of channels for input features.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie, Van Seijen, Buddhikot, Forero, and Bernat with the teachings of Tang for better accuracy (see Tang [0021] However, the disclosure provides a hardware-friendly sparsity method by grouping and accelerated hardware design, to facilitate convergence of the algorithm accuracy and provide a high sparse rate in the same algorithm accuracy).
As per claim 15, it is an operating method claim of claim 6, so it is rejected for similar reasons.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie, Van Seijen, Buddhikot, Forero, and Bernat, as applied to claims 1 and 10 above, in view of Kim et al. (US 20230018893 A1 hereinafter Kim).
As per claim 8, Xie, Van Seijen, Buddhikot, Forero, and Bernat teach the system of claim 7. Xie teaches wherein in the sparsity parallel processing architecture, the VPU performs parallel processing on a column of a plurality of weight mask matrices ([0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j), and determines an input to be multiplied by a corresponding weight when input data is broadcasted by input memory ([0121] Input buffer 0 is used to store input vector X0; [0122] In addition, in order to compensate the different sparsity distributed to different PEs, it provides FIFO to store input vectors before sending these input vectors to PEs; [0067] In FIG. 3, it shows an example multiplying an input activation vector a (of length 8) by a 16×8 weight matrix W yielding an output activation vector b (of length 16) on N=4 PEs; [0068] It performs the sparse matrix x sparse vector operation by scanning vector a to find its next non-zero value a.sub.j and broadcasting a.sub.j along with its index j to all PEs. Each PE then multiplies a.sub.j by the non-zero elements in its portion of column W.sub.j).
Xie, Van Seijen, Buddhikot, Forero, and Bernat fail to teach each weight is unicasted by weight memory.
However, Kim teaches each weight is unicasted by weight memory ([0072] unicast the local weight (w.sub.k.sup.t) stored in the memory 120 to the central server 10.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Xie, Van Seijen, Buddhikot, Forero, and Bernat with the teachings of Kim since unicasting is reliable.
As per claim 17, it is an operating method claim of claim 8, so it is rejected for similar reasons.
Allowable Subject Matter
Claims 3-5, 9, 12-14, and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, and 35 U.S.C. 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/H.L./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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