DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 08/20/2025, in which claim 1 was amended, claims 13-14 were cancelled, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application JP2020165463 filed on 09/30/2020. The foreign application is not in English. The certified copy of the foreign priority application JP2020165463 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application JP2020165463 that is not in English, an English translation of the non-English language foreign application JP2020165463 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of “the first semiconductor device further includes a detector circuit configured to detect a characteristic parameter of the first power amplifier circuit, and wherein the second semiconductor device includes a characteristic adjustment circuit” of claim 9 ; “wherein the multilayer substrate includes a matching circuit built in the multilayer substrate” of claim 12 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531) in view of Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130) and Uchida (US Pub. 20020180058).
Regarding claim 1, Yasuda discloses in Fig. 6A, a radio-frequency module comprising:
a multilayer substrate [10] including a plurality of stacked layers [14 and 15], the multilayer substrate [10] having a first major face [face include face 24/dash line in annotated drawing] and a second major face [10b][paragraph [0053]];
a first semiconductor device [30][paragraph [0047]];
a second semiconductor device [40][paragraph [0047]];
a mount component [50] having a thickness greater than a thickness of the second semiconductor device [40], the mount component [50] being a component to be mounted [paragraph [0047]],
wherein the first major face includes a first recess [in region 12] and a second recess [in region 11][see annotated drawing],
wherein the mount component [50] is mounted onto a bottom face of the second recess [region 11][See annotated drawing],
wherein the first semiconductor device [30] is mounted over a bottom face of the first recess [region 12][See annotated drawing];
wherein the second semiconductor device [40] is mounted over the first major face so as to overlie the first recess [in region 12][See annotated drawing], and
wherein the first semiconductor device [30] is connected with a metallic via.
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Yasuda fails to disclose
wherein the second recess has a depth less than a depth of the first recess.
Lim discloses in Fig. 3A-3B
wherein the second recess [103] has a depth less than/equal to a depth of the first recess [104].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lim into the method of Yasuda to include wherein the second recess has a depth less than a depth of the first recess. The ordinary artisan would have been motivated to modify Yasuda in the above manner for the purpose of providing suitable depth of the second recess with respect to depth of the first recess to achieve slim and compact purposes [paragraph [0035] of Lim].
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a depth of the second recess with respect to a depth of the first recess: a depth of the second recess is greater than/less than/equal to a depth of the first recess. Absent unexpected results, it would have been obvious to try a depth of the second recess is greater than a depth of the first recess to yield a miniatured module.
Yasuda fails to disclose
an anisotropic conductive resin component,
wherein the anisotropic conductive resin component is disposed on the bottom face of the first recess,
wherein the anisotropic conductive resin component interposed between the first semiconductor device and the bottom face of the first recess.
Uchida discloses in Fig. 5, paragraph [0060]
an anisotropic conductive resin component [315];
wherein the anisotropic conductive resin component [315] is disposed on the bottom face of the first recess [322],
the anisotropic conductive resin component [315] interposed between the first semiconductor device [302] and the bottom face of the first recess [322].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Uchida into the method of Yasuda to include an anisotropic conductive resin component; wherein the anisotropic conductive resin component is disposed on the bottom face of the first recess, the anisotropic conductive resin component interposed between the first semiconductor device and the bottom face of the first recess. The ordinary artisan would have been motivated to modify Yasuda in the above manner for the purpose of providing suitable material filled within the cavity which enhancing electrically connecting the metal bumps of the first semiconductor chip to the metal terminals in the cavity while providing isolation in lateral direction [paragraph [0060] of Uchida]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Yasuda fails to disclose
the metallic via extending through a portion of the multilayer substrate from the bottom face of the first recess to the second major face.
Konishi et al. discloses in Fig. 10
the metallic via [11] extending through a portion of the multilayer substrate [2] from the bottom face of the first recess [10] to the second major face [paragraph [0043]-[0048]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Konishi et al. into the method of Yasuda to include the metallic via extending through a portion of the multilayer substrate from the bottom face of the first recess to the second major face. The ordinary artisan would have been motivated to modify Yasuda in the above manner for the purpose of electrically connecting the first semiconductor device with external conductive element; and/or providing the semiconductor module 1 (high frequency power amplifying device) having high heat radiation property [paragraph [0041], [0047], [0076] of Konishi et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US Pub. 20020180058) in view of Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557) and Konishi et al. (US Pub. 20060171130).
Regarding claim 1, Uchida discloses in Fig. 5, paragraph [0010], [0013], [0040], [0060] a radio-frequency module comprising:
a module substrate [301], the module substrate [301] having a first major face and a second major face [paragraph [0041]];
a first semiconductor device [302];
a second semiconductor device [304]; and
an anisotropic conductive resin component [315];
wherein the first major face includes a first recess [322],
wherein the anisotropic conductive resin component [315] is disposed on a bottom face of the first recess [322],
wherein the first semiconductor device [302] is mounted over the bottom face of the first recess [322] with the anisotropic conductive resin component [315] interposed between the first semiconductor device [302] and the bottom face of the first recess [322];
wherein the second semiconductor device [304] is mounted over the first major face so as to overlie the first recess [322].
Uchida fails to disclose
the module substrate is a multilayer substrate including a plurality of stacked layers;
wherein the first semiconductor device is connected with a metallic via, the metallic via extending through a portion of the multilayer substrate from the bottom face of the first recess to the second major face.
Konishi et al. discloses in Fig. 10
the module substrate [2] is a multilayer substrate including a plurality of stacked layers [paragraph [0041]];
wherein the first semiconductor device [25] is connected with a metallic via [11], the metallic via [11] extending through a portion of the multilayer substrate [2] from the bottom face of the first recess [10] to the second major face [paragraph [0043]-[0048]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Konishi et al. into the method of Uchida to include the substrate is a multilayer substrate including a plurality of stacked layers; wherein the first semiconductor device is connected with a metallic via, the metallic via extending through a portion of the multilayer substrate from the bottom face of the first recess to the second major face. The ordinary artisan would have been motivated to modify Uchida in the above manner for the purpose of providing suitable configuration of a module substrate; electrically connecting the first semiconductor device with external conductive element; and/or providing the semiconductor module 1 (high frequency power amplifying device) having high heat radiation property [paragraph [0041], [0047], [0076] of Konishi et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Konishi et al. and Uchida fails to disclose
a mount component having a thickness greater than a thickness of the second semiconductor device, the mount component being a component to be mounted,
wherein the first major face includes a second recess,
wherein the mount component is mounted onto a bottom face of the second recess.
Yasuda discloses in Fig. 6A
a mount component [50] having a thickness greater than a thickness of the second semiconductor device [40], the mount component [50] being a component to be mounted [paragraph [0047]],
wherein the first major face includes a first recess [in region 12] and a second recess [in region 11][see annotated drawing],
wherein the mount component [50] is mounted onto a bottom face of the second recess [region 11][See annotated drawing],
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yasuda into the method of Konishi et al. and Uchida to include a mount component having a thickness greater than a thickness of the second semiconductor device, the mount component being a component to be mounted, wherein the first major face includes a second recess, wherein the mount component is mounted onto a bottom face of the second recess. The ordinary artisan would have been motivated to modify Konishi et al. and Uchida in the above manner for the purpose of providing miniaturized high-frequency module including a chip inductor having the high quality factor Q [paragraph [0092], [0110] of Yasuda].
Konishi et al., Uchida and Yasuda fails to disclose
wherein the second recess has a depth less than a depth of the first recess.
Lim discloses in Fig. 3A-3B
wherein the second recess [103] has a depth less than/equal to a depth of the first recess [104].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lim into the method of Konishi et al., Uchida and Yasuda to include wherein the second recess has a depth less than a depth of the first recess. The ordinary artisan would have been motivated to modify Konishi et al., Uchida and Yasuda in the above manner for the purpose of providing suitable depth of the second recess with respect to depth of the first recess to achieve slim and compact purposes [paragraph [0035] of Lim].
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a depth of the second recess with respect to a depth of the first recess: a depth of the second recess is greater than/less than/equal to a depth of the first recess. Absent unexpected results, it would have been obvious to try a depth of the second recess is greater than a depth of the first recess to yield a miniatured module.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Konishi et al. (US Pub. 20060171130) in view of Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557) and Uchida (US Pub. 20020180058).
Regarding claim 1, Konishi et al. discloses in Fig. 10, a radio-frequency module comprising:
a multilayer substrate [2] including a plurality of stacked layers, the multilayer substrate [2] having a first major face and a second major face [paragraph [0041]];
a first semiconductor device [25];
a second semiconductor device [15]; and
wherein the first major face includes a first recess [10][paragraph [0080]],
wherein the first semiconductor device [25] is mounted over a bottom face of the first recess [10][paragraph [0080]];
wherein the second semiconductor device [15] is mounted over the first major face so as to overlie the first recess [10], and
wherein the first semiconductor device [25] is connected with a metallic via [11], the metallic via [11] extending through a portion of the multilayer substrate [2] from the bottom face of the first recess [10] to the second major face [paragraph [0076]].
Konishi et al. fails to disclose
an anisotropic conductive resin component,
wherein the anisotropic conductive resin component is disposed on the bottom face of the first recess,
wherein the anisotropic conductive resin component interposed between the first semiconductor device and the bottom face of the first recess.
Uchida discloses in Fig. 5, paragraph [0060]
an anisotropic conductive resin component [315];
wherein the anisotropic conductive resin component [315] is disposed on a bottom face of the first recess [322],
the anisotropic conductive resin component [315] interposed between the first semiconductor device [302] and the bottom face of the first recess [322].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Uchida into the method of Konishi et al. to include an anisotropic conductive resin component; wherein the anisotropic conductive resin component is disposed on a bottom face of the first recess, the anisotropic conductive resin component interposed between the first semiconductor device and the bottom face of the first recess. The ordinary artisan would have been motivated to modify Konishi et al. in the above manner for the purpose of providing suitable material filled within the cavity which enhancing electrically connecting the metal bumps of the first semiconductor chip to the metal terminals in the cavity while providing isolation in lateral direction [paragraph [0060] of Uchida]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Konishi et al. and Uchida fails to disclose
a mount component having a thickness greater than a thickness of the second semiconductor device, the mount component being a component to be mounted,
wherein the first major face includes a second recess,
wherein the mount component is mounted onto a bottom face of the second recess.
Yasuda discloses in Fig. 6A
a mount component [50] having a thickness greater than a thickness of the second semiconductor device [40], the mount component [50] being a component to be mounted [paragraph [0047]],
wherein the first major face includes a first recess [in region 12] and a second recess [in region 11][see annotated drawing],
wherein the mount component [50] is mounted onto a bottom face of the second recess [region 11][See annotated drawing],
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yasuda into the method of Konishi et al. and Uchida to include a mount component having a thickness greater than a thickness of the second semiconductor device, the mount component being a component to be mounted, wherein the first major face includes a second recess, wherein the mount component is mounted onto a bottom face of the second recess. The ordinary artisan would have been motivated to modify Konishi et al. and Uchida in the above manner for the purpose of providing miniaturized high-frequency module including a chip inductor having the high quality factor Q [paragraph [0092], [0110] of Yasuda].
Konishi et al., Uchida and Yasuda fails to disclose
wherein the second recess has a depth less than a depth of the first recess.
Lim discloses in Fig. 3A-3B
wherein the second recess [103] has a depth less than/equal to a depth of the first recess [104].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lim into the method of Konishi et al., Uchida and Yasuda to include wherein the second recess has a depth less than a depth of the first recess. The ordinary artisan would have been motivated to modify Konishi et al., Uchida and Yasuda in the above manner for the purpose of providing suitable depth of the second recess with respect to depth of the first recess to achieve slim and compact purposes [paragraph [0035] of Lim].
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a depth of the second recess with respect to a depth of the first recess: a depth of the second recess is greater than/less than/equal to a depth of the first recess. Absent unexpected results, it would have been obvious to try a depth of the second recess is greater than a depth of the first recess to yield a miniatured module.
Claims 1, 5-6, 11, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Konishi et al. (US Pub. 20040188834), hereafter Konishi834, in view of Higashitani et al. (US Pub. 20050017740), Yasuda (US Pub. 20190320531), and Lim (US Pub. 20200152557)
Regarding claim 1, Konishi834 discloses in Fig. 1, a radio-frequency module comprising:
a multilayer substrate [4] including a plurality of stacked layers, the multilayer substrate [4] having a first major face and a second major face [paragraph [0041]];
a first semiconductor device [7][paragraph [0042]];
a second semiconductor device [2][paragraph [0042]];
a conductive bonding component [11][paragraph [0044],
wherein the first major face includes a first recess [4a][paragraph [0044]],
wherein the conductive bonding component [11] is disposed on the bottom face of the first recess [4a],
wherein the conductive bonding component [11] interposed between the first semiconductor device [7] and the bottom face of the first recess [4a];
wherein the first semiconductor device [7] is mounted over a bottom face of the first recess [4a][paragraph [0044]];
wherein the second semiconductor device [2] is mounted over the first major face so as to overlie the first recess [4a] [paragraph [0046]], and
wherein the first semiconductor device [7] is connected with a metallic via [4h], the metallic via [4h] extending through a portion of the multilayer substrate [4] from the bottom face of the first recess [4a] to the second major face [paragraph [0041]].
Konishi834 fails to disclose
wherein the conductive bonding component comprises an anisotropic conductive resin component.
Higashitani et al. discloses in paragraph [0056]
wherein the conductive bonding component comprises an anisotropic conductive resin component.
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Higashitani et al. into the method of Konishi834 to include wherein the conductive bonding component comprises an anisotropic conductive resin component. The ordinary artisan would have been motivated to modify Konishi834 in the above manner for the purpose of providing suitable alternative conductive material to electrically bond the semiconductor device to the module board [paragraph [0044] of Konishi834, paragraph [0056] of Higashitani et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Higashitani et al. and Konishi834 fails to disclose
a mount component having a thickness greater than a thickness of the second semiconductor device, the mount component being a component to be mounted,
wherein the first major face includes a second recess,
wherein the mount component is mounted onto a bottom face of the second recess.
Yasuda discloses in Fig. 6A
a mount component [50] having a thickness greater than a thickness of the second semiconductor device [40], the mount component [50] being a component to be mounted [paragraph [0047]],
wherein the first major face includes a first recess [in region 12] and a second recess [in region 11][see annotated drawing],
wherein the mount component [50] is mounted onto a bottom face of the second recess [region 11][See annotated drawing],
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yasuda into the method of Higashitani et al. and Konishi834 to include a mount component having a thickness greater than a thickness of the second semiconductor device, the mount component being a component to be mounted, wherein the first major face includes a second recess, wherein the mount component is mounted onto a bottom face of the second recess. The ordinary artisan would have been motivated to modify Higashitani et al. and Konishi834 in the above manner for the purpose of providing miniaturized high-frequency module including a chip inductor having the high quality factor Q [paragraph [0092], [0110] of Yasuda].
Higashitani et al., Konishi834 and Yasuda fails to disclose
wherein the second recess has a depth less than a depth of the first recess.
Lim discloses in Fig. 3A-3B,
wherein the second recess [103] has a depth less than/equal to a depth of the first recess [104].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lim into the method of Higashitani et al., Konishi834 and Yasuda to include wherein the second recess has a depth less than a depth of the first recess. The ordinary artisan would have been motivated to modify Higashitani et al., Konishi834 and Yasuda in the above manner for the purpose of providing suitable depth of the second recess with respect to a depth of the first recess to achieve slim and compact purposes [paragraph [0035] of Lim].
Further, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a depth of the second recess with respect to a depth of the first recess: a depth of the second recess is greater than/less than/equal to a depth of the first recess. Absent unexpected results, it would have been obvious to try a depth of the second recess is greater than a depth of the first recess to yield a miniatured module.
Regarding claim 5, Konishi834 discloses in Fig. 1, Fig. 4, paragraph [0057]
wherein the second semiconductor device [2] includes at least one of a low-noise amplifier circuit, a switching circuit, or a control circuit [control IC 2f].
Regarding claim 6, Konishi834 discloses in Fig. 1, Fig. 4, paragraph [0060], [0070]
wherein the first semiconductor device [7] includes a first power amplifier circuit [7e, 7h].
Regarding claim 11, Konishi834 discloses in Fig. 1, Fig. 4, paragraph [0049]-[0063]
wherein the second semiconductor device [2] further includes a second power amplifier circuit [2e], wherein the second power amplifier circuit [2e] in cascading connection with the first power amplifier circuit [7e, 7h].
Regarding claim 15, the combination of Konishi834 and Uchida result to “A communication apparatus comprising: a radio-frequency integrated circuit configured to process a radio-frequency signal transmitted and received by an antenna; and the radio-frequency module according to Claim 1 configured to propagate the radio-frequency signal between the antenna and the radio-frequency integrated circuit.”
Notes, “configured to process a radio-frequency signal transmitted and received by an antenna” and “configured to propagate the radio-frequency signal between the antenna and the radio-frequency integrated circuit” directs to intended operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114. Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Claims 2-3, 5-6, 15, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130) and Uchida (US Pub. 20020180058) as applied to claim 1 above.
Regarding claims 2-3, Uchida discloses in Fig 5, paragraph [0060], [0065]
a mold layer [310] sealing the second semiconductor device [310], wherein the anisotropic conductive resin component [315] and the mold layer [310] comprise different materials;
wherein the anisotropic conductive resin component [315] has a thermal conductivity higher than a thermal conductivity of the mold layer [310][the anisotropic conductive resin 315 is a kind of resin which contains conductive spheres while the mold layer [310] is formed of epoxy resin or polyimide resin without conductive sphere. The presence of conductive spheres would result to a thermal conductivity of the anisotropic conductive resin component [315] be higher than a thermal conductivity of the mold layer [310]].
Regarding claims 5, 18 and 19, Konishi et al. discloses in paragraph [0084]
wherein the second semiconductor device [15] includes at least one of a low-noise amplifier circuit, a switching circuit, or a control circuit.
Yasuda discloses in paragraph [0050] wherein the second semiconductor device [40] includes at least one of a low-noise amplifier circuit, a switching circuit, or a control circuit [switching element or an amplifier circuit element].
Regarding claim 6, Konishi et al. discloses in paragraph [0014], [0047]
wherein the first semiconductor device [25] includes a first power amplifier circuit.
Regarding claim 15, the combination of Konishi et al. and Uchida result to “A communication apparatus comprising: a radio-frequency integrated circuit configured to process a radio-frequency signal transmitted and received by an antenna; and the radio-frequency module according to Claim 1 configured to propagate the radio-frequency signal between the antenna and the radio-frequency integrated circuit.”
Notes, “configured to process a radio-frequency signal transmitted and received by an antenna” and “configured to propagate the radio-frequency signal between the antenna and the radio-frequency integrated circuit” directs to intended operation of the device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). MPEP 2114. Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Claims 4, 16 and 17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130) and Uchida (US Pub. 20020180058) as applied to claims 1, 2 and 3 above and further in view of Lambert et al. (US Pub. 20200006305).
Regarding claims 4, 16 and 17, Konishi et al. discloses in paragraph [0045]
wherein the second semiconductor device [15] includes a silicon semiconductor substrate.
Uchida, Konishi et al., Yasuda and Lim fails to disclose
wherein the first semiconductor device includes a compound semiconductor substrate.
However, Uchida discloses in paragraph [0059] the first semiconductor device 302] and the second semiconductor device [304] includes chips that fabricated according to the different process rules.
Lambert et al. discloses in Fig. 2, paragraph [0039]-[0045], [0065]
wherein the first semiconductor device [213 or 413a] includes a compound semiconductor substrate, and
wherein the second semiconductor device [211 or 411] includes a silicon semiconductor substrate.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Lambert et al. into the method of Uchida, Konishi et al., Yasuda and Lim to include wherein the first semiconductor device includes a compound semiconductor substrate. The ordinary artisan would have been motivated to modify Uchida, Konishi et al., Yasuda and Lim in the above manner for the purpose of providing suitable substrate for the first semiconductor device to form a CMOS die and a compound semiconductor die arranged within a semiconductor package [paragraph [0039]-[0045], [0098] of Lambert et al.].
Regarding claim 20, Konishi et al. discloses in paragraph [0084]
wherein the second semiconductor device [15] includes at least one of a low-noise amplifier circuit, a switching circuit, or a control circuit.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130) and Uchida (US Pub. 20020180058) as applied to claim 6 above and further in view of Kwon et al. (US Pub. 20160113115)
Regarding claim 7, Konishi et al. discloses in Fig. 10, paragraph [0041]
wherein the multilayer substrate [2] includes an electric conductor, the electric conductor being disposed at least inside the multilayer substrate [2].
Yasuda also discloses in Fig. 6A
wherein the multilayer substrate [10] includes an electric conductor [15a, b], the electric conductor being disposed at least inside the multilayer substrate [10]
Uchida, Konishi et al., Yasuda and Lim fails to disclose
the electric conductor electrically connecting the first semiconductor device and the second semiconductor device with each other.
Kwon et al. discloses in Fig. 4B, paragraph [0054]
the electric conductor electrically connecting the first semiconductor device [120a] and the second semiconductor device [143] with each other.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kwon et al. into the method of Uchida, Konishi et al., Yasuda and Lim to include the electric conductor electrically connecting the first semiconductor device and the second semiconductor device with each other. The ordinary artisan would have been motivated to modify Uchida, Konishi et al., Yasuda and Lim in the above manner for the purpose of providing layout or routing of the electrically conductive paths within the PCB of an SoP module so that components of the module can communicate each other [paragraph [0047], [0054] of Kwon et al.].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130) and Uchida (US Pub. 20020180058) and Kwon et al. (US Pub. 20160113115) as applied to claim 7 above and further in view of Kobayashi et al. (US Pub. 20200212849).
Regarding claim 8, Uchida, Konishi et al., Yasuda , Lim and Kwon et al. fails to disclose
wherein the first semiconductor device further includes a temperature sensor configured to detect a temperature of the first power amplifier circuit, and
wherein the second semiconductor device includes a bias adjustment circuit, based on the temperature detected by the temperature sensor, configured to adjust a bias to be supplied to the first power amplifier circuit.
Konishi et al. discloses in paragraph [0014], [0045], [0047], [0084]
wherein the first semiconductor device [25] includes the first power amplifier circuit and wherein the second semiconductor device [15] includes a second power amplifier circuit and a control circuit.
Kobayashi et al. discloses in Fig. 1, paragraph [0020]-[0021], [0031]-[0033]
wherein the first semiconductor device/ the first power amplifier circuit [10] further includes a temperature sensor [101] configured to detect a temperature of the first power amplifier circuit [10], and
wherein the second semiconductor device/ the second power amplifier circuit [20] includes a bias adjustment circuit [21], based on the temperature detected by the temperature sensor [101], configured to adjust a bias [PAen] to be supplied to the first power amplifier circuit [10].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kobayashi et al. into the method of Uchida, Konishi et al., Yasuda, Lim and Kwon et al. to include wherein the first semiconductor device further includes a temperature sensor configured to detect a temperature of the first power amplifier circuit, and wherein the second semiconductor device includes a bias adjustment circuit, based on the temperature detected by the temperature sensor, configured to adjust a bias to be supplied to the first power amplifier circuit. The ordinary artisan would have been motivated to modify Uchida, Konishi et al., Yasuda, Lim and Kwon et al. in the above manner for the purpose of compensating the gain that decreases with increase of temperature, and maintaining linearity of the power amplifier [paragraph [0020]-[0021] of Kobayashi et al.].
Claim 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130), Uchida (US Pub. 20020180058), and Kwon et al. (US Pub. 20160113115) as applied to claim 7 above and further in view of Kobayashi et al. (US Pub. 20200212849) and Chen et al. (US Pub. 20190041890).
Regarding claims 9-10, Uchida, Konishi et al., Yasuda, Lim and Kwon et al. fails to disclose
wherein the first semiconductor device further includes a detector circuit configured to detect a characteristic parameter of the first power amplifier circuit, and
wherein the second semiconductor device includes a characteristic adjustment circuit, based on the characteristic parameter detected by the detector circuit, configured to adjust the characteristic parameter;
wherein the characteristic parameter includes at least one of impedance, phase, or power of the first power amplifier circuit.
Konishi et al. discloses in paragraph [0014], [0045], [0047], [0084]
wherein the first semiconductor device [25] includes the first power amplifier circuit and wherein the second semiconductor device [15] includes a second power amplifier circuit and a control circuit.
Kobayashi et al. discloses in Fig. 1, paragraph [0005], [0020]-[0021], [0031]-[0033]
wherein the first semiconductor device/ the first power amplifier circuit [10] further includes a detector circuit [101] configured to detect a characteristic parameter [a temperature] of the first power amplifier circuit [10], and
wherein the second semiconductor device/ the second power amplifier circuit [20] includes a characteristic adjustment circuit [21], based on the characteristic parameter [temperature] detected by the temperature sensor [101], configured to adjust the characteristic parameter [adjusting temperature variable by adjusting bias voltage][“the gain that decreases with increase of temperature is compensated”].
Kobayashi et al. further discloses in paragraph [0008] that it is desired to provide a power amplifier circuit that facilitates the suppression of degradation of linearity of amplification characteristics and maintains linearity of the power amplifier.
Chen et al. discloses in Fig. 1A, Fig. 3, paragraph [0004], [0005], [0022] that power is an amplification characteristic and is needed to adjust to improve linearity of the power amplifier circuit.
Chen et al. discloses
wherein the first semiconductor device [PA1, 10a, M1, 20] or [PA1, PA2, PA3 and 20] further includes a detector circuit [20] configured to detect a characteristic parameter of the first power amplifier circuit [PA1 or PA3], and
wherein the second semiconductor device includes a characteristic adjustment circuit [30], based on the characteristic parameter detected by the detector circuit [20], configured to adjust the characteristic parameter [adjusting power by adjusting current];
wherein the characteristic parameter includes at least one of impedance, phase, or power of the first power amplifier circuit [power].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kobayashi et al. and Chen et al. into the method of Uchida, Konishi et al., Yasuda, Lim and Kwon et al. to include wherein the first semiconductor device further includes a detector circuit configured to detect a characteristic parameter of the first power amplifier circuit, and wherein the second semiconductor device includes a characteristic adjustment circuit, based on the characteristic parameter detected by the detector circuit, configured to adjust the characteristic parameter; wherein the characteristic parameter includes at least one of impedance, phase, or power of the first power amplifier circuit. The ordinary artisan would have been motivated to modify Uchida, Konishi et al., Yasuda, Lim and Kwon et al. in the above manner for the purpose of providing a compensation circuit to improve linearity of the power amplifier [paragraph [0020]-[0021] of Kobayashi et al., paragraph [0004], [0005], [0022] of Chen et al.].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yasuda (US Pub. 20190320531), Lim (US Pub. 20200152557), Konishi et al. (US Pub. 20060171130), Uchida (US Pub. 20020180058) as applied to claim 6 above and further in view of Naniwa (US Pub.20200235772).
Regarding claim 12, Konishi et al. discloses in paragraph [0014], [0015]
a matching circuit being connected with the first power amplifier circuit [25].
Uchida, Konishi et al., Yasuda, and Lim fails to disclose
wherein the multilayer substrate includes the matching circuit built in the multilayer substrate.
Naniwa discloses in Fig. 5-Fig. 10, paragraph [0043]-[0044], [0062]-[0065]
wherein the multilayer substrate [91] includes the matching circuit [42] built in the multilayer substrate [91].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Naniwa into the method of Uchida, Konishi et al., Yasuda, and Lim to include wherein the multilayer substrate includes the matching circuit built in the multilayer substrate. The ordinary artisan would have been motivated to modify Uchida, Konishi et al., Yasuda, and Lim in the above manner for the purpose of suppressing degradation in quality of reception signals and providing a miniaturized module [paragraph [0109] of Naniwa].
Response to Arguments
Applicant's arguments filed 08/20/2025 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments on page 6 of Applicant’s remark that “Figs. 1-2 illustrate a first semiconductor device 10, and [0056] of the present application describes that the first semiconductor device 10 includes a detector circuit. Given this, one would understand that the illustrated semiconductor device 10 to be a representation of a detector circuit.” Examiner respectfully disagrees because of the following reason:
First, the specification does not define semiconductor device 10 as a detector circuit.
Second, Fig. 2 illustrate a first semiconductor device 10 and paragraph [0043] of Applicant describes “the first semiconductor device 10 includes the power amplifier circuits 131, 132, and 133 and the matching circuits 113, 114, 115, and 116.” Clearly, the illustrated semiconductor device 10 is not a representation of any circuit (i.e. power amplifier circuits, matching circuits…) included in the illustrated semiconductor device 10. Further, any attempt to use the same element number for different claim features will be subjected to drawing objection and specification objection. See 37 CFR 1.84(p)(4) “The same part of an invention appearing in more than one view of the drawing must always be designated by the same reference character, and the same reference character must never be used to designate different parts” and MPEP 608.01 (o) “The meaning of every term used in any of the claims should be apparent from the descriptive portion of the specification with clear disclosure as to its import; and in mechanical cases, it should be identified in the descriptive portion of the specification by reference to the drawing, designating the part or parts therein to which the term applies… The use of a confusing variety of terms for the same thing should not be permitted.”
Consequently, Applicant’s argument does not have support and are not persuasive, the drawing objection is maintained.
Regarding Applicant’s argument with respect to Yasuda and Farooq et al., Examiner respectfully disagrees because of the following reasons.
First, the elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). MPEP 2131.
The below annotated drawings of Applicant’s Fig. 1C and Yasuda’s Fig. 6A illustrating the claimed major face, the claimed recesses and those disclosed by Yasuda. In addition, Fig. 2 and column 3, lines 32, 44-45 of US Pat. 7642640 provided support for Examiner’s interpretation of “recess”. Therefore, Applicant is required to provide a clear definition of major surface and recess as well as prove that the features identified in Yasuda’s Fig. 6A should not be interpreted as major face and recesses.
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Finally, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
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