Detailed Action
The instant application having Application No. 18/158,620 has a total of 19 claims pending in the application; there are 2 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the arguments filed 12/10/25. Claims 1 and 4-21 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-8, 12-17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (U.S. Patent Application Publication No. 2015/0178092), herein referred to as Mishra et al. in view of Davis et al. (U.S. Patent No. 10,346,342), herein referred to as Davis et al.
Referring to claim 1, Mishra et al. disclose as claimed, a computer comprising: a first computer device of a first class; a second computer device of the first class, each computer device of the first class comprising a first external port and a second external port, at least one memory controller configured to attach to external memory (see fig. 6 showing memory controller 106a and memory controller 106b, which would be the first and second devices of the first class. See fig. 7 and para. 62, where each memory controller has die-to-die communication channels for input and output, which would be the first and second links (coupled to a processor). Also see para.54. See para. 19, where the routing networks are built into the dies of the memory controller), and routing logic configurable to route data from the first external port to one of the at least one memory controller and the second external port (see para. 54-57, where the die to die channel is coupled to the memory controller, and therefore data flowing into the first external port would flow to the memory controller. Outgoing packets are then routed by the die of the memory controller through the unit level parallel partition switch to be transferred to the die of a microprocessor, which would therefore be routed through the second external port. See para. 19, where the routing networks are built into the dies of the memory controller); a third computer device of a second class (see para. 22, where each block in a plurality of blocks contains a plurality of processors and memories. See para. 53, where each unit 210a-n has an associated memory controller and may have 8 blocks in a unit. Each unit would be a device of a second class. See fig. 2, showing unit 210a comprising multiple blocks), the third computer device being connected to the first external ports via first and second links (see para. 54, where the processors are connected to the memory controllers via die-to-die channels. Each parallel partition switch 410a-410n as shown in fig. 5 connects to a unit (containing processors) and connects to a memory controller), the third computer device comprising first processing circuitry configured to execute a first computer program and connected to the first and second links to transmit and receive messages (see para. 17-22, where each block includes a plurality of processors which would execute computer programs. See para. 27-28, where the processors send and receive packets. See fig. 7, where a processor is connected to a first and second links as shown in die to die input and output channels); and a fourth computer device of the second class, the fourth computer device being connected to the second external ports via third and fourth links, the fourth computer device comprising second processing circuitry configured to execute a second computer program (see para. 53, where there are multiple units, and a fourth computer device would be a second unit which would also be connected to the memory controller which contains a second external port via a parallel partition switch as shown in fig. 5. The third and fourth links would be the input and output channels as shown in fig. 7) and connected to the third and fourth links to transmit and receive messages (See para. 27-28, where the processors send and receive packets.); wherein the third computer device is configured to transmit a message to the first external port of the first computer device via the first link, and the routing logic on the first computer device is configured to route the message to the second external port of the first computer device and to transmit the message to the fourth computer device (see Mishra et al., fig. 7, where a processor would send a message to the memory controller though an input first link, and the memory controller would then route that data to another processor (fourth computer) through the output link. Also see para. 54, where the processors and memory controllers have die-to-die communication channels and para. 53, where each processor has an associated memory controller. See fig. 6, where each memory controller such as 106a is coupled to each unit/processor or computer device, and messages between processors would need to be routed through the memory controllers).
Mishra et al. disclose the claimed invention except for wherein each of the first, second, third and fourth links comprise fixed point-to-point links without intermediate switches.
However, Davis et al. disclose wherein each of the first, second, third and fourth links comprise fixed point-to-point links without intermediate switches (see col. 3, lines 29-50, where each system on a chip is connected serially with a point-to-point link to multiple different memory agents, providing uniform latency).
Mishra et al. and Davis et al. are analogous art because they are from the same field of endeavor of integrated circuits (see Mishra et al., abstract and Davis et al., abstract, regarding integrated circuits and System on chips).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra et al. to comprise wherein each of the first, second, third and fourth links comprise fixed point-to-point links without intermediate switches, as taught by Davis et al., in order to provide uniform access latency to different memories or controllers from each processor or SoC (see Davis, col. 3, lines 29-50, regarding advantages of multiple fixed point to point links without intermediate switches)
As to claim 4, Mishra et al. and Davis et al. also disclose the computer of claim 1 wherein the first, second, third and fourth links comprise serial links (see Mishra et al., para. 27, where the links may be a serial or parallel bus or cross-bar or matrix switch network).
As to claim 5, Mishra et al. and Davis et al. also disclose the computer of claim 1 wherein the third computer device is configured to transmit a memory access message to the first computer device, and wherein the routing logic of the first computer device is configured to route the memory access message to its at least one memory controller for accessing the external memory (see Mishra et al., para. 54-57, where the die to die channel is coupled to the memory controller, and data going to the memory or another processing unit would pass through the first device or memory controller, which routes the data. See para. 19, where the routing networks are built into the dies of the memory controller).
As to claim 6, Mishra et al. and Davis et al. also disclose the computer of claim 5 wherein the memory access message is a memory write (see Mishra et al., para. 27, where memory accesses may be reads or writes).
As to claim 7, Mishra et al. and Davis et al. also disclose the computer of claim 5 wherein the memory access message is a memory read (see Mishra et al., para. 27, where memory accesses may be reads or writes).
As to claim 8, Mishra et al. and Davis et al. also disclose the computer of claim 1 wherein the first computer device comprises a single chip having a fabric core in which the routing logic is implemented and a port connection region extending along one longitudinal edge of the chip in which the first external port is arranged (see Mishra et al., para. 19, where the routing networks may be built into the dies of the memory controller, and therefore the memory controller would have a fabric core or routing logic built in. See fig. 6, showing memory controllers having a connection region along one edge of the chip as they connect to memory or the processor).
As to claim 12, Mishra et al. and Davis et al. also disclose the computer of claim 1 wherein the first computer device comprises one or more memory attachment interfaces for attaching the at least one memory controller to the external memory (see Mishra et al., fig. 1, showing the memory controllers connected to external memory. A interface would be necessary and therefore part of the memory controller in order to send/receive data from the external memory. See para. 80, where data gets routed from the memory controller to the external memory).
As to claim 13, Mishra et al. and Davis et al. also disclose the computer of claim 1 further comprising a first cluster of n computer devices of the first class and N computer devices of the second class, where n is two or more, and N is greater than two and wherein each computer device of the second class is connected to the n computer devices of the first class via respective fixed links, and each computer device of the first class is connected to the N computer devices of the second class via respective fixed links (see Mishra et al., fig. 6, showing multiple memory controllers, which would be devices of the first class, and multiple processing blocks, which would be devices of the second class. An example memory controller 106a is shown connecting to each processing block 200, and each processing block 200 is coupled to each memory controller. Also see para. 54).
As to claim 14, Mishra et al. and Davis et al. also disclose the computer of claim 13 wherein n is greater than or equal to N (see Mishra et al., fig. 6, where the amount of processing blocks and memory controllers is equal).
As to claim 15, Mishra et al. and Davis et al. also disclose the computer of claim 13 wherein there are no direct connections between computer devices of the first class, or between computer devices of the second class, in the first cluster (see Mishra et al., fig. 6, showing no direct connections between memory controllers and no direct connections between processing blocks).
As to claim 16, Mishra et al. and Davis et al. also disclose the computer of claim 13 further comprising: a second cluster of n computer devices of the first class and N computer devices of the second class; and at least one cluster connecting link which is connected between a particular computer device of the first class in the first cluster and a particular computer device of the first class in the second cluster (see Mishra et al., para. 53-54, where each unit has an associated memory controller, and each processing block and memory controller are interconnected. Therefore a cluster of 2 computer devices of each class (for example, 106a and 106b) would be interconnected with another cluster of 2 other computer devices of each class (for example 106c and 106d)).
As to claim 17, Mishra et al. and Davis et al. also disclose the computer of claim 1 further comprising a switch fabric, wherein the first computer device comprises a system connection configured to connect to the switch fabric (see Mishra et al., fig. 6, showing the memory controller connected to unit level partition switches which would be a switch fabric).
Referring to claim 19, Mishra et al. disclose as claimed, a method of routing packets in a computer comprising a first computer device of a first class, a second computer device of the first class (see fig. 6 showing memory controller 106a and memory controller 106b, which would be the first and second devices of the first class), a third computer device of a second class, and a fourth computer device of the second class (see para. 22, where each block in a plurality of blocks contains a plurality of processors and memories. See para. 53, where each unit 210a-n has an associated memory controller and may have 8 blocks in a unit. Each unit would be a device of a second class. See fig. 2, showing unit 210a comprising multiple blocks), the method comprising: transmitting a packet from a designated external port of the third computer device, the external port being connected to the first computer device (see para. 54-57, where the die to die channel is coupled to the memory controller, and therefore data flowing into the first external port from the processors or third computer device would flow to the memory controller or the first computer device), wherein the packet contains destination information (see para. 68, where packets are forwarded based on tag information); at routing logic of the first computer device, determining from the destination information that the packet is destined for either: memory attached to the first computer device or the fourth computer device attached to an external port of the first computer device; and routing the packet according to the destination information (see para. 68, where the parallel partition packet network control logic, which is built into the memory controller (see para. 19) routes the packets to their destinations).
Mishra et al. disclose the claimed invention except for where the external port is connected to the first computer device via a fixed point-to-point link without intermediate switches.
However, Davis et al. disclose for where the external port is connected to the first computer device via a fixed point-to-point link without intermediate switches (see col. 3, lines 29-50, where each system on a chip is connected serially with a point-to-point link to multiple different memory agents, providing uniform latency).
Mishra et al. and Davis et al. are analogous art because they are from the same field of endeavor of integrated circuits (see Mishra et al., abstract and Davis et al., abstract, regarding integrated circuits and System on chips).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra et al. to comprise for where the external port is connected to the first computer device via a fixed point-to-point link without intermediate switches, as taught by Davis et al., in order to provide uniform access latency to different memories or controllers from each processor or SoC (see Davis, col. 3, lines 29-50, regarding advantages of multiple fixed point to point links without intermediate switches)
As to claim 20, Mishra et al. and Davis et al. also disclose the method of claim 19, wherein the determining comprises determining from the destination information that the packet is destined for the memory attached to the first computer device; and wherein the routing the packet comprises routing the packet to a memory controller of the first computer device (see Mishra et al., para. 68, where the logic determines the destination from the tag in the packet and then routes the packet appropriately. See fig. 6, showing the connections between the routing logic and the memory controller and system memory).
As to claim 21, Mishra et al. and Davis et al., also disclose the method of claim 19, wherein the determining comprises determining from the destination information that the packet is destined for the fourth computer device; and wherein the routing the packet comprises routing the packet to the external port (see Mishra et al., fig. 7, where a processor would send a message to the memory controller though an input first link, and the memory controller would then route that data to another processor (fourth computer) through the output link. Also see para. 54, where the processors and memory controllers have die-to-die communication channels and para. 53, where each processor has an associated memory controller. See fig. 6, where each memory controller such as 106a is coupled to each unit/processor or computer device, and messages between processors would need to be routed through the memory controllers).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. in view of Davis et al. and in view of Teh et al. (U.S. Patent Application No. 2020/0104064), herein referred to as Teh et al.
As to claim 9, Mishra et al. and Davis et al. disclose the claimed invention except for the computer of claim 1 wherein the third computer device comprises a single chip having a first processor core in which the first processing circuitry is implemented, a plurality of edges and a processor port connection region arranged along at least one edge of the plurality of edges of the chip in which processor ports are arranged connected to the first and second links, the chip comprising a further processor port connection region along an opposite edge of the plurality of edges of the chip, the further processor port connection region comprising further processor ports for connection to additional links connected to additional computer devices of the first class.
However, Teh et al. disclose wherein the third computer device comprises a single chip having a first processor core in which the first processing circuitry is implemented, a plurality of edges and a processor port connection region arranged along at least one edge of the plurality of edges of the chip in which processor ports are arranged connected to the first and second links, the chip comprising a further processor port connection region along an opposite edge of the plurality of edges of the chip, the further processor port connection region comprising further processor ports for connection to additional links connected to additional computer devices of the first class (see fig. 3, showing a processor core with a plurality of edges and a port connection region connecting first and second links 309 on one side, as well as a further port connection region along the opposite edge).
Mishra et al. and Teh et al. are analogous art because they are from the same field of endeavor of integrated circuits (see Mishra et al., abstract and Teh et al., abstract, regarding integrated circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra et al. to comprise wherein the third computer device comprises a single chip having a first processor core in which the first processing circuitry is implemented, a plurality of edges and a processor port connection region arranged along at least one edge of the plurality of edges of the chip in which processor ports are arranged connected to the first and second links, the chip comprising a further processor port connection region along an opposite edge of the plurality of edges of the chip, the further processor port connection region comprising further processor ports for connection to additional links connected to additional computer devices of the first class, as taught by Teh et al., in order to take advantage of every edge of the chip to connect to more devices. It should be noted that this would be advantageous for Mishra et al. to implement as Mishra’s processors need to connect to a large amount of memory controllers.
As to claim 10, Mishra et al., Davis et al. and Teh et al. also disclose the computer of claim 9 wherein the first processor core extends substantially to other edges of the plurality of edges of the chip (see Teh et al., fig. 3, showing the processor core extending to other edges of the chip).
As to claim 11, Mishra et al., Davis et al., and Teh et al. also disclose the computer of claim 9 wherein the other edges of the plurality of edges of the chip comprise high bandwidth memory connectors configured to connect the chip to at least one high bandwidth memory device (see Teh et al., fig. 3, showing the other edges of the chip having high bandwidth memory connectors and connected to high bandwidth memory devices).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. in view of Davis et al. and in view of Gray (U.S. Patent Application No. 2017/0220499), herein referred to as Gray.
As to claim 18, Mishra et al. and Davis et al. disclose the claimed invention except for the computer of claim 1 wherein the first computer device comprises a host connector configured to connect to a host.
However, Gray discloses wherein the first computer device comprises a host connector configured to connect to a host (see fig. 1 and para. 5, showing a large computing network with multiple processors and memories connected to a host through a host connector. Each router connects to a processor and also connects to the host device. When combined with Mishra, this would allow each memory controller to connect to the host device).
Mishra et al. and Gray are analogous art because they are from the same field of endeavor of integrated circuits (see Mishra et al., abstract and Gray, abstract, regarding integrated circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra et al. to comprise wherein the first computer device comprises a host connector configured to connect to a host, as taught by Gray, in order to allow for greater control and faster communication from a host. In addition it is well known in the art for memory controllers to connect and send/receive data to/from hosts.
Response to Arguments
Applicant's arguments, filed 12/10/25, have been fully considered but they are not persuasive.
Applicant argues that Mishra describes packets being routed from the die of the memory controller to the microprocessor, but does not discuss packets being routed by the network from a processor to a processor. Applicant argues that at a block level, packets are routed through the local block network to the destination within the block, and at the unit level, they are routed via the unit level switch or the unit-to-unit switch.
However, claim 1 recites routing messages from one computer device to another. A computer device given a broadest reasonable interpretation could include unit switches or unit-to-unit switches, both of which do route packets from processor to processor. In addition, Mishra, para. 62-63 discloses that the memory controller may also contain a unit level switch which is coupled to each parallel partition packet network. So a computer device could certainly contain both a memory controller and unit level switches or unit-to-unit switches, which would be operable to route packets from processor to processor. This was clearly envisioned by Mishra as well, which in para. 62-63 discloses that the memory controller may contain a unit level switch. However, even without that, applicant’s claim 1 only recites the limitation of computer device. A computer device could certainly include both a switch and a memory controller.
Applicant further argues that in Davis, the system on chips are in direct communication by inter-socket interconnects. It is unclear how the chips being connected to memory via point-to-point links is in contrast to claim 1. Davis is being combined to show that network connections may be done serially through point to point links to provide uniform latency and speed.
Applicant additionally argues that it would not have been obvious to combine Mishra and Davis because Mishra discloses a hierarchical and parallel partition network to interconnect circuit dies, in order to improve efficiency, and a modification would render Mishra unsatisfactory for its intended purpose. A combination such as taught by Mishra and Davis would allow for a network that has improved speed via more direct connections as well as uniform latency. Mishra’s intended purpose is to offer a connection network between various processors/memory. The combination of Mishra/Davis still does that, just with a different method of interconnection that would have advantages/disadvantages. See Davis, col. 3, lines 29-50, regarding advantages of multiple fixed point to point links without intermediate switches.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 and 4-21 stand rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132