DETAILED ACTION
This action is filed in response to the Request for Continued Examination filed on 11/06/2025.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/06/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-29 have been considered but
are not persuasive. Applicant argues the cited prior art does not teach a central EDT circuit because the test circuits in Chakraborty are coupled in series. Examiner notes the central EDT circuit embodiment is fulfilled by the test controllers Elements 511 and 611 in Figures 5 and 6 respectively. These test controllers are connected to all other EDT circuits and is responsible for multiplexing and demultiplexing the data.
The amendments to Claims 1, 2, 4, 10, 13, 20, 23, and 25 are addressed in the rejections below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 10-14, 16, 20-24, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chakraborty (US20090193306A1).
Regarding Claim 1, Chakraborty teaches an integrated circuit device (e.g. see [Fig. 13 Element 1330] and [0021] “FIG. 13 depicts a high-level block diagram of a testing environment in which a testing system is used for testing a system-on-chip having embedded thereon a system-on-chip”), comprising:
two or more semiconductor dice (e.g. see [0068] “In one embodiment, the testing scan path and control scan path may be implemented using combined physical components. In one embodiment, for example, the system-on-chip includes a plurality of non-hierarchical testing components and at least one hierarchy-enabling component”), each semiconductor die comprising:
a circuit block configured to implement a function of the integrated circuit device (e.g. see [Fig. 2 Elements 210] and [0038-0041]); and
wherein the circuit block is partitioned into a plurality of embedded distributed test (EDT) sections; and a plurality of EDT circuits, wherein at least one EDT circuit is provided in each EDT section in the plurality of EDT sections, and wherein each pf the plurality of EDT circuits is configured to collect test information from a corresponding EDT section (e.g. see [Fig. 6 Elements TC00, TC01, TC10, TC11, TC20, and TC21] and [0073] Examiner notes the prior art shows 6 EDT test sections each with one test circuit); and
a central EDT circuit provided in the circuit block (e.g. see [Fig. 5 and Fig.6; Elements 511 and 611] Examiner notes the testing controllers described in [0055] and [0074] are central EDT circuits) configured to receive an input from each EDT circuit in the plurality of EDT circuits (e.g. see [0074] “The application of the input testing vector to the testing scan path 621 results in an output testing vector being received by testing controller 611 from testing scan path 621 via the internal ITDO output coupled to the output of testing scan path 621. The testing controller 611 propagates the output testing vector to the testing system, which processes the output testing vector in order to determine testing results”) and
to provide an output EDT data stream by multiplexing the input received from the each EDT circuit with inputs received from other EDT circuits in the plurality of EDT circuits (e.g. see [0059-0060] “The system-on-chip 500 includes an output control MUX514. The output control MUX514 includes two input ports: a first input port coupled to the output from testing scan path 521 (denoted as ITDO) and a second input port coupled to the output from control scan path 526 (denoted as HTDO). The output control MUX514 includes an output port coupled to the TDO port of testing controller 511…The input control DEMUX513 and output control MUX514 are each controlled by an internal register (IR) 515. The IR 515 is loaded with control values, as desired/needed, to control input control DEMUX 513 and output control MUX514. The control values may be loaded into IR 515 by testing controller 511 (e.g., using control signals received from an associated testing system)”).
Regarding Claim 2, Chakraborty teaches the limitations of Claim 1. Chakraborty further discloses wherein each EDT circuit comprises: a demultiplexer configured to extract one or more channels in a multiplexed EDT data stream that are allocated to the each EDT circuit (e.g. see [0058]); and
a multiplexer configured to recombine the one or more channels that are allocated to the each EDT circuit into the output EDT data stream (e.g. see [0059]).
Regarding Claim 3, Chakraborty teaches the limitations of Claim 1. Chakraborty further discloses wherein the central EDT circuit is configured to: distribute a plurality of channels in a multiplexed EDT data stream to the plurality of EDT circuits, wherein the test information collected by each EDT circuit is inserted into a channel that is distributed to the each EDT circuit (e.g. see [0059] “The output control MUX 514 includes an output port coupled to the TDO port of testing controller 511. The output control MUX 514 is adapted to couple the output bitstream from the testing scan path 521 or the output bitstream from the control scan path 526 to the TDO output (via testing controller 511) as desired/needed,” [0060], and [0061] “The output of internal register 515 is coupled to a control port of output control MUX 514 to control selection of output bitstreams from testing scan path 521 and control scan path 526 (i.e., to decide, for each output bit slot, whether to select the output bit value available from testing scan path 521 or to select the output bit value available from control scan path 526)”).
Regarding Claim 4, Chakraborty teaches the limitations of Claim 3. Chakraborty further discloses wherein the central EDT circuit is further configured to combine channels output by the plurality of EDT circuits to obtain the output data test data stream (e.g. see [0061] “the output of internal register 515 is coupled to a control port of input control DEMUX 513 to control application of input bitstreams to testing scan path 521 and control scan path 526 (i.e., to decide, for each input bit value, whether to apply that input bit value to testing scan path 521, control scan path 526, or both testing scan path 521 and control scan path 526”).
Regarding Claim 6, Chakraborty teaches the limitations of Claim 1. Chakraborty further discloses wherein the circuit block is partitioned into a plurality of EDT sections based on a distribution of interconnects associated with the plurality of EDT circuits (e.g. see [0036] “FIG. 2 depicts a high-level block diagram of an exemplary system-on-chip adapted for used in the testing environment of FIG. 1. As depicted in FIG. 2, S-o-C 110 includes a plurality of components 210.sub.A-210.sub.E (collectively, components 210) which are interconnected by a plurality of component interconnections 220 (collectively, component interconnections 220). It will be understood that S-o-C 110 depicted and described with respect to FIG. 2 merely constitutes an example of a system-on-chip (i.e., S-o-C 110 may include various other components that may be configured in various other ways)”).
Regarding Claim 10, Chakraborty discloses a method for communicating test information, comprising: providing a data stream to a circuit block that is implemented on a semiconductor die (e.g. see [0030] “The TC 111 receives input bitstreams from TC 120 via input port 115.sub.l. The TC 111 controls application of input bitstreams to the testing scan path of S-o-C 110 (via an internal testing input interface ITDI) and the control scan path of S-o-C 110 (via an internal control input interface HTDI). The TC 111 transmits output bitstreams to TC 120 via output port 11 5o. The TC 111 controls selection of output bitstreams from the testing scan path of S-o-C 110 (via an internal testing output interface ITDO) and from the control scan path of S-o-C 110 (via an internal control output interface HTDO) for propagation to TS 120,” and [0036] “FIG. 2 depicts a high-level block diagram of an exemplary system-on-chip adapted for used in the testing environment of FIG. 1. As depicted in FIG. 2, S-o-C 110 includes a plurality of components 210.sub.A-210.sub.E (collectively, components 210) which are interconnected by a plurality of component interconnections 220 (collectively, component interconnections 220)”);
wherein the circuit block is partitioned into a plurality of embedded distributed test (EDT) sections and at least one EDT circuit is provided in each EDT section in the plurality of EDT sections (e.g. see [Fig. 6 Elements TC00, TC01, TC10, TC11, TC20, and TC21] and [0073] Examiner notes the prior art shows 6 EDT test sections each with one test circuit);
demultiplexing data channels from the data stream at a central EDT circuit (e.g. see [0058] “The system-on-chip 500 includes an input control DEMUX 513. The input control DEMUX 513 includes an input port coupled to the TDI port of testing controller 511”);
multiplexing the data channels at the central EDT circuit to obtain a modified data stream after test information collected by the central EDT circuit from each of the plurality of EDT sections has been inserted into one or more data channels allocated to the plurality of EDT sections of the circuit block by corresponding (EDT) circuits (e.g. see [0059-[0061] and [0073]); and
transmitting the modified data stream from the central EDT circuit to another circuit block implemented on the semiconductor die (e.g. see [0058] and [0061] “The output of internal register 515 is coupled to a control port of input control DEMUX 513 to control application of input bitstreams to testing scan path 521 and control scan path 526 (i.e., to decide, for each input bit value, whether to apply that input bit value to testing scan path 521, control scan path 526, or both testing scan path 521 and control scan path 526”).
Regarding Claim 11, Chakraborty teaches the limitations of Claim 10. Chakraborty further discloses wherein each EDT circuit is configured to: extract at least one data channel allocated to the each EDT circuit (e.g. see [0057] “As depicted in FIG. 5, since system-on-chip 500 supports two scan paths to which bitstreams must be applied in order to test system-on-chip 500 (namely, testing scan path 521 and control scan path 526), system-on-chip 500 supports two internal inputs and two internal outputs within system-on-chip 500”); and
use a multiplexer to recombine the at least one data channel allocated to the each EDT circuit into an output EDT data stream (e.g. see [0059]).
Regarding Claim 12, Chakraborty teaches the limitations of Claim 10. Chakraborty further discloses distributing a portion of the data channels to each EDT circuit based on location of the circuit block and an association between the circuit block and the each EDT circuit (e.g. see [0104] “In this example, the HTDI control input is coupled to the HTDI port of testing controller 910 and the HTDO control output is coupled to the HTDI input of hierarchy-enabling component HC00 (i.e., the control ports of each hierarchy-enabling component are directly connected to control ports of adjacent hierarchy-enabling components in the control scan path such that the control bits may pass directly between hierarchy-enabling components and do not need to pass through the non-hierarchy-enabling testing components which may be disposed between hierarchy-enabling components)”).
Regarding Claim 13, Chakraborty teaches the limitations of Claim 10. Chakraborty further discloses wherein the central EDT circuit is configured to distribute the data channels in the data stream among the EDT circuits (e.g. see [0059] “The output control MUX 514 includes an output port coupled to the TDO port of testing controller 511. The output control MUX 514 is adapted to couple the output bitstream from the testing scan path 521 or the output bitstream from the control scan path 526 to the TDO output (via testing controller 511) as desired/needed,” [0060], and [0061] “The output of internal register 515 is coupled to a control port of output control MUX 514 to control selection of output bitstreams from testing scan path 521 and control scan path 526 (i.e., to decide, for each output bit slot, whether to select the output bit value available from testing scan path 521 or to select the output bit value available from control scan path 526)”).
Regarding Claim 14, Chakraborty teaches the limitations of Claim 13. Chakraborty further discloses wherein the central EDT circuit is further configured to combine output channels provided by the EDT circuits to obtain the modified data stream (e.g. see [0061] “the output of internal register 515 is coupled to a control port of input control DEMUX 513 to control application of input bitstreams to testing scan path 521 and control scan path 526 (i.e., to decide, for each input bit value, whether to apply that input bit value to testing scan path 521, control scan path 526, or both testing scan path 521 and control scan path 526”).
Regarding Claim 16, Chakraborty teaches the limitations of Claim 10. Chakraborty further discloses wherein the circuit block is partitioned into a plurality of EDT sections based on a distribution of interconnects associated with the EDT circuits (e.g. see [0036] “FIG. 2 depicts a high-level block diagram of an exemplary system-on-chip adapted for used in the testing environment of FIG. 1. As depicted in FIG. 2, S-o-C 110 includes a plurality of components 210.sub.A-210.sub.E (collectively, components 210) which are interconnected by a plurality of component interconnections 220 (collectively, component interconnections 220). It will be understood that S-o-C 110 depicted and described with respect to FIG. 2 merely constitutes an example of a system-on-chip (i.e., S-o-C 110 may include various other components that may be configured in various other ways)”).
Regarding Claim 20, Chakraborty discloses an apparatus comprising: means for providing a data stream to a circuit block that is implemented on a semiconductor die (e.g. see [0030] “The TC 111 receives input bitstreams from TC 120 via input port 115.sub.l. The TC 111 controls application of input bitstreams to the testing scan path of S-o-C 110 (via an internal testing input interface ITDI) and the control scan path of S-o-C 110 (via an internal control input interface HTDI). The TC 111 transmits output bitstreams to TC 120 via output port 11 5o. The TC 111 controls selection of output bitstreams from the testing scan path of S-o-C 110 (via an internal testing output interface ITDO) and from the control scan path of S-o-C 110 (via an internal control output interface HTDO) for propagation to TS 120,” and [0036] “FIG. 2 depicts a high-level block diagram of an exemplary system-on-chip adapted for used in the testing environment of FIG. 1. As depicted in FIG. 2, S-o-C 110 includes a plurality of components 210.sub.A-210.sub.E (collectively, components 210) which are interconnected by a plurality of component interconnections 220 (collectively, component interconnections 220)”);
wherein the circuit block is partitioned into a plurality of embedded distributed test (EDT) sections and at least one EDT circuit is provided in each EDT section in the plurality of EDT sections (e.g. see [Fig. 6 Elements TC00, TC01, TC10, TC11, TC20, and TC21] and [0073] Examiner notes the prior art shows 6 EDT test sections each with one test circuit);
means for demultiplexing data channels from the data stream, including a central EDT circuit that is configured to receive an input from the at least one EDT circuit in each EDT section (e.g. see [0058] Examiner notes the central EDT embodiment is fulfilled by test controller 511 which is coupled to the demultiplexer); and
means for multiplexing the data channels to obtain a modified data stream after test information collected from the plurality of EDT sections has been inserted into one or more data channels allocated to the plurality of EDT sections of the circuit block by corresponding EDT circuits, wherein the test information is received by the central EDT circuit in inputs provided by the at least one EDT circuit in each EDT section in the plurality of EDT sections (e.g. see [0059-[0061] and [0073]),
wherein the modified data stream is transmitted by the central EDT circuit to another circuit block implemented on the semiconductor die (e.g. see [0058] and [0061] “The output of internal register 515 is coupled to a control port of input control DEMUX 513 to control application of input bitstreams to testing scan path 521 and control scan path 526 (i.e., to decide, for each input bit value, whether to apply that input bit value to testing scan path 521, control scan path 526, or both testing scan path 521 and control scan path 526”).
Regarding Claim 21, Chakraborty teaches the limitations of Claim 20. Chakraborty further discloses wherein each EDT circuit is configured to: extract at least one data channel allocated to the each EDT circuit (e.g. see [0057] “As depicted in FIG. 5, since system-on-chip 500 supports two scan paths to which bitstreams must be applied in order to test system-on-chip 500 (namely, testing scan path 521 and control scan path 526), system-on-chip 500 supports two internal inputs and two internal outputs within system-on-chip 500”); and
use a multiplexer to recombine the at least one data channel allocated to the each EDT circuit into an output EDT data stream (e.g. see [0059]).
Regarding Claim 22, Chakraborty teaches the limitations of Claim 20. Chakraborty further discloses means for distributing a portion of the data channels to each EDT circuit based on location of the circuit block and an association between the circuit block and the each EDT circuit (e.g. see [0104] “In this example, the HTDI control input is coupled to the HTDI port of testing controller 910 and the HTDO control output is coupled to the HTDI input of hierarchy-enabling component HC00 (i.e., the control ports of each hierarchy-enabling component are directly connected to control ports of adjacent hierarchy-enabling components in the control scan path such that the control bits may pass directly between hierarchy-enabling components and do not need to pass through the non-hierarchy-enabling testing components which may be disposed between hierarchy-enabling components)”)..
Regarding Claim 23, Chakraborty teaches the limitations of Claim 20. Chakraborty further discloses wherein the central EDT circuit is configured to distribute the data channels in the data stream among the EDT circuits (e.g. see [0059] “The output control MUX 514 includes an output port coupled to the TDO port of testing controller 511. The output control MUX 514 is adapted to couple the output bitstream from the testing scan path 521 or the output bitstream from the control scan path 526 to the TDO output (via testing controller 511) as desired/needed,” [0060], and [0061] “The output of internal register 515 is coupled to a control port of output control MUX 514 to control selection of output bitstreams from testing scan path 521 and control scan path 526 (i.e., to decide, for each output bit slot, whether to select the output bit value available from testing scan path 521 or to select the output bit value available from control scan path 526)”).
Regarding Claim 24, Chakraborty teaches the limitations of Claim 23. Chakraborty further discloses wherein the central EDT circuit is further configured to combine output channels provided by the EDT circuits to obtain the modified data stream (e.g. see [0061] “the output of internal register 515 is coupled to a control port of input control DEMUX 513 to control application of input bitstreams to testing scan path 521 and control scan path 526 (i.e., to decide, for each input bit value, whether to apply that input bit value to testing scan path 521, control scan path 526, or both testing scan path 521 and control scan path 526”).
Regarding Claim 26, Chakraborty teaches the limitations of Claim 20. Chakraborty further discloses wherein the circuit block is partitioned into the plurality of EDT sections based on a distribution of interconnects associated with the EDT circuits (e.g. see [0036] “FIG. 2 depicts a high-level block diagram of an exemplary system-on-chip adapted for used in the testing environment of FIG. 1. As depicted in FIG. 2, S-o-C 110 includes a plurality of components 210.sub.A-210.sub.E (collectively, components 210) which are interconnected by a plurality of component interconnections 220 (collectively, component interconnections 220). It will be understood that S-o-C 110 depicted and described with respect to FIG. 2 merely constitutes an example of a system-on-chip (i.e., S-o-C 110 may include various other components that may be configured in various other ways)”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 15, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chakraborty (US20090193306A1) in view of Kawasaki (US20100176838A1) .
Regarding Claim 5, Chakraborty teaches the limitations of Claim 1. Chakraborty does not explicitly disclose wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections. In the same field of endeavor, Kawasaki teaches wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections. (e.g. see [0069] “In the case of a multiple power-driven semiconductor device, power consumption may be unduly high if a power supply voltage of, for example, 1.2 V is uniformly applied to a chip even though the 1.2 V may not be necessary to perform a desired operation. Accordingly, a voltage lower than the power supply voltage, for example, 0.8 V is applied to circuit blocks capable of performing desired operation even at lower voltages, thereby achieving a low-power operation. In the multiple power-driven semiconductor device, different power supply voltages minimally necessary for the respective circuit blocks are applied thereto, in order to suppress the power consumption of the semiconductor device as a whole”).
It would have been obvious to one of ordinary skill in the art before the effective filling date to combine the plurality of EDT sections of Chakraborty with the multiple voltages of Kawasaki for the purpose of utilizing a multiple power driven semiconductor device with the advantage of utilizing different circuit block configurations to fit the testing needs of the user.
Regarding Claim 15, Chakraborty teaches the limitations of Claim 10. Chakraborty does not explicitly disclose wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of sections of EDT sections. In the same field of endeavor, Kawasaki teaches wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections. (e.g. see [0069] “In the case of a multiple power-driven semiconductor device, power consumption may be unduly high if a power supply voltage of, for example, 1.2 V is uniformly applied to a chip even though the 1.2 V may not be necessary to perform a desired operation. Accordingly, a voltage lower than the power supply voltage, for example, 0.8 V is applied to circuit blocks capable of performing desired operation even at lower voltages, thereby achieving a low-power operation. In the multiple power-driven semiconductor device, different power supply voltages minimally necessary for the respective circuit blocks are applied thereto, in order to suppress the power consumption of the semiconductor device as a whole”).
It would have been obvious to one of ordinary skill in the art before the effective filling date to combine the plurality of EDT sections of Chakraborty with the multiple voltages of Kawasaki for the purpose of utilizing a multiple power driven semiconductor device with the advantage of utilizing different circuit block configurations to fit the testing needs of the user.
Regarding Claim 25, Chakraborty teaches the limitations of Claim 20. Chakraborty does not explicitly disclose wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections. In the same field of endeavor, Kawasaki teaches wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections. (e.g. see [0069] “In the case of a multiple power-driven semiconductor device, power consumption may be unduly high if a power supply voltage of, for example, 1.2 V is uniformly applied to a chip even though the 1.2 V may not be necessary to perform a desired operation. Accordingly, a voltage lower than the power supply voltage, for example, 0.8 V is applied to circuit blocks capable of performing desired operation even at lower voltages, thereby achieving a low-power operation. In the multiple power-driven semiconductor device, different power supply voltages minimally necessary for the respective circuit blocks are applied thereto, in order to suppress the power consumption of the semiconductor device as a whole”).
It would have been obvious to one of ordinary skill in the art before the effective filling date to combine the plurality of EDT sections of Chakraborty with the multiple voltages of Kawasaki for the purpose of utilizing a multiple power driven semiconductor device with the advantage of utilizing different circuit block configurations to fit the testing needs of the user.
Claims 7-9, 17-19, and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Chakraborty (US20090193306A1) in view of Cote (US10476740B) .
Regarding Claim 7, Chakraborty teaches the limitations of Claim 1. Chakraborty does not explicitly disclose wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the plurality of EDT circuits. In the same field of endeavor, Cote teaches wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the plurality of EDT circuits (e.g. see [Col. 2 lines 43-49] “Adding to the complexity are physical implementation (layout) considerations. Connecting multiple cores to each I/O can lead to routing congestion. The I/Os can also be embedded inside cores when using flip-chip technology. So the connections for one core impact the design of other cores to which the signals have to be connected, or through which the scan connections flow,” and [Col. 3 lines 13-20] “A relatively recent trend in SOC design, referred to as tile-based layout, is adding further complexity and constraints to DFT architectures. In tile-based designs, virtually all logic and routing is done within the cores and not at the top level. The cores abut one another when integrated into the chip with connections flowing from one core to the next. Any connectivity between cores has to flow through cores that are between them,” and [Col. 3 lines 26-29] “When retargeting core-level patterns, limited chip-level I/O counts may be dealt with by increasing the number of core groups, as long as there are enough I/Os to drive at least each core individually”).
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to combine the EDT sections and circuits of Chakraborty with the circuit density embodiment of Cote for the purpose of reducing congestion with the advantage of enhanced efficiency of the circuit.
Regarding Claim 8, Chakraborty teaches the limitations of Claim 1. While Chakraborty does teach partitioning circuit blocks, Chakraborty does not explicitly teach wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum.
In the same field of endeavor, Cote teaches wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum (e.g. see [Col. 14 lines 5-20] “The multiplexing device 1000 can select which of two preceding nodes to connect to its output. It serves the same purpose as a Segment Insertion Bit (SIB) node does in the IJTAG standard. Such a node allows a portion of the network to be included in the network, or bypassed when inactive. This enables among others: 1) Improving efficiency by bypassing a portion of the network when not being used; 2) improving operational flexibility by allowing, for example, cores including the inactive part of the network to be powered down without breaking the operation of the active portion of the network; 3) bypassing, without disabling the entire network, a portion of the network when there is a manufacturing defect in that portion of the network; and 4) linking different width sections of the network, allowing the use of the full wider width when the smaller width section is bypassed”).
Examiner notes the prior art teaches portioning circuit blocks and gives rationales for doing so including power conservation, and bypassing certain areas in the circuit. Isolation clamps are well known in the art to serve these same functions. Therefore it would have been obvious to one of ordinary skill in the art, before the effective filling date, to combine the portioned circuit blocks of Chakraborty with the rationales of Cote for the purpose of directing data through specific routes within an integrated circuit with the advantage of power conservation and the creation of a specified route (See MPEP 2143(I)(C)).
Regarding Claim 9, Chakraborty teaches the limitations of Claim 1. Chakraborty does not explicitly disclose a decoder configured to decompress a plurality of channels that includes channels modified by the plurality of EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream.
In the same field of endeavor, Cote teaches a decoder configured to decompress a plurality of channels that includes channels modified by the plurality of EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream (e.g. see [Col 9. Line 36-49] “Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can reduce not only the amount of data stored on the tester but also the test time for a given test data bandwidth,” and [Col. 9 line 55-Col 10 line 2] “The EDT hardware features a continuous-flow decompressor. The EDT compression of test cubes is performed by treating the external test data as Boolean variables. Scan cells are conceptually filled with symbolic expressions that are linear functions of input variables injected into the decompressor. In the case of a decompressor comprising a ring generator and an associated phase shifter, a set of linear equations corresponding to scan cells whose values are specified may be used. A compressed pattern can be determined by solving the system of equations. If the compressed pattern determined as such is then scanned in through the decompressor, the bits that were specified by ATPG will be generated accordingly. Unspecified bits are set to pseudorandom values based on the decompressor architecture”).
It would have been obvious to one of ordinary skill in the art, before the effective filling date to combine the integrated circuit of Chakraborty with the decompressor of Cote for the purpose of expanding data in order to test multiple data strains at once which advantageously lessens the time needed to test data bandwidth.
Regarding Claim 17, Chakraborty teaches the limitations of Claim 10. Chakraborty does not explicitly disclose wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the EDT circuits.
In the same field of endeavor, Cote teaches wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the EDT circuits (e.g. see [Col. 2 lines 43-49] “Adding to the complexity are physical implementation (layout) considerations. Connecting multiple cores to each I/O can lead to routing congestion. The I/Os can also be embedded inside cores when using flip-chip technology. So the connections for one core impact the design of other cores to which the signals have to be connected, or through which the scan connections flow,” and [Col. 3 lines 13-20] “A relatively recent trend in SOC design, referred to as tile-based layout, is adding further complexity and constraints to DFT architectures. In tile-based designs, virtually all logic and routing is done within the cores and not at the top level. The cores abut one another when integrated into the chip with connections flowing from one core to the next. Any connectivity between cores has to flow through cores that are between them,” and [Col. 3 lines 26-29] “When retargeting core-level patterns, limited chip-level I/O counts may be dealt with by increasing the number of core groups, as long as there are enough I/Os to drive at least each core individually”).
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to combine the EDT sections and circuits of Chakraborty with the circuit density embodiment of Cote for the purpose of reducing congestion with the advantage of enhanced efficiency of the circuit.
Regarding Claim 18, Chakraborty teaches the limitations of Claim 10. While Chakraborty does teach partitioning circuit blocks, Chakraborty does not explicitly teach wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum.
In the same field of endeavor, Cote teaches wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum (e.g. see [Col. 14 lines 5-20] “The multiplexing device 1000 can select which of two preceding nodes to connect to its output. It serves the same purpose as a Segment Insertion Bit (SIB) node does in the IJTAG standard. Such a node allows a portion of the network to be included in the network, or bypassed when inactive. This enables among others: 1) Improving efficiency by bypassing a portion of the network when not being used; 2) improving operational flexibility by allowing, for example, cores including the inactive part of the network to be powered down without breaking the operation of the active portion of the network; 3) bypassing, without disabling the entire network, a portion of the network when there is a manufacturing defect in that portion of the network; and 4) linking different width sections of the network, allowing the use of the full wider width when the smaller width section is bypassed”).
Examiner notes the prior art teaches portioning circuit blocks and gives rationales for doing so including power conservation, and bypassing certain areas in the circuit. Isolation clamps are well known in the art to serve these same functions. Therefore it would have been obvious to one of ordinary skill in the art, before the effective filling date, to combine the portioned circuit blocks of Chakraborty with the rationales of Cote for the purpose of directing data through specific routes within an integrated circuit with the advantage of power conservation and the creation of a specified route (See MPEP 2143(I)(C)).
Regarding Claim 19, Chakraborty teaches the limitations of Claim 10. Chakraborty does not explicitly disclose decompressing a plurality of channels that include channels modified by the EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream.
In the same field of endeavor, Cote teaches decompressing a plurality of channels that include channels modified by the EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream. (e.g. see [Col 9. Line 36-49] “Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can reduce not only the amount of data stored on the tester but also the test time for a given test data bandwidth,” and [Col. 9 line 55-Col 10 line 2] “The EDT hardware features a continuous-flow decompressor. The EDT compression of test cubes is performed by treating the external test data as Boolean variables. Scan cells are conceptually filled with symbolic expressions that are linear functions of input variables injected into the decompressor. In the case of a decompressor comprising a ring generator and an associated phase shifter, a set of linear equations corresponding to scan cells whose values are specified may be used. A compressed pattern can be determined by solving the system of equations. If the compressed pattern determined as such is then scanned in through the decompressor, the bits that were specified by ATPG will be generated accordingly. Unspecified bits are set to pseudorandom values based on the decompressor architecture”).
It would have been obvious to one of ordinary skill in the art, before the effective filling date to combine the integrated circuit of Chakraborty with the decompressor of Cote for the purpose of expanding data in order to test multiple data strains at once which advantageously lessens the time needed to test data bandwidth.
Regarding Claim 27, Chakraborty teaches the limitations of Claim 20. Chakraborty does not explicitly disclose wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the EDT circuits.
In the same field of endeavor, Cote teaches wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the EDT circuits (e.g. see [Col. 2 lines 43-49] “Adding to the complexity are physical implementation (layout) considerations. Connecting multiple cores to each I/O can lead to routing congestion. The I/Os can also be embedded inside cores when using flip-chip technology. So the connections for one core impact the design of other cores to which the signals have to be connected, or through which the scan connections flow,” and [Col. 3 lines 13-20] “A relatively recent trend in SOC design, referred to as tile-based layout, is adding further complexity and constraints to DFT architectures. In tile-based designs, virtually all logic and routing is done within the cores and not at the top level. The cores abut one another when integrated into the chip with connections flowing from one core to the next. Any connectivity between cores has to flow through cores that are between them,” and [Col. 3 lines 26-29] “When retargeting core-level patterns, limited chip-level I/O counts may be dealt with by increasing the number of core groups, as long as there are enough I/Os to drive at least each core individually”).
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to combine the EDT sections and circuits of Chakraborty with the circuit density embodiment of Cote for the purpose of reducing congestion with the advantage of enhanced efficiency of the circuit.
Regarding Claim 28, Chakraborty teaches the limitations of Claim 20. While Chakraborty does teach partitioning circuit blocks, Chakraborty does not explicitly teach wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum.
In the same field of endeavor, Cote teaches wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum (e.g. see [Col. 14 lines 5-20] “The multiplexing device 1000 can select which of two preceding nodes to connect to its output. It serves the same purpose as a Segment Insertion Bit (SIB) node does in the IJTAG standard. Such a node allows a portion of the network to be included in the network, or bypassed when inactive. This enables among others: 1) Improving efficiency by bypassing a portion of the network when not being used; 2) improving operational flexibility by allowing, for example, cores including the inactive part of the network to be powered down without breaking the operation of the active portion of the network; 3) bypassing, without disabling the entire network, a portion of the network when there is a manufacturing defect in that portion of the network; and 4) linking different width sections of the network, allowing the use of the full wider width when the smaller width section is bypassed”).
Examiner notes the prior art teaches portioning circuit blocks and gives rationales for doing so including power conservation, and bypassing certain areas in the circuit. Isolation clamps are well known in the art to serve these same functions. Therefore it would have been obvious to one of ordinary skill in the art, before the effective filling date, to combine the portioned circuit blocks of Chakraborty with the rationales of Cote for the purpose of directing data through specific routes within an integrated circuit with the advantage of power conservation and the creation of a specified route (See MPEP 2143(I)(C)).
Regarding Claim 29, Chakraborty teaches the limitations of Claim 20. Chakraborty does not explicitly disclose means for decompressing a plurality of channels that include channels modified by the EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream.
In the same field of endeavor, Cote teaches means for decompressing a plurality of channels that include channels modified by the EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream. (e.g. see [Col 9. Line 36-49] “Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can reduce not only the amount of data stored on the tester but also the test time for a given test data bandwidth,” and [Col. 9 line 55-Col 10 line 2] “The EDT hardware features a continuous-flow decompressor. The EDT compression of test cubes is performed by treating the external test data as Boolean variables. Scan cells are conceptually filled with symbolic expressions that are linear functions of input variables injected into the decompressor. In the case of a decompressor comprising a ring generator and an associated phase shifter, a set of linear equations corresponding to scan cells whose values are specified may be used. A compressed pattern can be determined by solving the system of equations. If the compressed pattern determined as such is then scanned in through the decompressor, the bits that were specified by ATPG will be generated accordingly. Unspecified bits are set to pseudorandom values based on the decompressor architecture”).
It would have been obvious to one of ordinary skill in the art, before the effective filling date to combine the integrated circuit of Chakraborty with the decompressor of Cote for the purpose of expanding data in order to test multiple data strains at once which advantageously lessens the time needed to test data bandwidth.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US2016259000A1 teaches, in part, digital circuitry implemented in an integrated circuit can be complex, and may include specialized circuitry that supports testing of various devices on the fabricated chip. For example, a system-on-a-chip (SoC) may include a central processing unit (CPU), which may be a multi-core processor with multiple processor cores, in addition to various digital or analog devices that provide a variety of functionality used by, or operating alongside, the CPU.
US5592993A teaches, in part, scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit).
US2010293423 A1 teaches, in part, a method including receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host where the plurality of target ICE controllers are associated with a plurality of components of the target hardware, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and propagating the scheduled set of scan segment operations toward a processor configured for executing the scheduled set of scan segment operations for testing one or one or more components of the target hardware.
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/NYLA GAVIA/ Examiner, Art Unit 2863
/Catherine T. Rastovski/ Supervisory Primary Examiner, Art Unit 2863