Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 1 indicates the logic is coupled to the processor, but Figure 13 shows it coupled to the AI accelerator 296, not the processor 282. Therefore, either Figure 13 should be changed so the logic is coupled to the processor instead of the AI Accelerator, or the claim should be updated to include the logic coupled to the AI Accelerator as shown in Figure 13. No new matter should be entered.
The drawings are also objected to under 37 CFR 1.84(o). Regarding Figure 13, 280 does not have a suitable legend. The Examiner suggests using the legend “Computing System”, per [0051] of the Specification. Regarding Figure 14, 350 does not have a suitable legend. The Examiner suggests using the label “Semiconductor Apparatus”, per [0054] of the Specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3, 11 and 20 are objected to because of the following informalities: on line 3, "based on most significant bits" should read "based on. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 9, 13-14, 17-18 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Espressif Systems, ESP32 Data Sheet, hereinafter ESP32, in view of Kraemer et al. (US 11,977,936), hereinafter Kraemer, and further in view of Allen et al., CMOS Analog Circuit Design, Chapter 2, “The MOS Transistor”, hereinafter Allen.
Regarding claim 1, ESP32 discloses a computing system comprising: a network controller (Figure 1, Wi-Fi MAC); and a processor coupled to the network controller (Figure 1, Core). ESP32 does not disclose logic including a differential signal path.
Kraemer discloses logic including a differential signal path to: conduct signed multiply-accumulate (MAC) operations on first analog signals and multibit weight data stored in the differential signal path (Figure 7B), and output second analog signals based on the signed MAC operations (Figure 7B). The ESP32 and Kraemer are considered analogous art because they are in the same field of endeavor of low-power computing. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified an ESP32 to include the multiply-accumulator disclosed by Kraemer because demand for artificial intelligence software applications has created a need for scalable hardware multiplier-accumulators for acceleration of software algorithms used in machine learning (Column 1, rows 16-19), and “[a] differential unit element provides greater isolation from disturbances from the supply voltage, as it tends to be self-cancelling as present on both inputs of the combining ADC” (Column 9, rows 23-25).
The combination of ESP32 and Kraemer does not disclose logic coupled to substrates. Allen discloses logic coupled to one or more substrates (Figure 2.3-1). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the transistor designed as disclosed by Allen to the ESP32 modified by Kraemer because CMOS has been the dominant technology for VLSI design since the 1980s (p. 18, ¶ 1).
Regarding claim 5, Kraemer discloses the computing system of claim 1, wherein the differential signal path is to bypass a remapping of the multibit weight data (Figure 7B lacks a remapping step).
Regarding claim 6, Kraemer discloses the computing system of claim 1, wherein the differential signal path is to bypass a calibration of the first analog signals and the second analog signals (Figure 7B lacks a calibration step).
Regarding claim 9, Allen discloses a semiconductor apparatus comprising: one or more substrates (Figure 2.3-1); and otherwise corresponds to computing system claim 1, and is rejected for the same reasons.
Regarding claims 13 and 14, they are semiconductor apparatus claims that correspond to computing system claims 5 and 6, and are rejected for the same reasons.
Regarding claim 17, Allen discloses the semiconductor apparatus of claim 9, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates (Figure 2.3-1).
Regarding claims 18 and 22-23, they are method claims that correspond to computing system claims 1 and 5-6, respectively, and are rejected for the same reasons.
Claims 2, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of ESP32, Kraemer and Allen as applied to claims 1, 9 and 18, respectively, above, and further in view of Nieh, “Recitation 3 - Signed Number Binary Represenation [sic] Supplement”.
Regarding claim 2, the combination of ESP32, Kraemer and Allen does not disclose the format the weight data is stored in. Nieh discloses the storing of numbers in a signed magnitude format (pp. 1-2). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use a signed magnitude format as disclosed by Nieh to the system disclosed by the combination of ESP32, Kraemer and Allen because applying the known technique of the signed magnitude format to storing of integers yields the predictable result of allowing the representation of negative numbers.
Regarding claim 10, it is a semiconductor apparatus claim that corresponds to computing system claim 2, and is rejected for the same reasons.
Regarding claim 19, it is a method claim that corresponds to computing system claim 2, and is rejected for the same reasons.
Claims 7, 15 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of ESP32, Kraemer and Allen as applied to claims 1, 9 and 18, respectively, above, and further in view of Razavi, “The Current-Steering DAC [A Circuit for All Seasons]”.
Regarding claim 7, ESP32 discloses the computing system of claim 1, wherein the logic further includes a plurality of digital to analog converters (DACs) coupled to the differential signal path (4.5 Digital-to-Analog Converter (DAC)), but the combination of ESP32, Kraemer and Allen does not disclose the DACs being used to generate analog signals or the kind of DACs used.
Razavi discloses using the DACs to generate the first analog signals based on digital activation signals (Figure 2, D1 through DN), and wherein the plurality of DACs include one or more of current steering DACs or differential resistive DACs (Figure 2). It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to use the DACs disclosed by Razavi to the system disclosed by the combination of ESP32, Kraemer and Allen because using current steering suppresses voltage fluctuations caused by parasitic inductances (p. 1, ¶ 4-5).
Regarding claim 10, it is a semiconductor apparatus claim that corresponds to computing system claim 2, and is rejected for the same reasons.
Regarding claim 19, it is a method claim that corresponds to computing system claim 2, and is rejected for the same reasons.
Claims 8, 16 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of ESP32, Kraemer and Allen as applied to claims 1, 9 and 18, respectively, above, and further in view of Alpman et al., “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS”, hereinafter Alpman.
Regarding claim 8, the combination of ESP32, Kraemer and Allen does not disclose a plurality of ADCs, or the kind of ADCs used.
Alpman discloses the computing system of claim 1, wherein the logic further includes a plurality of analog to digital converters (ADCs) coupled to the differential signal path (Alpman, Figure 4.2.7), Kraemer discloses the plurality of ADCs to generate digital accumulation signals based on the second analog signals (Kraemer, Figure 4A, 414), and Alpman discloses the plurality of ADCs include differential successive approximation register converters (Figure 4.2.1).
Regarding claim 10, it is a semiconductor apparatus claim that corresponds to computing system claim 2, and is rejected for the same reasons.
Regarding claim 19, it is a method claim that corresponds to computing system claim 2, and is rejected for the same reasons.
Allowable Subject Matter
Claims 3-4, 11-12 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claims 3-4, the prior art of record does not teach or suggest a combination as claimed including “the differential signal path includes butterfly switch circuitry to steer the second analog signals between a positive voltage and a negative voltage based on most significant bits in the multibit weight data” (emphasis added). Yang et al. (US 11,948,659) discloses the use of a butterfly switch or transmission gate (Figure 1), but it is used for the MAC operation itself, not determining the sign based on the most significant bits. Vorbach (US 11,797,474) discloses a transmission gate used for triggers (Figure 26A, 2603, 2604), but does not disclose using it for determining the sign based on the most significant bits of the inputs. Claim 4 would be allowable by virtue of its dependency on claim 3.
Regarding claim 11-12, they are semiconductor apparatus claims that correspond to computing system claim 3-4, respectively, and would be allowable for the same reasons.
Regarding claim 20-21, they are method claims that correspond to computing system claim 3-4, respectively, and would be allowable for the same reasons.
Discussion of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yoshida (US 2022/0137926) discloses a differential multiply-accumulate compute-in-memory device (Figure 5), but does not disclose the operation being done with signed numbers. Naous et al. (US 2023/0376273) discloses using butterfly switches for multiply-accumulators (Figure 6), but the operation is done via Booth encoders.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew Strapp whose telephone number is (571)272-9343. The examiner can normally be reached Monday-Friday 8:00 AM-4:00 PM.
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/M.S./
Matthew StrappExaminer, Art Unit 2182
(571)272-9343
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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