DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
No Claims have been amended. No Claims have been added or cancelled. Claims 1-20 remain pending and are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-8, 10-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Greathouse et al. (US Publication No. 2023/0132931 -- "Greathouse") in view of Faith et al. (US Patent No. 10,114,751 -- "Faith") in further view of Durnov et al. (US Publication No. 2019/0272104 -- "Durnov") in further view of Gupta et al. (US Publication No. 2022/0188235 – “Gupta”).
Regarding claim 8, Greathouse teaches A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising: (Greathouse paragraph [0030], During DMA, the one or more processor cores 308 queue DMA commands in the DMA buffer(s) 316 and can signal their presence to the DMA engines 314. For example, in some embodiments, an application program running on the system 300 prepares an appropriate chain of descriptors in memory accessible to the DMA engine (e.g., DMA buffers 316) to initiate a chain of DMA data transfers. The processor cores 308 then sends a message (or other notification) to the DMA engine 314 indicating the memory address of the first descriptor in the chain, which is a request to the DMA engine to start execution of the descriptors. The computer program may be implemented via processor to execute the instructions of the particular memory system) identifying a cache probe event associated with a cache memory system; (Greathouse paragraph [0041], In addition to independently fetching the same DMA job description from the same location (i.e., DMA buffer 416), each of the DMA engines 414A and 414B also independently determine a portion of data transfer requested by the DMA transfer command to perform. In one embodiment, DMA engines 414A and 414B each issue speculative DMA transfers by broadcasting a cache probe request 422 (e.g., a read and/or a write probe) to the cache memory 410 and main memory (e.g., memory module 412) of their respective chiplets 404. In response to the cache probe requests, the cache memory 410 and main memory of each chiplet 404 will return one or more return responses to the requesting DMA engine. For example, for a DMA read probe, the cache memories 410 can return a cache hit or a cache miss to indicate whether the requested data is found within cache memory 410. A cache probe is sent to a cache memory system via a read/write probe) determining a cache size adjustment impact based upon, at least in part, a change in a hit rate associated with the cache memory system; (Greathouse paragraph [0041], In addition to independently fetching the same DMA job description from the same location (i.e., DMA buffer 416), each of the DMA engines 414A and 414B also independently determine a portion of data transfer requested by the DMA transfer command to perform. In one embodiment, DMA engines 414A and 414B each issue speculative DMA transfers by broadcasting a cache probe request 422 (e.g., a read and/or a write probe) to the cache memory 410 and main memory (e.g., memory module 412) of their respective chiplets 404. In response to the cache probe requests, the cache memory 410 and main memory of each chiplet 404 will return one or more return responses to the requesting DMA engine. For example, for a DMA read probe, the cache memories 410 can return a cache hit or a cache miss to indicate whether the requested data is found within cache memory 410. The memory module may be analyzed to determine the impact of the cache probe on the cache hit/miss data returns, see Greathouse paragraph [0042], As illustrated in FIG. 4, the retrieved DMA job description 420 is a single transfer command to read data from physical addresses X and Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 (e.g., L3 or some last level cache) of the first graphics processing stacked die chiplet 404A, the DMA engine 414A broadcasts a cache probe request 422 to the cache memory 410 (including cache controllers [not shown]) before memory modules 412 and receives one or more return responses indicating a cache hit for address X and a cache miss for address Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 of the second graphics processing stacked die chiplet 404B, the DMA engine 414B similarly broadcasts the cache probe request 422 to the cache memory 410 and receives one or more return responses indicating a cache miss for address X and a cache miss for address Y).
Greathouse does not teach in response to identifying the cache probe event, processing a hit rate associated with each cache in the cache memory system; maintaining a listing of cache histogram or other data structure defining a plurality of cache memory system metrics for each of the caches in the cache memory system including a percentage of zero cache hit rate value; adjusting a cache size of the cache memory system based upon, at least in part, the cache probe event; and determining whether to further adjust the cache size of the cache memory system based upon, at least in part, the cache size adjustment impact; wherein adjusting the cache size of the cache memory system includes identifying and selecting a cache in the cache memory system with the percentage of zero cache hit rate value being above a predefined threshold and removing a portion of storage capacity from the cache memory system; and determining a change in IO pattern associated with the cache size adjustment impact, and, in response to determining the change, adjusting the cache size by rolling back the portion of storage capacity previously removed from the cache memory system.
However, Faith teaches in response to identifying the cache probe event, processing a hit rate associated with each cache in the cache memory system; maintaining a listing of cache histogram or other data structure defining a plurality of cache memory system metrics for each of the caches in the cache memory system (Faith column 1; lines 45-55, Miss Rate Curves (MRC) have been generated to attempt to address this problem, by tracking or estimating cache usage to attempt to determine the miss rates for a given cache size. The problem is that conventional MRC algorithms require large amounts of memory to keep track of how the cache is being used. For example, estimating cache hit ratios (the cache hit ratio is one minus the cache miss ratio) given a particular cache size traditionally demands prohibitive memory consumption requirements. The cache probe may contain a hit/miss rate for each cache size, and can be stored recorded in storage, see Faith column 10; lines 15-18, At 508, the value of the miss counter is divided by the sum of the miss and hit counter values for the HLL. The result of the division corresponds to the MRC value for the HLL. At 510, the MRC data is recorded for the size of the HLL) adjusting a cache size of the cache memory system based upon, at least in part, the cache probe event; (Faith column 4; lines 27-33, The HLL is able to perform this type of functionality in a very memory efficient way. Only a very small amount of memory is needed to implement a HLL that can represent an extremely large number of unique values. This permits the inventive approach to use very memory efficient HLL structures that can represent a large number of different cache sizes with great efficiency and effectiveness. The cache size can be adjusted based on the cache probe and associated hit/miss rate, also see Faith column 4; lines 40-46, FIG. 1B shows a high-level flowchart of some embodiments of the invention. At 180, a set of different cache sizes are selected for analysis. This list of sizes represents the set of cache sizes for which it is desired to identify MRC values, and therefore represents possible expectant cache sizes to implement for the system) and determining whether to further adjust the cache size of the cache memory system based upon, at least in part, the cache size adjustment impact (Faith column 5, lines 25-34, At 236, a determination is made whether the current size is the last size in the list. If so, then the initialization process ends at 240. However, if there are additional cache sizes that need to be initialized for the HLLs, then the process proceeds to 238 to make the current size be the next size in the list. The process then loops through the above actions to initialize the HLL for this current size. This continues until all sizes from the list have been initialized. The cache current size can be monitored for hit/miss rate, and further adjusted based on the impact (i.e., the new hit/miss rate)) wherein adjusting the cache size of the cache memory system includes identifying and selecting a cache in the cache memory system with the percentage of zero cache hit rate value being above a predefined threshold and removing a portion of storage capacity from the cache memory system (Faith column 5, lines 40-51, At 370, a HLL from the set of HLLs is selected for processing. For example, assuming that four HLLs have been initialized to represent four different cache sizes (e.g., for 8, 16, 32, and 64 GByte cache sizes), then one of these HLLs is selected at 370 (e.g., the first HLL for the first size in the list if this is the first time through the processing loop). At 372, the data item for the I/O is added to the HLL. A determination is made at 374 whether cache hit/miss processing should be performed, or whether the processing should just skip to the next HLL at this point. For example, analysis can be made upon the “reset” status of the HLL to determine whether processing should skip to the next HLL. The adjusting of cache size can be performed based on the cache probe, and can have the cache size shrunk (i.e., smaller cache size) based on said result).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse with those of Faith. Faith is added to explicitly teach the concept of using different cache sizes as a means to improve the function of the cache memory system. The concept of using a cache probe including hit/miss data to improve the cache function through different cache sizes would have been obvious to add to the teachings of Greathouse (Faith column 10; lines 39-50, The MRC values can be organized and analyzed in any suitable way. For example, as illustrated in FIG. 7, the MRC values can be graphed to their cache size values. This helps to identify the relative costs and benefits of the different cache sizes, particularly as they pertain to the miss rates. A specific cache value can then be selected to optimize the size of the cache relative to a desired miss rate level. In the example of FIG. 7, one might wish to choose 32 as the cache size that is large enough to provide significant performance benefits, without requiring excessive allocation of cache storage).
Greathouse in view of Faith does not teach including a percentage of zero cache hit rate value; selecting a cache in the cache memory system with the percentage of zero cache hit rate value being above a predefined threshold; and determining a change in IO pattern associated with the cache size adjustment impact, and, in response to determining the change, adjusting the cache size by rolling back the portion of storage capacity previously removed from the cache memory system.
However, Durnov teaches including a percentage of zero cache hit rate value; selecting a cache in the cache memory system with the percentage of zero cache hit rate value being above a predefined threshold (Durnov paragraph [0027], Such a 100% cache miss rate is indicative that the entirety of the initial portion of the target data (e.g., one or more pages but fewer than all pages of the memory page group A 116a ) copied during the learning sequence phase (or a data store analysis phase) is not stored in the cache 112. In the above two examples, the cache miss rate threshold is set to a value greater than zero and less than 100%. As such, the cache miss rate of zero for the memory page group A 116a is less than the cache miss rate threshold. The cache zero hit rate may be compared to a threshold value for determination).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse and Faith with those of Durnov. The teachings of Durnov explicitly disclose the concept of using a zero-cache hit rate (i.e., a complete or 100% cache miss) as a means of evaluating the cache performance. Using a zero-cache hit rate would have been obvious to provide more explicit indication of a cache not effectively using the available space (Durnov paragraph [0027], Such a zero cache miss rate is indicative that the entirety of the initial portion of the target data (e.g., one or more pages but fewer than all pages of the memory page group A 116a ) copied during the learning sequence phase (or a data store analysis phase) is stored in the cache 112. As another example, a memory copy request from the program 108 and/or the OS 106 that identifies the target data as the memory page group C 116c would result in selection of a type of memory copy operation that does not use the cache 112 to perform the copying of the memory page group C 116c. That is, since the entirety of the memory page group C 116c is not stored in the cache 112 in the illustrated example of FIG. 1 and must be accessed from the memory 104, the cache miss rate determined during the learning sequence phase (or a data store analysis phase) would be 100% (or all data reads resulted in cache miss events). Such a 100% cache miss rate is indicative that the entirety of the initial portion of the target data (e.g., one or more pages but fewer than all pages of the memory page group A 116a ) copied during the learning sequence phase (or a data store analysis phase) is not stored in the cache 112. In the above two examples, the cache miss rate threshold is set to a value greater than zero and less than 100%. As such, the cache miss rate of zero for the memory page group A 116a is less than the cache miss rate threshold, resulting in selection of a type of memory copy operation that uses the cache 112 to perform the copying of the remaining portion of the memory page group A 116a during a main body copy phase).
Greathouse in view of Faith in further view of Durnov does not teach determining a change in IO pattern associated with the cache size adjustment impact, and, in response to determining the change, adjusting the cache size by rolling back the portion of storage capacity previously removed from the cache memory system.
However, Gupta teaches determining a change in IO pattern associated with the cache size adjustment impact, (Gupta paragraph [0044], In an embodiment, the cache optimization module 400 may include one or more of an initialization module 402, a read hit ratio calculation module 404, a read hit ratio comparison module 406, a partition size adjustment module 408, and a partition size verification module 410. In an embodiment, the initialization module 402 includes logic and functionality to initialize cache partitions 304b in the lower performance portion 218b of the cache memory. The initialization module also initializes the cache partition statistics 330b for each of the cache partitions 304b including resetting the read hit counter 332b, the read access counter 334b, and the read hit ratio 336b, and setting the minimum 340b, maximum 342b, and current 344b partition sizes. The size change is monitored with respect to the IO pattern, including elements such as read hit counter, ratio, etc.) and, in response to determining the change, adjusting the cache size by rolling back the portion of storage capacity previously removed from the cache memory system (Gupta paragraph [0052], In certain embodiments, the partition size decrease of each cache partition 304b having a read hit ratio 336b less than the average read hit ratio can be adjusted equally such that the adjusted sum of partition size decreases balances with the smaller sum of partition size increases. In certain embodiments, the partition size decrease of each cache partition 304b having a read hit ratio 336b less than the average read hit ratio can be adjusted proportionally such that the adjusted sum of partition size decreases balances with the smaller sum of partition size increases. As in the previous example, if two cache partitions 304b yield a sum of partition size decreases of 200 GB that exceeds the sum of cache partition size increases by 20 GB, then a cache management policy can reduce the partition size decreases for each partition 304b by 10 GB. In the alternative, the cache management policy can also reduce the partition size decrease for each cache partition 304b in proportion to the comparative current partition sizes 344b of the cache partitions 304b. In an embodiment, the method 600 then proceeds to step 640. The size of the cache can be dynamically decreased for a given cache partition resulting in adding back memory space when an adjustment is required).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse and Faith and Durnov with those of Gupta. Gupta teaches using a dynamic I/O pattern to determine cache performance and can adjust the cache size based on said determination, which allows for improvement of the memory system by optimizing cache size (see Gupta paragraph [0055], As stated previously, cache management methods and systems improve the performance of storage systems by maintaining highly accessed data tracks in the cache memory 218, and reducing the time to read the requested data. Thus, increasing the size of the cache memory 218 by using less expensive flash memory, or SCM 218b, is an important element of an effective cache memory management policy. The present invention focuses on reserving segments of the SCM, or cache partitions 304b, for specific types of data or data used for specific purposes or with specific software applications. The present invention describes cache management policies that dynamically adjust the size of the cache partitions 304b to optimize the cache memory system and improve the performance of the storage system).
Claims 1 and 15 are the corresponding method and system claims to the non-transitory computer-readable medium claim 8. They are rejected with the same references and rationale.
Regarding claim 10, Greathouse in view of Faith in further view of Durnov and further in view of Gupta teaches The computer program product of claim 8, wherein the cache probe event includes one or more of: a change in IO pattern, a change in cache memory system metrics, and a periodic cycle (Greathouse paragraph [0041], In addition to independently fetching the same DMA job description from the same location (i.e., DMA buffer 416), each of the DMA engines 414A and 414B also independently determine a portion of data transfer requested by the DMA transfer command to perform. In one embodiment, DMA engines 414A and 414B each issue speculative DMA transfers by broadcasting a cache probe request 422 (e.g., a read and/or a write probe) to the cache memory 410 and main memory (e.g., memory module 412) of their respective chiplets 404. In response to the cache probe requests, the cache memory 410 and main memory of each chiplet 404 will return one or more return responses to the requesting DMA engine. For example, for a DMA read probe, the cache memories 410 can return a cache hit or a cache miss to indicate whether the requested data is found within cache memory 410. The cache probe may be sent as a read/write probe which will change the pattern of I/O responses for the cache and memory system).
Claims 3 and 17 are the corresponding method and system claims to the non-transitory computer-readable medium claim 10. They are rejected with the same references and rationale.
Regarding claim 11, Greathouse in view of Faith in further view of Durnov and further in view of Gupta teaches The computer program product of claim 8, wherein adjusting the cache size of the cache memory system includes adding a portion of storage capacity to the cache memory system (Faith column 4; lines 27-33, The HLL is able to perform this type of functionality in a very memory efficient way. Only a very small amount of memory is needed to implement a HLL that can represent an extremely large number of unique values. This permits the inventive approach to use very memory efficient HLL structures that can represent a large number of different cache sizes with great efficiency and effectiveness. The cache size can be increased or decreased based on the cache probe and associated hit/miss rate, also see Faith column 4; lines 40-46, FIG. 1B shows a high-level flowchart of some embodiments of the invention. At 180, a set of different cache sizes are selected for analysis. This list of sizes represents the set of cache sizes for which it is desired to identify MRC values, and therefore represents possible expectant cache sizes to implement for the system).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse with those of Faith. Faith is added to explicitly teach the concept of using different cache sizes as a means to improve the function of the cache memory system. The concept of using a cache probe including hit/miss data to improve the cache function through different cache sizes would have been obvious to add to the teachings of Greathouse (Faith column 10; lines 39-50, The MRC values can be organized and analyzed in any suitable way. For example, as illustrated in FIG. 7, the MRC values can be graphed to their cache size values. This helps to identify the relative costs and benefits of the different cache sizes, particularly as they pertain to the miss rates. A specific cache value can then be selected to optimize the size of the cache relative to a desired miss rate level. In the example of FIG. 7, one might wish to choose 32 as the cache size that is large enough to provide significant performance benefits, without requiring excessive allocation of cache storage).
Claims 4 and 18 are the corresponding method and system claims to the non-transitory computer-readable medium claim 11. They are rejected with the same references and rationale.
Regarding claim 12, Greathouse in view of Faith in further view of Durnov and further in view of Gupta teaches The computer program product of claim 11, wherein determining the cache size adjustment impact includes comparing a hit rate associated with the cache memory system prior to adjusting the cache size to a hit rate associated with the cache memory system after adjusting the cache size (Greathouse paragraphs [0042-0043], As illustrated in FIG. 4, the retrieved DMA job description 420 is a single transfer command to read data from physical addresses X and Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 (e.g., L3 or some last level cache) of the first graphics processing stacked die chiplet 404A, the DMA engine 414A broadcasts a cache probe request 422 to the cache memory 410 (including cache controllers [not shown]) before memory modules 412 and receives one or more return responses indicating a cache hit for address X and a cache miss for address Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 of the second graphics processing stacked die chiplet 404B, the DMA engine 414B similarly broadcasts the cache probe request 422 to the cache memory 410 and receives one or more return responses indicating a cache miss for address X and a cache miss for address Y. In various embodiments, probes include messages passed from a coherency point (e.g., at the DMA engine 414) to one or more caches in the computer system to request a response indicating whether the caches have a copy of a block of data and, in some implementations, to indicate a cache state into which the cache should place the block of data. In some implementations, if a DMA engine 414 receives a memory request targeting its corresponding memory controller (e.g., a memory request for data stored at an address or a region of addresses in a memory controlled by the memory controller), the DMA engine 414 performs a lookup (e.g., a tag-based lookup) to its corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of any of the cache subsystems. The cache hit rate (and associated miss rate) can be impacted by the cache probe results and the newly allocated cache regions and cache lines and is therefore tracked with the cache probe).
Claims 5 and 19 are the corresponding method and system claims to the non-transitory computer-readable medium claim 12. They are rejected with the same references and rationale.
Regarding claim 13, Greathouse in view of Faith in further view of Durnov and further in view of Gupta teaches The computer program product of claim 11, wherein determining whether to further adjust the cache size of the cache memory system includes: determining that the hit rate associated with the cache memory has decreased in response to removing a portion of storage capacity from the cache memory system; (Greathouse paragraphs [0042-0043], As illustrated in FIG. 4, the retrieved DMA job description 420 is a single transfer command to read data from physical addresses X and Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 (e.g., L3 or some last level cache) of the first graphics processing stacked die chiplet 404A, the DMA engine 414A broadcasts a cache probe request 422 to the cache memory 410 (including cache controllers [not shown]) before memory modules 412 and receives one or more return responses indicating a cache hit for address X and a cache miss for address Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 of the second graphics processing stacked die chiplet 404B, the DMA engine 414B similarly broadcasts the cache probe request 422 to the cache memory 410 and receives one or more return responses indicating a cache miss for address X and a cache miss for address Y. In various embodiments, probes include messages passed from a coherency point (e.g., at the DMA engine 414) to one or more caches in the computer system to request a response indicating whether the caches have a copy of a block of data and, in some implementations, to indicate a cache state into which the cache should place the block of data. In some implementations, if a DMA engine 414 receives a memory request targeting its corresponding memory controller (e.g., a memory request for data stored at an address or a region of addresses in a memory controlled by the memory controller), the DMA engine 414 performs a lookup (e.g., a tag-based lookup) to its corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of any of the cache subsystems. The cache hit rate (and associated miss rate) can be impacted (i.e., increased or decreased) by the cache probe results and the newly allocated cache regions and cache lines and is therefore tracked with the cache probe) and adjusting the cache size by adding the portion of storage capacity previously removed from the cache memory system (Faith column 4; lines 27-33, The HLL is able to perform this type of functionality in a very memory efficient way. Only a very small amount of memory is needed to implement a HLL that can represent an extremely large number of unique values. This permits the inventive approach to use very memory efficient HLL structures that can represent a large number of different cache sizes with great efficiency and effectiveness. The cache size can be adjusted based on the cache probe and associated hit/miss rate, also see Faith column 4; lines 40-46, FIG. 1B shows a high-level flowchart of some embodiments of the invention. At 180, a set of different cache sizes are selected for analysis. This list of sizes represents the set of cache sizes for which it is desired to identify MRC values, and therefore represents possible expectant cache sizes to implement for the system).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse with those of Faith. Faith is added to explicitly teach the concept of using different cache sizes as a means to improve the function of the cache memory system. The concept of using a cache probe including hit/miss data to improve the cache function through different cache sizes would have been obvious to add to the teachings of Greathouse (Faith column 10; lines 39-50, The MRC values can be organized and analyzed in any suitable way. For example, as illustrated in FIG. 7, the MRC values can be graphed to their cache size values. This helps to identify the relative costs and benefits of the different cache sizes, particularly as they pertain to the miss rates. A specific cache value can then be selected to optimize the size of the cache relative to a desired miss rate level. In the example of FIG. 7, one might wish to choose 32 as the cache size that is large enough to provide significant performance benefits, without requiring excessive allocation of cache storage).
Claims 20 are the corresponding system claim to the non-transitory computer-readable medium claim 13. It is rejected with the same references and rationale.
Regarding claim 14, Greathouse in view of Faith in further view of Durnov and further in view of Gupta teaches The computer program product of claim 11, wherein determining whether to further adjust the cache size of the cache memory system includes: determining that the hit rate associated with the cache memory has not changed in response to adding a portion of storage capacity to the cache memory system; (Greathouse paragraphs [0042-0043], As illustrated in FIG. 4, the retrieved DMA job description 420 is a single transfer command to read data from physical addresses X and Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 (e.g., L3 or some last level cache) of the first graphics processing stacked die chiplet 404A, the DMA engine 414A broadcasts a cache probe request 422 to the cache memory 410 (including cache controllers [not shown]) before memory modules 412 and receives one or more return responses indicating a cache hit for address X and a cache miss for address Y. To determine whether some of the data associated with addresses X and Y is currently residing in cache memory 410 of the second graphics processing stacked die chiplet 404B, the DMA engine 414B similarly broadcasts the cache probe request 422 to the cache memory 410 and receives one or more return responses indicating a cache miss for address X and a cache miss for address Y. In various embodiments, probes include messages passed from a coherency point (e.g., at the DMA engine 414) to one or more caches in the computer system to request a response indicating whether the caches have a copy of a block of data and, in some implementations, to indicate a cache state into which the cache should place the block of data. In some implementations, if a DMA engine 414 receives a memory request targeting its corresponding memory controller (e.g., a memory request for data stored at an address or a region of addresses in a memory controlled by the memory controller), the DMA engine 414 performs a lookup (e.g., a tag-based lookup) to its corresponding cache directory to determine whether the request targets a memory address or region cached in at least one cache line of any of the cache subsystems. The cache hit rate (and associated miss rate) can be impacted (i.e., increased or decreased) by the cache probe results and the newly allocated cache regions and cache lines and is therefore tracked with the cache probe) and adjusting the cache size by removing the portion of storage capacity previously added to the cache memory system (Faith column 4; lines 27-33, The HLL is able to perform this type of functionality in a very memory efficient way. Only a very small amount of memory is needed to implement a HLL that can represent an extremely large number of unique values. This permits the inventive approach to use very memory efficient HLL structures that can represent a large number of different cache sizes with great efficiency and effectiveness. The cache size can be adjusted based on the cache probe and associated hit/miss rate, also see Faith column 4; lines 40-46, FIG. 1B shows a high-level flowchart of some embodiments of the invention. At 180, a set of different cache sizes are selected for analysis. This list of sizes represents the set of cache sizes for which it is desired to identify MRC values, and therefore represents possible expectant cache sizes to implement for the system).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse with those of Faith. Faith is added to explicitly teach the concept of using different cache sizes as a means to improve the function of the cache memory system. The concept of using a cache probe including hit/miss data to improve the cache function through different cache sizes would have been obvious to add to the teachings of Greathouse (Faith column 10; lines 39-50, The MRC values can be organized and analyzed in any suitable way. For example, as illustrated in FIG. 7, the MRC values can be graphed to their cache size values. This helps to identify the relative costs and benefits of the different cache sizes, particularly as they pertain to the miss rates. A specific cache value can then be selected to optimize the size of the cache relative to a desired miss rate level. In the example of FIG. 7, one might wish to choose 32 as the cache size that is large enough to provide significant performance benefits, without requiring excessive allocation of cache storage).
Claims 7 are the corresponding method claim to the non-transitory computer-readable medium claim 14. It is rejected with the same references and rationale.
Claim(s) 2, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Greathouse in view of Faith in further view of Durnov in further view of Gupta as applied to claims 1, 8 and 15 above, and further in view of Barczak (US Publication No. 2019/0095336 -- "Barczak").
Regarding claim 9, Greathouse in view of Faith in further view of Durnov in further view of Gupta and in further view of Barczak teaches The computer program product of claim 8, wherein the cache memory system includes one or more of: a metadata cache and a user data cache (Barczak paragraphs [0076-0077], From a performance standpoint, the baseline is provided by caching with no classification—usually a LRU policy; see for example FIG. 1B. The classification provided by the filesystem scanner 226 allows distinguishing I/O meaning by corresponding I/O classes. A user (or a cache analytics with auto-tuning) may configure the cache engine as desired by setting the cache policy and the I/O classes as desired. According to some aspects, the executed operations described above allow, for example, to store most required and hot data (e.g., filesystem metadata) in the cache, e.g., in the cache device 204 (also referred to as cache storage device 204). I/Os 230 from the guest application 536a may be handled without changing already cached data classification and may be passed to the primary storage 502 in the case that no classification is available from the filesystem scanner 226. The cache can be used to store both metadata and user data depending upon the executed/requested operations).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Greathouse, Faith and Durnov and Gupta with those of Barczak. Barczak teaches a cache memory system including both a metadata and a user cache, which provides additional flexibility and optimization for the cache storage depending upon particular I/O requests and required features/characteristics (Barczak paragraphs [0053-0054], Illustratively, the cache processor 208 provides one or more cache policies that define rules to determine whether the request 230 (e.g., an I/O request) can be satisfied using a cached copy of the requested data or file (e.g., using the cache storage device 204). If this is not the case, the request 230 is satisfied using the storage device 202. Since, according to some aspects, the request 230 is received without a classification tag (also referred to as hint) related to the respective one or more cache policies, the filesystem scanner 226 may be used to provide one or more classification tags 226c, e.g., as a lookup table, that allows a classification of the request 230. Upon receiving a specific request 230, the cache processor 208 may be configured to check whether a classification tag 226c corresponding to the specific request 230 (also referred to as corresponding generated classification tag) is provided by the filesystem scanner 226, and if this is the case, the request 230 can be handle according to the one or more cache policies based on the corresponding classification tag).
Claims 2 and 16 are the corresponding method and system claims to the non-transitory computer-readable medium claim 9. They are rejected with the same references and rationale.
Response to Arguments
Applicant's arguments filed August 29th, 2025 have been fully considered but they are not persuasive.
Applicant argues:
“As shown above in the cited portions of Gupta, while Gupta may teach determining a size change and various counters for the cache optimization module, and the equal adjustment of partition size decreases based on multiple cache partition sizes, the combination of Greathouse, Faith, Durnov, and Gupta does not teach determining a change in IO pattern associated with the cache size adjustment impact, and, in response to determining the change, adjusting the cache size by rolling back the portion of storage capacity previously removed from the cache memory system. Gupta’s adjustment of partition size decrease in paragraph [0052] does not appear to be in response to a change in the IO pattern, but is based on other partition size decreases for other cache partitions. This is independent of any changes to the IO pattern. As such, Applicant respectfully submits that the combination of Greathouse, Faith, Durnov, and Gupta fails to teach or suggest all of the features of Applicant’s independent claim 1.
The addition of Barczak does not appear to, and has not been asserted to, remedy the deficiencies of the combination of Greathouse, Faith, Durnov, and Gupta. In consideration of the foregoing, Applicant respectfully submits that the cited references are not understood to teach or suggest all of the features of Applicant’s independent claim 1. Further, since Applicant’s independent claims 8 and 15 include similar limitations to independent claim 1, Applicant respectfully submits that claims 8 and 15 are in condition for allowance as well. Since the remaining dependent claims depend, either directly or indirectly, from Applicant’s independent claims 1, 8 and 15.”
The examiner respectfully disagrees. Regarding the applicant’s arguments towards independent claims 1, 8 and 15, specifically regarding the Gupta reference, the examiner asserts that the Gupta reference sufficiently discloses the concept of rolling back cache size storage capacity. In the Gupta reference, a means of resizing a cache partition based on various cache partition statistics (i.e., read hit ratios for example), wherein the partition size can be decreased or increased. In this case, Gupta explicitly describes a rolling adjustment, wherein the process of cache size adjustment and subsequent readjustment occurs repeatedly, with each subsequent readjustment factoring in the size change effect on the cache partition statistics being measured. In the specific cited claim section, the examiner asserts that Gupta describes a cache size being increased through the rollback of previously deallocated cache partition sections (i.e., see Gupta paragraph [0052] as cited in the rejection above. Further details regarding the allocation of storage memory as cache partitions can also be seen in the Gupta reference, such as Gupta paragraph [0003], Cache memories can be implemented as multi-level caches. For example, a cache memory system may include both “primary” and “secondary” caches. When reading data, a computing system or device may first look for data in the primary cache and, if the data is not located, look for it in the secondary cache. If the data is not in either cache, the computing system or device may retrieve the data from disk drives or other backend storage devices that reside behind the cache. When writing data, a computing system or device may write data to the primary cache. This data may subsequently be moved, or destaged, to the secondary cache or a storage device to free up memory space in the primary cache). In light of the above arguments and rationale, the applicant’s arguments are not considered persuasive and the corresponding 35 USC 103 Rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.C.K./ Examiner, Art Unit 2136
/KENNETH M LO/ Supervisory Patent Examiner, Art Unit 2136
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