Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment filed 10/29/2025. In the instant amendment, claims 1-5, 9-13, 17-18 and 20 were amended; claims 1, 9 and 17 are independent claims; Claims 1-20 are pending in this application. THIS ACTION IS MADE FINAL.
Response to Arguments
The claim objection to claim 17 has been withdrawn.
The claim interpretation under 35 U.S.C. 112(f) has been withdrawn.
Applicant’s arguments with respect to claims 1, 9 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594) and further in view of Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) and further in view of Kim et al (“Kim,” US 9,515,520).
Regarding claim 1, Cosgrove discloses a method for managing operation of data processing systems, the method comprising:
during a first period of time while a data processing system is inactive: (Cosgrove, [0044] describes during a first period of time [0048] while a data processing system [0068] of the data processing systems [0068] is powered off or intentionally disconnected [inactive] [0157])
identifying a time for the occurrence; (Cosgrove, [0044] describes identifying a time for the occurrence [0241], [0048])
during a second period of time while the data processing system is active: (Cosgrove, [0044] describes during a second period of time [0048] while the data processing system is running [active]: [0077])
providing, based on the occurrence and the time, a first report to a processing circuit of the data processing system, the first report indicating that an intrusion has occurred; (Cosgrove, [0004] describes providing, based on the occurrence and the time [0044], a first report [0244] to a processing circuit [0085] of the data processing system [0068], the first report [0244] indicating that an intrusion has occurred [0046])
providing, based on the occurrence and the time, a second report to a management control circuit of the data processing system, the second report indicating that the intrusion has occurred; and (Cosgrove, [0004] describes providing, based on the occurrence and the time [0048], a second report [0244], [0004] to a management control circuit [0367] of the data processing system [0068], the second report [0244] indicating that the intrusion has occurred [0046])
performing a first action set based on at least one of the first report and the second report to mitigate a threat presented by the intrusion, (Cosgrove, [0004] describes performing a first action set [0063] based on at least one of the first report [0244] and the second report [0244] to mitigate a threat [0004] presented by the intrusion [0046])
Cosgrove fails to explicitly disclose identifying, using disconnect circuitry and a monitor, an occurrence of a detachment of a secure control module of the data processing system from a host processor module of the data processing system.
However, in an analogous art, Shibata discloses identifying, using disconnect circuitry and a monitor, an occurrence of a detachment of a secure control module of the data processing system from a host processor module of the data processing system, (Shibata, [0007] describes identifying, using disconnect circuitry and a monitor, an occurrence of a detachment of a Trusted Platform Module [secure control module] of the data processing system [0012] from a CPU [host processor module] [0023] of the data processing system [0012])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shibata with the method and system of Cosgrove to include identifying, using disconnect circuitry and a monitor, an occurrence of a detachment of a secure control module of the data processing system from a host processor module of the data processing system. One would have been motivated to an authentication function for providing a computer with a highly reliable authentication function based on TCPA (Trusted Computing Platform Alliance) specifications or an authentication function providing method (Shibata, [0001]).
Cosgrove and Shibata fail to explicitly disclose wherein the disconnect circuitry comprises a regulator configured to regulate a power level of a power supply of the data processing system based on a power level of a backup power supply.
However, in an analogous art, Kim discloses wherein the disconnect circuitry comprises a regulator configured to regulate a power level of a power supply of the data processing system based on a power level of a backup power supply, (Kim discloses wherein the disconnect circuitry (Col. 1, Lines 56-64; Col. 3, Lines 56-61; Col. 4, Lines 1-10) comprises a regulator configured (Col. 4, Lines 39-41) to regulate a power level of a power supply of the data processing system (Col. 1, Lines 56-64; Col. 2, Lines 3-9; Col. 3, Lines 12-21; Col. 4, Lines 39-41) based on a power level of a backup power supply (Col. 4, Lines 22-38; Col. 2, Lines 35-56)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the method and system of Cosgrove and Shibata to wherein the disconnect circuitry comprises a regulator configured to regulate a power level of a power supply of the data processing system based on a power level of a backup power supply. One would have been motivated to provide battery backup in a power system based on voltage feed-forward control (Kim, Col. 1, Lines 7-9).
Regarding claim 9, claim 9 is directed to a non-transitory machine-readable medium. Claim 9 is similar in scope to claim 1 and is therefore rejected under the same rationale.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) in view of Kim et al (“Kim,” US 9,515,520) and further in view of Uehara et al (“Uehara,” US 20140230024).
Regarding claim 2, Cosgrove, Shibata and Kim disclose the method of claim 1.
Cosgrove and Shibata fail to explicitly disclose wherein the first report and the second report are provided by the monitor, the host processor module comprises the processing circuit, and the secure control module comprises the management control circuit.
However, in an analogous art, Uehara discloses wherein the first report and the second report are provided by the monitor, the host processor module comprises the processing circuit, and the secure control module comprises the management control circuit, (Uehara, [0267] describes wherein the first report and the second report are provided by the monitor [0252], the CPU [host processor module] [0062] comprises the processor [processing circuit] [0012], and the trusted platform module [secure control module] [0062] comprises the baseboard management control circuit [management control circuit] [0062])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Uehara with the method and system of Cosgrove, Shibata and Kim to include wherein the first report and the second report are provided by the monitor, the host processor module comprises the processing circuit, and the secure control module comprises the management control circuit. One would have been motivated to safely distribute a virtual computer on a cloud computing platform and authenticate a virtual computer (Uehara, [0002]).
Regarding claim 10, claim 10 is directed to the non-transitory machine-readable medium of claim 9. Claim 10 is similar in scope to claim 2 and is therefore rejected under the same rationale.
Claims 3-5 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) in view of Kim et al (“Kim,” US 9,515,520) and further in view of Kanarellis et al (“Kanarellis,” WO 2019060786).
Regarding claim 3, Cosgrove, Shibata and Kim disclose the method of claim 1.
Cosgrove, Shibata and Kim fail to explicitly disclose further comprising: during a third period of time: monitoring the power level of the backup power supply to the disconnect circuitry and the monitor; and obtaining, from the monitor, an indication that the monitor has reset; and in a first instance of the monitoring where the power level of the backup power supply exceeds a threshold: performing a second action set to mitigate a threat presented by a second intrusion.
However, in an analogous art, Kanarellis discloses further comprising:
during a third period of time: monitoring a power level of a backup power supply used to operate the disconnect circuitry and the monitor; (Kanarellis, [72] describes during a third period of time [69]: monitoring a power level [188], [103] of a backup power supply [111] used to operate the disconnect circuitry [110] and the monitor [111], [206])
and obtaining, from the monitor, an indication that the monitor has reset; (Kanarellis, [88] describes and obtaining, from the monitor [206], an indication that the monitor [206] has reset [06])
and in a first instance of the monitoring where the power level of backup power supply exceeds a threshold: performing a second action set to mitigate a threat presented by a second intrusion, (Kanarellis, [72] describes and in a first instance of the monitoring where the power level [188], [103] of backup power supply [111] exceeds a threshold [189]: performing a second action set to mitigate [232] a threat presented by a second intrusion [232], [142])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanarellis with the method and system of Cosgrove, Shibata and Kim to include further comprising: during a third period of time: monitoring a power level of a backup power supply used to operate the disconnect circuitry and the monitor; and obtaining, from the monitor, an indication that the monitor has reset; and in a first instance of the monitoring where the power level exceeds a threshold: performing a second action set to mitigate a threat presented by a second intrusion. One would have been motivated to supply uninterruptible power to a Power over Ethernet (PoE) device (Kanarellis, [03]).
Regarding claim 4, Cosgrove, Shibata and Kim disclose the method of claim 3.
Cosgrove, Shibata and Kim fail to explicitly disclose further comprising: during the third period of time: in a second instance of the monitoring where the power level of the backup power supply does not exceed the threshold: performing a third action set based on a conclusion that the backup power supply ran out of power.
However, in an analogous art, Kanarellis discloses further comprising: during the third period of time: in a second instance of the monitoring where the power level of the backup power supply does not exceed the threshold (Kanarellis, [69], [72] describes during the third period of time: in a second instance of the monitoring [111] where the power level [188] of the backup power supply [111] does not exceed the threshold [0132])
performing a third action set based on a conclusion that the backup power supply ran out of power, (Kanarellis, [103] describes performing a third action set based on a conclusion that the backup power supply [111] ran out of power [132])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanarellis with the method and system of Cosgrove, Shibata and Kim to include further comprising: during the third period of time: in a second instance of the monitoring where the power level does not exceed the threshold: performing a third action set based on a conclusion that the backup power supply ran out of power. One would have been motivated to supply uninterruptible power to a Power over Ethernet (PoE) device (Kanarellis, [03]).
Regarding claim 5, Cosgrove, Shibata and Kim disclose the method of claim 4.
Cosgrove, Shibata and Kim fail to explicitly disclose wherein the backup power supply comprises a battery, and the disconnect circuitry and the monitor are redundantly powered by the backup power supply and the power supply of the data processing system.
However, in an analogous art, Kanarellis discloses wherein the backup power supply comprises a battery, and the disconnect circuitry and the monitor are redundantly powered by the backup power supply and the power supply of the data processing system., (Kanarellis, [33] describes wherein the backup power supply comprises a battery [78], and the disconnect circuitry [110] and the monitor [206] are redundantly powered [232] by the backup power supply [33] and a power supply [232] of the data processing system [04])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanarellis with the method and system of Cosgrove, Shibata and Kim to include wherein the backup power supply comprises a battery, and the disconnect circuitry and the monitor are redundantly powered by the backup power supply and the power supply of the data processing system. One would have been motivated to supply uninterruptible power to a Power over Ethernet (PoE) device (Kanarellis, [03]).
Regarding claim 11, claim 11 is directed to the non-transitory machine-readable medium of claim 9. Claim 11 is similar in scope to claim 3 and is therefore rejected under the same rationale.
Regarding claim 12, claim 12 is directed to the non-transitory machine-readable medium of claim 11. Claim 12 is similar in scope to claim 4 and is therefore rejected under the same rationale.
Regarding claim 13, claim 13 is directed to the non-transitory machine-readable medium of claim 12. Claim 13 is similar in scope to claim 5 and is therefore rejected under the same rationale.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) in view of Kim et al (“Kim,” US 9,515,520) and further in view of Pachoud et al (“Pachoud,” US 20210076529).
Regarding claim 6, Cosgrove, Shibata and Kim disclose the method of claim 5.
Cosgrove, Shibata and Kim fail to explicitly disclose wherein the disconnect circuitry comprises a sensing loop distributed over the host processor module and the secure control module.
However, in an analogous art, Pachoud discloses wherein the disconnect circuitry comprises a sensing loop distributed over the host processor module and the secure control module, (Pachoud, [0027] describes wherein the disconnect circuitry [0027] comprises a sensing loop [0474] distributed over the CPU [host processor module] [0152] and the secure control module [0248], [0384)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pachoud with the method and system of Cosgrove, Shibata and Kim to include wherein the disconnect circuitry comprises a sensing loop distributed over the host processor module and the secure control module. One would have been motivated to supply power in data center environments (Pachoud, [0002]).
Regarding claim 14, claim 14 is directed to the non-transitory machine-readable medium of claim 13. Claim 14 is similar in scope to claim 6 and is therefore rejected under the same rationale.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) in view of Kim et al (“Kim,” US 9,515,520) and further in view of Ward et al (“Ward,” US 20210281553).
Regarding claim 7, Cosgrove, Shibata and Kim disclose the method of claim 1.
Cosgrove, Shibata and Kim fail to explicitly disclose wherein the first action set is performed by the secure control module, and the method further comprises: performing, by the host processing module, a second action set based on at least one of the first report and the second report to mitigate the threat presented by the intrusion.
However, in an analogous art, Ward discloses wherein the first action set is performed by the secure control module, and the method further comprises: performing, by the host processing module, a second action set based on at least one of the first report and the second report to mitigate the threat presented by the intrusion (Ward, [0031] describes wherein the first action set [0028] is performed by the trusted platform module [secure control module], and the method further comprises: performing, by the CPU [host processing module] [0109], a second action set [0028] based on at least one of the first report and the second report [0028] to mitigate the threat presented by the intrusion [0103], [0069])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ward with the method and system of Cosgrove, Shibata and Kim to include wherein the first action set is performed by the secure control module, and the method further comprises: performing, by the host processing module, a second action set based on at least one of the first report and the second report to mitigate the threat presented by the intrusion. One would have been motivated to provide evaluation and generation of attestation information within a network enclave to assess the reliability and trustworthiness of networking and computing devices operating within the network enclave (Ward, [0001]).
Regarding claim 8, Cosgrove, Shibata and Kim disclose the method of claim 7.
Ward further discloses wherein the first action set and the second action set are different from one another, (Ward, [0103] describes wherein the first action set [0102] and the second action set are different from one another [0028], [0100])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ward with the method and system of Cosgrove, Shibata and Kim to include wherein the first action set and the second action set are different from one another. One would have been motivated to provide evaluation and generation of attestation information within a network enclave to assess the reliability and trustworthiness of networking and computing devices operating within the network enclave (Ward, [0001]).
Regarding claim 15, claim 15 is directed to the non-transitory machine-readable medium of claim 9. Claim 15 is similar in scope to claim 7 and is therefore rejected under the same rationale.
Regarding claim 16, claim 16 is directed to the non-transitory machine-readable medium of claim 15. Claim 16 is similar in scope to claim 8 and is therefore rejected under the same rationale.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594) in view of Kim et al (“Kim,” US 9,515,520) and further in view of Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8).
Regarding claim 17, Cosgrove discloses a data processing system, comprising:
a secure control module; (Cosgrove, [0239] describes a secure control module)
a host processor module (Cosgrove, [0240] describes a central processing unit [host processor module])
a disconnection monitoring system comprising a monitor and disconnect circuitry, wherein the disconnection monitoring system is adapted to: (Cosgrove, [0240] a disconnection monitoring system [0157] comprising a monitor [0106] and disconnection circuitry [0240] describes wherein the disconnection monitoring system is adapted to [0157])
during a first period of time while the secure control module and the host processor module are inactive: (Cosgrove, [0044] describes during a first period of time while the secure control module and the host processor [0240] are [0068] is powered off or intentionally disconnected [inactive])
identifying a time for the occurrence; (Cosgrove, [0044] describes identifying a time for the occurrence [0241], [0048])
during a second period of time while the secure control module and the host processor module are active: (Cosgrove, [0044] describes during a second period of time while [0048] the secure control module [0239] and the host processor module [0240] are active)
providing, based on the occurrence and the time, a first report to a processing circuit of the host processor module, the first report indicating that an intrusion has occurred; and (Cosgrove, [0004] describes providing, based on the occurrence [0241], [0048] and the time [0044], a first report [0244] to a processing circuit [0085] of the host processor module [0240], the first report [0244] indicating that an intrusion has occurred [0046])
providing, based on the occurrence and the time, a second report to a management control circuit of the secure control module, the second report indicating that the intrusion has occurred, (Cosgrove, [0004] describes providing, based on the occurrence [0241], [0048] and the time [0044], a second report [0244] to a management control circuit [0367] of the secure control module [0239], the second report [0244] indicating that the intrusion has occurred, [0046])
wherein the processing circuit and the management control circuit are adapted to perform actions sets based on the first report or the second report to mitigate a threat presented by an intrusion of the data processing system, (Cosgrove, [0004] describes wherein the processing circuit [0085] and the management control circuit [0367] are adapted to perform actions sets [0063] based on the first report [0244] or the second report [0244] to mitigate a threat [0004] presented by an intrusion [0046] of the data processing system [0068])
using the monitor and the disconnect circuitry, (Cosgrove, describes using a monitor [0106] and disconnect circuitry [0240])
Cosgrove fails to explicitly disclose wherein the disconnect circuitry comprises a regulator configured to regulate a power level of a power supply of the data processing system based on a power level of a backup power supply.
However, in an analogous art, Kim discloses wherein the disconnect circuitry comprises a regulator configured to regulate a power level of a power supply of the data processing system based on a power level of a backup power supply (Kim discloses wherein the disconnect circuitry (Col. 1, Lines 56-64; Col. 3, Lines 56-61; Col. 4, Lines 1-10) comprises a regulator configured (Col. 4, Lines 39-41) to regulate a power level of a power supply of the data processing system (Col. 1, Lines 56-64; Col. 2, Lines 3-9; Col. 3, Lines 12-21; Col. 4, Lines 39-41) based on a power level of a backup power supply (Col. 4, Lines 22-38; Col. 2, Lines 35-56)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the method and system of Cosgrove to include wherein the disconnect circuitry comprises a regulator configured to regulate a power level of a power supply of the data processing system based on a power level of a backup power supply. One would have been motivated to provide battery backup in a power system based on voltage feed-forward control (Kim, Col. 1, Lines 7-9).
Cosgrove and Kim fail to explicitly disclose identifying, an occurrence of a detachment of the secure control module from the host processor module.
However, in an analogous art, Shibata discloses identifying, an occurrence of a detachment of the secure control module from the host processor module; (Shibata, [0007] describes identifying, an occurrence of a detachment of a Trusted Platform Module [secure control module] of the data processing system [0012] from a CPU [host processor module] [0023] of the data processing system [0012])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shibata with the method and system of Cosgrove and Kim to include identifying, an occurrence of a detachment of the secure control module from the host processor module. One would have been motivated to an authentication function for providing a computer with a highly reliable authentication function based on TCPA (Trusted Computing Platform Alliance) specifications or an authentication function providing method (Shibata, [0001]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Kim et al (“Kim,” US 9,515,520) in view of Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) and further in view of Sudhaus et al (“Sudhaus,” WO 2023089066, See Google Patents Translation).
Regarding claim 18, Cosgrove, Kim and Shibata disclose the data processing system of claim 17.
Cosgrove, Kim and Shibata fail to explicitly disclose wherein the monitor is adapted to identify the occurrence based on a voltage; and the disconnect circuitry is adapted to modulate the voltage based on a connection state of the secure control module and the host processor module.
However, in an analogous art, Sudhaus discloses wherein the monitor is adapted to identify the occurrence based on a voltage; (Sudhaus, Page 3, Lines 5-6 describes wherein the disconnect monitoring system comprises: a monitor Page 7, Lines 23-24 is adapted to identify the occurrence based on a voltage Page 8, Lines 3-4)
and the disconnect circuitry is adapted to modulate the voltage based on a connection state of the secure control module and the host processor module, (Sudhaus, Page 3, Lines 5-6 describes and disconnect circuitry is adapted to modulate the voltage Page 75, Lines 11-18 based on a connection state Page 8, Lines 5-10 of the secure module [secure control module] Page 98, Lines 8-14 and the CPU [host processor module] Page 5, Lines 24-25)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sudhaus with the method and system of Cosgrove, Kim and Shibata to include wherein the monitor is adapted to identify the occurrence based on a voltage; and the disconnect circuitry is adapted to modulate the voltage based on a connection state of the secure control module and the host processor module. One would have been motivated to modulate the voltage (Sudhas, Page 75, Lines 11-18).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Kim et al (“Kim,” US 9,515,520), Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8) in view of Sudhaus et al (“Sudhaus,” WO 2023089066) and further in view of Pachoud et al (“Pachoud,” US 20210076529).
Regarding claim 19, Cosgrove, Kim, Shibata and Sudhaus disclose the data processing system of claim 18.
Cosgrove, Kim, Shibata and Sudhaus fail to explicitly disclose wherein the disconnect circuitry comprises: a sensing loop distributed over the host processor module and the secure control module.
However, in an analogous art, Pachoud discloses wherein the disconnect circuitry comprises: a sensing loop distributed over the host processor module and the secure control module (Pachoud, [0027] describes wherein the disconnect circuitry [0027] comprises a sensing loop [0474] distributed over the CPU [host processor module] [0152] and the secure control module [0248], [0384)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pachoud with the method and system of Cosgrove, Kim, Shibata and Sudhaus to include wherein the disconnect circuitry comprises a sensing loop distributed over the host processor module and the secure control module. One would have been motivated to supply power in data center environments (Pachoud, [0002]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cosgrove et al (“Cosgrove,” US 20220360594), Kim et al (“Kim,” US 9,515,520), Shibata et al (“Shibata,” JP 2004282391, See Google Patents Translation of JP2004282391, Pages 1-8), Kim et al (“Kim,” US 9,515,520) in view of Sudhaus et al (“Sudhaus,” WO 2023089066) and further in view of Kanarellis et al (“Kanarellis,” WO 2019060786).
Regarding claim 20, Cosgrove, Kim, Shibata and Sudhaus disclose the data processing system of claim 18.
Cosgrove, Kim, Shibata and Sudhaus fail to explicitly disclose wherein the disconnect circuitry and the monitor are redundantly powered by the backup power supply and the power supply.
However, in an analogous art, Kanarellis discloses wherein the disconnect circuitry and the monitor are redundantly powered by the backup power supply and the power supply., (Kanarellis, describes the disconnect circuitry [110] and the monitor [206] are redundantly powered [232] by the backup power supply [33] and a power supply [232] of the data processing system [04])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kanarellis with the method and system of Cosgrove, Kim, Shibata and Sudhaus to include further comprising: a power supply; and a backup power supply comprising a battery, wherein the disconnect circuitry and the monitor are redundantly powered by the backup power supply and the power supply. One would have been motivated to supply uninterruptible power to a Power over Ethernet (PoE) device (Kanarellis, [03]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES J WILCOX whose telephone number is (571)270-3774. The examiner can normally be reached M-F: 8 A.M. to 5 P.M..
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/JAMES J WILCOX/Examiner, Art Unit 2439
/LUU T PHAM/Supervisory Patent Examiner, Art Unit 2439