DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application. Claims 1-4, 6-10, 12, 14-17, and 19 are amended. Claims 5, 11, 13, 18, and 20 are original.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Response to Arguments
Applicant’s arguments, see Remarks page 15, filed 12/29/25, with respect to the rejections of claims 1, 7, and under 102 (a)(1) and 102 (a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Zerbe et al. (US 20060170453 A1).
Response to Amendment
Amendments to the specification and drawings are considered. The amendments to the specification regarding informalities of par [0035] and [0055] are sufficient to overcome the specification objections. However, they are not sufficient to overcome the drawing objections and 35 U.S.C. 112(b) rejection of claims 1-20 of the previous office action dated 09/25/25, therefore the drawing objections/rejection remain.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
a pass transistor including a plurality of transistors in parallel configured to receive said bus voltage and provide an output voltage and an output current to a load of claim 1
a pass transistor with a plurality of transistors coupled in parallel configured to receive said bus voltage and provide an output voltage and an output current to a load of claim 7
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, lines 3-4, the phrase "a pass transistor including a plurality of transistors coupled in parallel" is unclear because a single transistor (i.e., "a pass transistor") cannot include a plurality of transistors. Par [0034] "the pass transistor 770 in the post regulator 730 would likely be made up of multiple devices operating in parallel (e.g., a transistor circuit)" and Par [0053] "at least one switch (770) such as a transistor circuit (e.g., including a plurality of transistors)" provides clarity to what the applicant means by the claim limitation in the phrase. For purpose of examination, the examiner interprets the claim limitation to recite a pass transistor circuit including a plurality of transistors coupled in parallel.
Regarding claims 2-6, they are rejected for the same reason as claim 1 above.
Regarding independent claims 7 and 14, they are rejected for the same reason as claim 1 above.
Regarding claims 8-13 and 15-20 they are rejected for the same reason as claim 1 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20200073425 A1), hereinafter Wang and further in view of Zerbe et al. (US 20060170453 A1), hereinafter Zerbe.
Regarding claim 1, Wang discloses a post regulator (fig 2, 204) for use with a power system (fig 2, multi-mode power supply circuit 200) including a power converter (fig 2, switched-mode power supply (SMPS) circuit 202 (e.g., a boost converter) configured to produce a bus voltage on an output bus (fig 2, MID_ELVDD voltage as the output voltage of SMPS 202; par [0027] “The various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.”), comprising: a pass transistor circuit (fig 2, circuit consisting of PMOS transistor 224) configured to receive said bus voltage (fig 2, the "LDO IN ELVDD" line serves as the input bus voltage for post regulator part of the circuit, which these transistors receive) and provide an output voltage and an output current to a load (fig 2, the primary function of this "Post Regulator" section (204) is to regulate and provide a stable "Vreg ELVDD" output voltage and current to the "To Panel" load); and a controller (fig 2, LDO_CTL 252 and Digital CTRL 260) configured to receive said bus voltage and control said pass transistor circuit (LDO_CTL 252 block receives the "high_psrr_ack" signal from the Envelope Detector (250) and directly controls the "LDO gate" which, in turn, controls the pass transistor (224) within the Post Regulator (204). The LDO_CTL also receives "LDO Bypass" and "LDO NPM" signals from the Digital CTRL (260). The post regulator's input, "LDO_IN_ELVDD", is connected to the output of the SMPS 202) to alter said output voltage of said post regulator for a period of time to enhance a slew rate of said output current or said output voltage (par [0030]) of said post regulator from a first level to a second level (par [0030], [0042], and [0046]; the text directly confirms that the digital controller is configured to manage and enhance the slew rate during transitions, which applies to both output voltage and current of the post regulator. Slew rate enhancement circuits are specifically designed to improve the transient response and speed of voltage or current changes during load transitions).
Wang discloses the pass transistor circuit as noted above but fails to disclose that the pass transistor circuit includes a plurality of transistors coupled in parallel.
Zerbe discloses a pass transistor circuit (fig 15, e.g., circuit including pass transistors 682-1 and 682-2) having plural pass transistors (i.e., 682-1, 682-2) coupled in parallel is conventional in the art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have optionally replaced the pass transistor circuit of Wang with the pass transistor circuit of Zerbe (i.e., having the plural pass transistors) in order to provide improved circuit reliability and redundancy for current flow.
Regarding claim 2, Wang and Zerbe disclose the post regulator as recited in Claim 1 wherein said pass transistor circuit is configured to block a difference between said bus voltage and said output voltage (Wang fig 2, pass transistor 224 (modified with plurality of transistors such as configured in Zerbe) is configured to "block" (or rather, drop) the difference between the input voltage (from the bus/SMPS) and the desired output voltage, thereby regulating the output voltage. In a linear regulator like an LDO, this transistor acts as the "pass element" or "series pass transistor" because it is connected in series between the input (LDO IN ELVDD) and the output (Vreg ELVDD). The input to the post regulator, LDO IN ELVDD, comes from the SMPS 202 and is typically higher than the desired regulated output, Vreg ELVDD. The pass transistor 224 is actively controlled by the feedback loop (involving the error amplifier and control circuit) to create a voltage drop across itself that precisely accounts for the difference between LDO IN ELVDD and Vreg ELVDD, ensuring Vreg ELVDD remains constant despite variations in the input or load.).
Regarding claim 3, Wang and Zerbe disclose the post regulator as recited in Claim 1 wherein said controller is configured to control said pass transistor circuit to boost said output voltage of said post regulator for said period of time to enhance said slew rate of said output current or said output voltage of said post regulator from said first level to said second level (Wang par [0008], [0039] and [0079]; “means for temporarily increasing a regulation point of the means for regulating the voltage to be higher than the voltage from the means for supplying power; and means for decreasing the regulation point of the means for regulating the voltage, after a delay.” explicit mention of controlling "timing and/or slew rate of the headroom adjustment to achieve smooth mode transitions" confirms the controller's capability and intent to manage the speed of voltage/current changes; regulating the voltage can also be referred to as boost or reduce).
Regarding claim 4, Wang and Zerbe disclose the post regulator as recited in Claim 3 wherein said controller is configured to control said pass transistor circuit to reduce said output voltage of said post regulator for a period of time to enhance said slew rate of said output current or said output voltage of said post regulator from said second level to said first level (Wang par [0008], [0039] and [0079]; “means for temporarily increasing a regulation point of the means for regulating the voltage to be higher than the voltage from the means for supplying power; and means for decreasing the regulation point of the means for regulating the voltage, after a delay.” explicit mention of controlling "timing and/or slew rate of the headroom adjustment to achieve smooth mode transitions" confirms the controller's capability and intent to manage the speed of voltage/current changes; regulating the voltage can also be referred to as boost or reduce).
Regarding claim 5, Wang and Zerbe disclose the post regulator as recited in Claim 1 wherein a level of said alteration of said output voltage of said post regulator and said period of time are selected to accelerate transitioning said output current or said output voltage from said first level to said second level (Wang par [0053] “If VPH_PWR overshoots to a particular voltage level (e.g., 4.8 V) or above, the SMPS (e.g., the boost converter) may not be able to maintain regulation due, for example, to a minimum on-time (e.g., 12 ns as shown in FIG. 4) for the shunt transistor (e.g., transistor 211) in the SMPS topology. In this case, the VMID voltage (labeled “MID_ELVDD” in FIG. 2) will also overshoot as shown. With the assistance of the digital controller (e.g., digital control circuit 260), when this condition is detected, the switching frequency may be immediately decreased (as illustrated by the switching frequency clock signal labeled “SW_CLK”) to have equivalently less duty cycle (as indicated by the Ramp signal in FIG. 4) and maintain the regulation. Meanwhile, the digital controller may enable an internal clamp circuit (as indicated by the clamp source select signal labeled “Clamp_SRC_SEL,” the clamp voltage signal, and the Vc signal) to allow the analog circuitry to have faster recovery. Similar, but opposite behavior may be used on the exit edge when VPH_PWR returns to normal voltage levels (e.g., the switching frequency is increased”).
Regarding claim 6, Wang and Zerbe disclose the post regulator as recited in Claim 1 wherein said controller is configured to control said pass transistor circuit responsive to a control signal from a host system (Wang fig 1, wireless device 100; par [0027] “ the various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.”; PMIC 124 of fig 1 is further detailed as multi-mode power supply circuit 200 in fig 2; digital control 260 receives control signals via the control signal bus from the wireless device 100 which may be a host system).
Regarding claim 7, Wang and Zerbe disclose a power system (Wang fig 2, 200), comprising: a power converter (Wang fig 2, 202) configured to produce a bus voltage on an output bus (Wang fig 2, MID_ELVDD voltage as the output voltage of SMPS 202; par [0027] “The various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.”) in response to a first control signal generated by a host system (Wang par [0059] “Two signals are employed to detect a high VPH_PWR event: (1) Vph_high is used to warm up the analog circuitry or tell the digital controller to keep the post regulator (e.g., LDO) in NPM if the post regulator has been in NPM; and (2) Vph_higher is used to determine whether a real high VPH_PWR event is occurring.”); and a post regulator (Wang fig 2, 204) coupled to said power converter (Wang fig 2, 202), including a pass transistor (Wang fig 2, 224 modified with plurality of pass transistors in parallel as in Zerbe) with a plurality of transistors coupled in parallel (Wang fig 2, 214 and 245) configured to receive said bus voltage (Wang fig 2, the "LDO IN ELVDD" line serves as the input bus voltage for post regulator part of the circuit, which these transistors receive) and provide an output voltage and an output current to a load (Wang fig 2, the primary function of this "Post Regulator" section (204) is to regulate and provide a stable "Vreg ELVDD" output voltage and current to the "To Panel" load), and a controller (Wang fig 2, LDO_CTL 252 and Digital CTRL 260) configured to receive said bus voltage and control said pass transistor circuit (Wang LDO_CTL 252 block receives the "high_psrr_ack" signal from the Envelope Detector (250) and directly controls the "LDO gate" which, in turn, controls the pass transistor (224) within the Post Regulator (204). The LDO_CTL also receives "LDO Bypass" and "LDO NPM" signals from the Digital CTRL (260). The post regulator's input, "LDO_IN_ELVDD", is connected to the output of the SMPS 202) to alter said output voltage of said post regulator for a period of time to enhance a slew rate of said output current or said output voltage (Wang par [0030]) of said post regulator from a first level to a second level (Wang par [0030], [0042], and [0046]; the text directly confirms that the digital controller is configured to manage and enhance the slew rate during transitions, which applies to both output voltage and current of the post regulator. Slew rate enhancement circuits are specifically designed to improve the transient response and speed of voltage or current changes during load transitions).
Regarding claim 8, Wang and Zerbe disclose the power system as recited in Claim 7 wherein said pass transistor circuit is configured to block a difference between said bus voltage and said output voltage (Wang fig 2, pass transistor 224 is configured to "block" (or rather, drop) the difference between the input voltage (from the bus/SMPS) and the desired output voltage, thereby regulating the output voltage. In a linear regulator like an LDO, this transistor acts as the "pass element" or "series pass transistor" because it is connected in series between the input (LDO IN ELVDD) and the output (Vreg ELVDD). The input to the post regulator, LDO IN ELVDD, comes from the SMPS 202 and is typically higher than the desired regulated output, Vreg ELVDD. The pass transistor 224 is actively controlled by the feedback loop (involving the error amplifier and control circuit) to create a voltage drop across itself that precisely accounts for the difference between LDO IN ELVDD and Vreg ELVDD, ensuring Vreg ELVDD remains constant despite variations in the input or load.).
Regarding claim 9, Wang and Zerbe disclose the power system as recited in Claim 7 wherein said controller is configured to control said pass transistor circuit to boost said output voltage of said post regulator for said period of time to increase said slew rate of said output current or said output voltage of said post regulator from said first level to said second level (Wang par [0008], [0039] and [0079]; “means for temporarily increasing a regulation point of the means for regulating the voltage to be higher than the voltage from the means for supplying power; and means for decreasing the regulation point of the means for regulating the voltage, after a delay.” explicit mention of controlling "timing and/or slew rate of the headroom adjustment to achieve smooth mode transitions" confirms the controller's capability and intent to manage the speed of voltage/current changes; regulating the voltage can also be referred to as boost or reduce).
Regarding claim 10, Wang and Zerbe disclose the power system as recited in Claim 9 wherein said controller is further configured to control said pass transistor circuit to reduce said output voltage of said post regulator for a period of time to reduce said slew rate of said output current or said output voltage of said post regulator from said second level to said first level (Wang par [0008], [0039] and [0079]; “means for temporarily increasing a regulation point of the means for regulating the voltage to be higher than the voltage from the means for supplying power; and means for decreasing the regulation point of the means for regulating the voltage, after a delay.” explicit mention of controlling "timing and/or slew rate of the headroom adjustment to achieve smooth mode transitions" confirms the controller's capability and intent to manage the speed of voltage/current changes; regulating the voltage can also be referred to as boost or reduce).
Regarding claim 11, Wang and Zerbe disclose the power system as recited in Claim 7 wherein a level of said alteration of said output voltage of said post regulator and said period of time are selected to accelerate transitioning said output current or said output voltage from said first level to said second level (Wang par [0053]).
Regarding claim 12, Wang and Zerbe disclose the power system as recited in Claim 7 wherein said controller is configured to control said pass transistor circuit responsive to a second control signal from said host system (Wang fig 1, wireless device 100; par [0027] “ the various components of the device 100 may be coupled together by a bus system 126, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus.”; PMIC 124 of fig 1 is further detailed as multi-mode power supply circuit 200 in fig 2; digital control 260 receives control signals via the control signal bus from the wireless device 100 which may be a host system).
Regarding claim 14, it is the method version of claim 7 above and is rejected for the same reasons as stated above.
Regarding claim 15, it is the method version of claim 8 above and is rejected for the same reasons as stated above.
Regarding claim 16, it is the method version of claim 9 above and is rejected for the same reasons as stated above.
Regarding claim 17, it is the method version of claim 10 above and is rejected for the same reasons as stated above.
Regarding claim 18, it is the method version of claim 11 above and is rejected for the same reasons as stated above.
Regarding claim 19, it is the method version of claim 12 above and is rejected for the same reasons as stated above.
Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US20200073425A1) and Zerbe as applied to claim 7 above, and further in view of Sato (US8681511B2).
Regarding claim 13, Wang and Zerbe disclose the power system as recited in Claim 7. Wang and Zerbe do not disclose wherein said power converter is an alternating current to direct current power converter.
Sato discloses a conventional three-phase AC-DC converter. Sato discloses power converter (fig 2) is an alternating current to direct current power converter (fig 2, three phase AC power supply 1; col 3 lines 41-42 “circuit diagram showing an AC-DC converter device”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wang and incorporate the AC-DC converter as taught by Sato. The advantage of this design to include alternating to direct current conversion device to convert alternating-current power into isolated direct-current power.
Regarding claim 20, it is the method version of claim 13 above and is rejected for the same reasons as stated above.
Conclusion
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838