The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I, Species III, and Claims 1-10 in the reply filed on 7/24/2024 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 22 recites ‘wherein the first and second busbars are each in a single plane’, which does not make sense since all physical components are in three-dimensional space, while a plane is only two dimensional. So any physical object is in multiple planes.
For purposes of this action, claim 22 is understood to mean that each of the first and second busbar is in a plane (could be two different planes)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka (US 6255672 B1, hereinafter Yoshioka) in view of Kosuga (US 9750147 B2, hereinafter Kosuga), further in view of Yokomae (US 20080087994 A1, hereinafter Yokomae)
Claim 1. Yoshioka teaches an apparatus comprising:
first and second planar terminals (10a, 10b)
However Yoshioka fails to teach a plurality of semiconductor devices;
a capacitor; and
first and second planar terminals electrically connected to the capacitor
Kosuga teaches a plurality of semiconductor devices (300a-c, 301a-c, fig 11);
a capacitor (514, fig 9b); and
first and second planar terminals (portions of 505, 507 which match 503a-f) electrically connected to the capacitor (col 12 lines 1-2 indicate that 503a-f are capacitor terminals while bridging paragraph between cols 11, 12 indicate that 505, 507, 503a-f are configured to reduce inductance)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of reducing inductance (Kosuga (col 12 lines 1-5).
However one could also argue that Yoshioka fails to teach first and second busbars
Yokomae teaches busbar (25, figs 7)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yokomae into the device of Yoshioka and Kosuga. The ordinary artisan would have been motivated to modify Yoshioka and Kosuga in the above manner for the purpose of connecting more semiconductors to each planar terminal (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’).
Claim 2. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, Kosuga further comprising a plurality of capacitors (514, fig 9b), wherein the first and second planar terminals are electrically connected to each of the plurality of capacitors (comparing figs 9a, 9b shows that 505 and 507 are connected to 503a-f).
Claim 3. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein each of the first and second planar terminals comprises a respective sheet (top sheet of 10a, 10b, Yoshioka fig 4; also see sheet shape of Kosuga elements 505, 507 of fig 9b) that extends between the capacitor (as taught my Kosuga and would be to the left of Yoshioka fig 4) and the plurality of semiconductor devices (Yoshioka fig 4).
Claim 4. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 3, wherein Yoshioka further teaches at least one of the sheets has a step shape (10b, fig 4) to provide a first contact plane on a far side of the capacitor (as taught my Kosuga and would be to the left of Yoshioka fig 4).
Claim 5. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 4, wherein Kosuga further teaches the other of the sheets also has a step shape (fig 9b) to provide a second contact plane on a near side of the capacitor (fig 9b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of having a compact design.
Claim 6. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein each of the first planar terminal and the second planar terminal is a single piece conductive sheet (Yoshioka fig 4, Kosuga fig 9b).
Claim 7. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein at least a portion of the second planar terminal (Kosuga 505, figs 9a, 9b) overlays on top of the at least a portion of the first planar terminal (Kosuga 507) with only a planar material electrical insulation layer (Kosuga 550, figs 9a, 9b, col 11 lines 18-24 recite ‘laminated conductive plate 501 is configured of a negative electrode conductive plate 505 and a positive electrode conductive plate 507 which are formed of a plate-like wide conductor, and an insulating sheet 550 which is held by the negative electrode conductive plate 505 and the positive electrode conductive plate 507’) without holes directly between the portion of the first planar terminal and the portion of the second planar terminal (Kosuga fig 9b shows 550 is directly between 505, 507 and that 550 does not have holes between 505, 507), and wherein the portion of the second planar terminal and the portion of the first planar terminal are not covered with laminate material (since figs 9a, 9b of Kosuga shows that 505, 507 are not covered except with the insulating sheet 550 between them).
Claim 8. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein Yoshioka further teaches at least a portion of the first planar terminal (Yoshioka 10b) and at least a portion of the second planar terminal (Yoshioka 10a) are stacked in a direction that is normal to the substrate (vertical direction of Yoshioka fig 4) such that the first planar terminal (Yoshioka 10b) overlays on top of the second planar terminal (Yoshioka 10a) before a turn associated with a step shape of
However Yoshioka fails to specifically teach the first planar terminal overlays on top of the second planar terminal before a turn associated with a step shape of both the first planar terminal and the second planar terminal
Kosuga teaches a first planar terminal (505, fig 9b) overlays on top of a second planar terminal (507, fig 9b) before a turn associated with a step shape of both the first planar terminal and the second planar terminal (see annotated fig 9b below)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of having a compact design.
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Claim 9. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 8, wherein at least a portion of the first planar terminal and at least a portion of the second planar terminal are stacked in a direction that is parallel to the substrate (vertical direction of fig 4 of Yoshioka and vertical direction of Kosuga fig 9b) such that the first planar terminal overlays the second planar terminal after the turn associated with the step shape of both the first planar terminal and the second planar terminal (see also Kosuga fig 9b).
Claim 10. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 8, wherein the first planar terminal overlays the second planar terminal throughout the turn associated with the step shape (Kosuga fig 9b).
Claim 22. Yoshioka in view of Kosuga further in view of Yokomae teaches the method of claim 1, wherein the first and second busbars (two separate instances of element 25 of Yokomae figs 7) are soldered to the first and second semiconductor circuits (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’), respectively, and the first and second planar terminals (10a, 10b of Yoshioka matching two separate instances of 15 of Yokomae) are welded to the first and second busbars ([0096] recites ‘conductor plate 15 is welded onto the projecting portion 25b of the metallic plate 25 by laser welding’), respectively, wherein the first and second busbars are each in a single plane (since they have flat parts that lie in a single plane, see Yoshioka fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yokomae into the device of Yoshioka and Kosuga. The ordinary artisan would have been motivated to modify Yoshioka and Kosuga in the above manner for the purpose of connecting more semiconductors to each planar terminal (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’ while [0096] recites ‘conductor plate 15 is welded onto the projecting portion 25b of the metallic plate 25 by laser welding’).
Claim 23. Yoshioka teaches a semiconductor apparatus comprising:
a first planar terminal (10a, fig 4) abutting the first busbar of
a second planar terminal (10b) comprising:
a contact portion (bottom portion of 10b of fig 4) of the second planar terminal abutting the second busbar (fig 4) of
wherein the first planar terminal and the main portion of the second planar terminal are stacked (fig 4) such that the second planar terminal overlays on top of the first planar terminal (fig 4)
However Yoshioka fails to teach a plurality of semiconductor devices;
a capacitor; and
first and second planar terminals electrically connected to the capacitor
Kosuga teaches a plurality of semiconductor devices (300a-c, 301a-c, fig 11);
a capacitor (514, fig 9b); and
first and second planar terminals (portions of 505, 507 which match 503a-f) electrically connected to the capacitor (col 12 lines 1-2 indicate that 503a-f are capacitor terminals while bridging paragraph between cols 11, 12 indicate that 505, 507, 503a-f are configured to reduce inductance)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of reducing inductance (Kosuga (col 12 lines 1-5).
However one could also argue that Yoshioka fails to teach first and second busbars
Yokomae teaches busbar (25, figs 7)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yokomae into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of connecting more semiconductors to each planar terminal (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’ while [0096] recites ‘conductor plate 15 is welded onto the projecting portion 25b of the metallic plate 25 by laser welding’).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka (US 6255672 B1, hereinafter Yoshioka) in view of Kosuga (US 9750147 B2, hereinafter Kosuga), further in view of Yokomae (US 20080087994 A1, hereinafter Yokomae), further in view of AAPA (Applicant Admitted Prior Art)
Claim 21. Yoshioka in view of Kosuga further in view of Yokomae teaches the method of claim 1, wherein the second planar terminal (Yoshioka 10b) abuts a first end of the second busbar (2b, Yoshioka fig 4) of each of the plurality of semiconductor devices,
However Yoshioka in view of Kosuga further in view of Yokomae fails to specifically teach the first end of the second busbar extends beyond the substrate
AAPA teaches a first end of the second busbar extends beyond the substrate ([0017] of the instant specification recites ‘In a conventional IGBT …. one busbar end is on the substrate and the other end extends beyond the edge of the substrate’)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by AAPA into the device of Yoshioka in view of Kosuga further in view of Yokomae. The ordinary artisan would have been motivated to modify Yoshioka in view of Kosuga further in view of Yokomae in the above manner for the purpose of improving heat dissipation by having a larger conductor.
Examiner Notes
Examiner cites particular elements, columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Arguments
Applicant's arguments filed 1/23/2025 have been fully considered but they are not found persuasive.
Applicant argues:
‘Thus, component 2b is described in the specification of Yoshioka as being an emitter electrode that is a part of IGBT (1b) and component 9a as being a collector electrode that is a part of IGBT (1a) and are not the first busbar or second busbar as alleged in the Office Action. The emitter electrode and the collector electrode are thin films of a conductive material deposited on top of one of the layers in a transistor, such as the IGBT. The Office Action does not mention how the collector electrode 9a is interpreted to be the recited first busbar and the emitter electrode 2b to be the second busbar since the collector and emitter components are only described as being portions of the IGBT device. The collector electrode is adjacent a p-type substrate formed in the main body of the transistor and the emitter is adjacent an n+ region and a p-type region as is known for IGBT devices.’
A busbar is essentially a conductor, and the electrodes of Yoshioka are essentially conductors. The term “busbar” has substantial overlap with the term “electrode”. Applicants instant specification at [0017] recites ‘In a conventional IGBT …. These busbars are usually parallel to each other’, which indicates that having busbars in an IGBT is common.
Applicant argues:
‘Applicant respectfully submits that there is no reason to modify any of the gate, emitter and collector electrodes in Yoshioka to be a busbar, even if busbars may be known from other art because there is no reason to do such a modification on a device that isn't connecting to anything else. There is no reason to substitute the electrode in Yoshioka with a busbar on a single device configuration that doesn't need to feed other devices.’
This cannot be found persuasive because the device of Yoshioka is meant to connect to other devices. It does not make sense for the electrical component of Yoshioka to not be connecting to anything else – even if the Yoshioka reference does not specify what it is connected to – one of ordinary skill in the art understands that Yoshioka is meant to be connected to something else.
Applicants specification at [0017] indicates Applicant Admitted Prior Art that is similar to the 103 rejection by stating ‘In operation, current flows into the semiconductor device through one of the busbars, passes through the silicon dies, and flows out of the device through the other busbar’.
Applicant argues:
‘Applicant respectfully submits that Kosuga does not teach planar terminals as explained by the Office. The Office does not use the component names that the Kosuga reference uses:’
The component names of the reference(s) are not required to match the language of the claims for a proper rejection. The issue is what the claims read on and what the references teach.
Applicant argues:
‘The Office refers to components 505, 507 as the terminals (rather than the plates as described by Kosuga). Each terminal 508 and 509 has multiple bends; plates 505, 507 each have a step and then a relay conductive section 530 and capacitor terminals 503a-f. Terminals 508 and 509 are side by side as seen in Figure 9A, and do not overlay as recited in Claim 1. Thus, the elements identified in Kosuga are not terminals, they are plates. The Office has not met their burden because the elements listed are not terminals.’
Terminals and plates are not mutually exclusive. Terminals can be plates and plates can be terminals. The term “plate” indicates a physical shape while the term “terminal” indicates electrical flow between components or from an end point.
Electricity can flow through a metal shaped into a plate. The plate will also have endpoints connected to other components when that happens.
Applicants argue in response to claim 7:
‘Applicant has amended Claim 7 to recite in part (enphasis added) "with only a planar material electrical insulation layer without holes directly between the portion of the first planar terminal and the portion of the second planar terminal, and wherein the portion of the second planar terminal and the portion of the first planar terminal are not covered with laminate material" to distinguish over the insulating material 550 having multiple bends (not planar) and holes (circles indicated on 550) as indicated in Fig. 9B. The Office admits above to the 'laminated conductive plate 501'. Thus, each and every feature of Claim 7 is not disclosed by the art.’
Claim 7 indicates a portion of the first/second planar terminals, while a portion of element 550 of Kosuga fig 9b is planar and between the terminals. Although element 550 may have holes, those holes are not between the portions of 505 and 507. Although 550 has circles aligned with holes of 505, 507 – those circles are not directly between the portions of 505 and 507 since the portions of 505, 507 are the metal portions and not the empty holes.
Although element 550 has step shapes, those step shapes are not between the portions of 505 and 507.
Claim 7 requires for an electrical insulation layer directly between portions of the first and second planar terminals. The Kosuga reference shows no indication of a laminate material covering element 505 from above, and no indication of a laminate material covering element 507 from below. Kosuga does teach electrical insulation layer 550 directly between portions of elements 505, 507 as required by claim 7.
The Merriam-Webster dictionary definition for laminate is included below
laminate
1 of 3
verb
lam·i·nate ˈla-mə-ˌnāt
laminated; laminating
transitive verb
1: to roll or compress into a thin plate
2: to separate into laminae
3a: to make (something, such as a windshield) by uniting superposed layers of one or more materials
b: to unite (layers of material) by an adhesive or other means
Since Claim 7 requires for an electrical insulation layer directly between portions of the first and second planar terminals, it is required for the first and second planar terminals to be at least partly covered with a laminate material. The last limitation of Claim 7 could cause a 112 2nd issue, or could be read broadly as meaning not externally covered with laminate material. The claim requires a laminate material on the inside, sandwiched between the planar terminals, and requires that the planar terminals are not sandwiched by a laminate material.
Applicant argues in response to claim 8 similarly as above in regards to the Kosuga reference using the term plate instead of terminal. The labels that the reference applies to the elements are not required to match the exact language of the claims for a proper rejection. The physical structure that Kosuga teaches matches the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS R BURTNER whose telephone number is (571)272-0966. The examiner can normally be reached on M-F 9-5.
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/DOUGLAS R BURTNER/ Examiner, Art Unit 2841 /ROCKSHANA D CHOWDHURY/Primary Examiner, Art Unit 2841