The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I, Species III, and Claims 1-10 in the reply filed on 7/24/2024 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the ‘one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices’ of claims 1, 23 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
Previous 112 rejection withdrawn.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10, 21-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The independent claims require “wherein one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices”, however this is not clearly described in the originally filed drawings or written description. [0017] mentions that ‘each of the busbars is positioned on top of two of the silicon dies so that one busbar end is on the substrate and the other end extends beyond the edge of the substrate’. However, as explained in the 112(b) rejection below, the claimed semiconductor device is not the same as the claimed substrate or semiconductor circuit.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 requires “a plurality of semiconductor devices each comprising a substrate, first and second semiconductor circuits on the substrate, and first and second busbars abutting the first and second semiconductor circuits, respectively” which means that the busbars are a part of the semiconductor devices, although different from the semiconductor circuits. Claim 1 also requires “wherein one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices”. Since the busbars are a part of the semiconductor devices, the busbars cannot extend beyond the semiconductor devices, because then the semiconductor devices would extend beyond themselves.
Perhaps claim 1 should require “wherein one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor circuits ”.
Claim 23 has a similar situation.
Claims 2-10, 22-23 are rejected for depending upon an indefinite claim.
Claim Objections
As a suggestion, it might be better to amend claim 22 to recite “wherein the first and second busbars are coplanar”, for simplicity.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka (US 6255672 B1, hereinafter Yoshioka) in view of Kosuga (US 9750147 B2, hereinafter Kosuga), further in view of Yokomae (US 20080087994 A1, hereinafter Yokomae), still further in view of Applicant Admitted Prior Art (hereinafter AAPA)
Claim 1. Yoshioka teaches an apparatus comprising:
first and second planar terminals (10a, 10b) wherein the second planar terminal (10b) abuts the second busbar (2b) of
However Yoshioka fails to teach a plurality of semiconductor devices;
a capacitor; and
first and second planar terminals electrically connected to the capacitor
Kosuga teaches a plurality of semiconductor devices (300a-c, 301a-c, fig 11);
a capacitor (514, fig 9b); and
first and second planar terminals (portions of 505, 507 which match 503a-f) electrically connected to the capacitor (col 12 lines 1-2 indicate that 503a-f are capacitor terminals while bridging paragraph between cols 11, 12 indicate that 505, 507, 503a-f are configured to reduce inductance)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of reducing inductance (Kosuga (col 12 lines 1-5).
However one could also argue that Yoshioka fails to teach first and second busbars
Yokomae teaches busbar (25, figs 7)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yokomae into the device of Yoshioka and Kosuga. The ordinary artisan would have been motivated to modify Yoshioka and Kosuga in the above manner for the purpose of connecting more semiconductors to each planar terminal (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’).
Yoshioka, Kosuga and Yokomae fail to specifically teach wherein one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices
AAPA teaches one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices ([0017] recites ‘In a conventional IGBT …. each of the busbars is positioned on top of two of the silicon dies so that one busbar end is on the substrate and the other end extends beyond the edge of the substrate’)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by AAPA into the device of Yoshioka, Kosuga and Yokomae. The ordinary artisan would have been motivated to modify Yoshioka, Kosuga and Yokomae in the above manner for the purpose of having a larger conductor that will dissipate more heat.
Claim 2. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, Kosuga further comprising a plurality of capacitors (514, fig 9b), wherein the first and second planar terminals are electrically connected to each of the plurality of capacitors (comparing figs 9a, 9b shows that 505 and 507 are connected to 503a-f).
Claim 3. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein each of the first and second planar terminals comprises a respective sheet (top sheet of 10a, 10b, Yoshioka fig 4; also see sheet shape of Kosuga elements 505, 507 of fig 9b) without holes (Yoshioka figs 3, 7 show no holes in the top sheets of 10a, 10b) that extends between the capacitor (as taught by Kosuga and would be to the left of Yoshioka fig 4) and the plurality of semiconductor devices (Yoshioka fig 4).
Claim 4. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 3, wherein Yoshioka further teaches at least one of the sheets has a step shape (10b, fig 4) to provide a first contact plane on a far side of the capacitor (as taught my Kosuga and would be to the left of Yoshioka fig 4).
Claim 5. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 4, wherein Kosuga further teaches the other of the sheets also has a step shape (fig 9b) to provide a second contact plane on a near side of the capacitor (fig 9b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of having a compact design.
Claim 6. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein each of the first planar terminal and the second planar terminal is a single piece conductive sheet (Yoshioka fig 4, Kosuga fig 9b).
Claim 7. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein at least a portion of the second planar terminal (Kosuga 505, figs 9a, 9b) overlays on top of the at least a portion of the first planar terminal (Kosuga 507) with only a material electrical insulation layer (Kosuga 550, figs 9a, 9b, col 11 lines 18-24 recite ‘laminated conductive plate 501 is configured of a negative electrode conductive plate 505 and a positive electrode conductive plate 507 which are formed of a plate-like wide conductor, and an insulating sheet 550 which is held by the negative electrode conductive plate 505 and the positive electrode conductive plate 507’) in a single plane (Kosuga fig 9b shows a portion of 550 sandwiched between portions of 505, 507 without holes in the portions)without holes directly between the portion of the first planar terminal and the portion of the second planar terminal (Kosuga fig 9b shows 550 is directly between 505, 507 and that 550 does not have holes between 505, 507), and wherein the portion of the second planar terminal and the portion of the first planar terminal are not covered with laminate material (since figs 9a, 9b of Kosuga shows that 505, 507 are not covered except with the insulating sheet 550 between them).
Claim 8. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 1, wherein Yoshioka further teaches at least a portion of the first planar terminal (Yoshioka 10b) without holes and at least a portion of the second planar terminal (Yoshioka 10a) without holes are stacked in a direction that is normal to the substrate (vertical direction of Yoshioka fig 4) such that the first planar terminal (Yoshioka 10b) overlays on top of the second planar terminal (Yoshioka 10a) before a turn associated with a step shape of
However Yoshioka fails to specifically teach the first planar terminal overlays on top of the second planar terminal before a turn associated with a step shape of both the first planar terminal and the second planar terminal
Kosuga teaches a first planar terminal (505, fig 9b) overlays on top of a second planar terminal (507, fig 9b) before a turn associated with a step shape of both the first planar terminal and the second planar terminal (see annotated fig 9b below)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the step shape as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify element 10a of Kosuga fig 4 to have a step shape for the purpose of having a larger conductor that will dissipate more heat.
PNG
media_image1.png
1272
856
media_image1.png
Greyscale
Claim 9. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 8, wherein at least a portion of the first planar terminal and at least a portion of the second planar terminal are stacked in a direction that is parallel to the substrate (vertical direction of fig 4 of Yoshioka and vertical direction of Kosuga fig 9b) such that the first planar terminal overlays the second planar terminal after the turn associated with the step shape of both the first planar terminal and the second planar terminal (see also Kosuga fig 9b).
Claim 10. Yoshioka in view of Kosuga further in view of Yokomae teaches the apparatus of claim 8, wherein the first planar terminal overlays the second planar terminal throughout the turn associated with the step shape (Kosuga fig 9b).
Claim 22. Yoshioka in view of Kosuga further in view of Yokomae teaches the method of claim 1, wherein the first and second busbars (two separate instances of element 25 of Yokomae figs 7) are soldered to the first and second semiconductor circuits (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’), respectively, and the first and second planar terminals (10a, 10b of Yoshioka matching two separate instances of 15 of Yokomae) are welded to the first and second busbars ([0096] recites ‘conductor plate 15 is welded onto the projecting portion 25b of the metallic plate 25 by laser welding’), respectively, wherein the first busbar is in a first single plane and the second busbar is in a second single plane (since they have flat parts that lie in a single plane, see Yoshioka fig 4), and wherein the first and second single planes are coplanar (Yoshioka fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yokomae into the device of Yoshioka and Kosuga. The ordinary artisan would have been motivated to modify Yoshioka and Kosuga in the above manner for the purpose of connecting more semiconductors to each planar terminal (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’ while [0096] recites ‘conductor plate 15 is welded onto the projecting portion 25b of the metallic plate 25 by laser welding’).
Claim 23. Yoshioka teaches a semiconductor apparatus comprising:
a first planar terminal (10a, fig 4) abutting the first busbar of
a second planar terminal (10b) comprising:
a contact portion (bottom portion of 10b of fig 4) of the second planar terminal abutting the second busbar (fig 4) of
wherein the first planar terminal and the main portion of the second planar terminal are stacked (fig 4) such that the second planar terminal overlays on top of the first planar terminal (fig 4)
However Yoshioka fails to teach a plurality of semiconductor devices;
a capacitor; and
first and second planar terminals electrically connected to the capacitor
Kosuga teaches a plurality of semiconductor devices (300a-c, 301a-c, fig 11);
a capacitor (514, fig 9b); and
first and second planar terminals (portions of 505, 507 which match 503a-f) electrically connected to the capacitor (col 12 lines 1-2 indicate that 503a-f are capacitor terminals while bridging paragraph between cols 11, 12 indicate that 505, 507, 503a-f are configured to reduce inductance)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yoshioka into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of reducing inductance (Kosuga (col 12 lines 1-5).
However one could also argue that Yoshioka fails to teach first and second busbars
Yokomae teaches busbar (25, figs 7)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by Yokomae into the device of Kosuga. The ordinary artisan would have been motivated to modify Kosuga in the above manner for the purpose of connecting more semiconductors to each planar terminal (Yokomae [0094] recites ‘metallic plate 25 is laid across and soldered onto semiconductor elements 13a, 13b, 13c, and 13d via a solder 14 and bonded to the semiconductor plates 13a, 13b, 13c, and 13d by soldering’ while [0096] recites ‘conductor plate 15 is welded onto the projecting portion 25b of the metallic plate 25 by laser welding’)
Yoshioka, Kosuga and Yokomae fail to specifically teach wherein one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices
AAPA teaches one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices ([0017] recites ‘In a conventional IGBT …. each of the busbars is positioned on top of two of the silicon dies so that one busbar end is on the substrate and the other end extends beyond the edge of the substrate’)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by AAPA into the device of Yoshioka, Kosuga and Yokomae. The ordinary artisan would have been motivated to modify Yoshioka, Kosuga and Yokomae in the above manner for the purpose of having a larger conductor that will dissipate more heat.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka (US 6255672 B1, hereinafter Yoshioka) in view of Kosuga (US 9750147 B2, hereinafter Kosuga), further in view of Yokomae (US 20080087994 A1, hereinafter Yokomae), further in view of AAPA (Applicant Admitted Prior Art)
Claim 21. Yoshioka in view of Kosuga further in view of Yokomae teaches the method of claim 1, wherein the second planar terminal (Yoshioka 10b) abuts a first end of the second busbar (2b, Yoshioka fig 4) of each of the plurality of semiconductor devices,
However Yoshioka in view of Kosuga further in view of Yokomae fails to specifically teach the first end of the second busbar extends beyond the substrate
AAPA teaches a first end of the second busbar extends beyond the substrate ([0017] of the instant specification recites ‘In a conventional IGBT …. one busbar end is on the substrate and the other end extends beyond the edge of the substrate’)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the arrangement as taught by AAPA into the device of Yoshioka in view of Kosuga further in view of Yokomae. The ordinary artisan would have been motivated to modify Yoshioka in view of Kosuga further in view of Yokomae in the above manner for the purpose of improving heat dissipation by having a larger conductor.
Examiner Notes
Examiner cites particular elements, columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Response to Arguments
Applicant's arguments filed 1/23/2025 have been fully considered but they are not found persuasive.
Applicant argues:
‘The Office Action identifies component 9a of Yoshioka as being the first busbar and component 2b as being the second busbar.
However, column 4 of Yoshioka recites: "[a]n emitter electrode 2b on the upper surface of the second IGBT lb" and "[c]ollector electrodes 9a and 9b are respectively formed on the upper surface of the first IGBT la and the lower surface of the second IGBT lb."
Thus, component 2b is described in the specification of Yoshioka as being an emitter electrode that is a part of IGBT (1b) and component 9a as being a collector electrode that is a part of IGBT (1a), and are not the first busbar or second busbar as alleged in the Office Action. An electrode is a conductive object that serves as the point of contact between an electrical circuit and another medium. In electrical systems, it is the interface where current is applied to or removed from a device (here, the IGBT). That is, the IGBT electrodes are the connection points for current to enter or leave the IGBT. An electrode is a connection point in a circuit, and not a power distribution path. In direct contrast, a busbar is a physical conductor that is usually a metal strip or bar used to carry and distribute electrical current between different parts of a system. A busbar is a conductor and structural element that organizes and routes current in a compact, high current capacity way. To summarize, an electrode is about current entry/exit for the IGBT device, while a busbar is about current distribution. They are different components of the same system, but their roles are distinct: the electrode is the interface, and the busbar is the highway for power flow..’
The claims do not provide a current cut-off level for how many amps the bus bars carry.
A busbar is essentially a conductor, and the electrodes of Yoshioka are essentially conductors. The term “busbar” has substantial overlap with the term “electrode”. Applicants instant specification at [0017] recites ‘In a conventional IGBT …. These busbars are usually parallel to each other’, which indicates that having busbars in an IGBT is common.
Applicant argues:
‘The Office Action also identifies component 25 (Fig. 7) of Yokomae as disclosing the first and second busbars of Applicant's claim. The component 25 attaches to the four semiconductor elements 13a-d, and does not disclose Applicant's recited first and second busbars. A portion of paragraph [0095] describes the component 25 as follows:
Here, the metallic plate 25 is a three-dimensional block and has a projecting portions 25b at a higher level than upper end faces 25a provided in four directions of the metallic plate 25. Specifically, the metallic plate 25 has steps.
First, metallic plate does not disclose Applicant's recited first and second busbars. Second, the four portions 25a that contact the four semiconductor elements 13a-d do not extend beyond the edges of the semiconductors as seen in Fig. 7A of Yokomae. This in direct contrast to the feature of Applicant's Claim 1: "wherein one end of each of the first busbar and the second busbar of each of the plurality of semiconductor devices extends beyond an edge of the semiconductor devices." ’
The component names of the reference(s) are not required to match the language of the claims for a proper rejection. The issue is what the claims read on and what the references teach. A metal plate generally reads on a bus bar. In particular, this metal plate is for connecting between multiple semiconductors while the claimed invention only requires the bus bar to connect to one semiconductor. It makes sense that this metal plate is sufficient to conduct more electricity than in the instant application.
Applicants specification at [0017] indicates Applicant Admitted Prior Art that is similar to the 103 rejection by stating ‘In operation, current flows into the semiconductor device through one of the busbars, passes through the silicon dies, and flows out of the device through the other busbar’. The applied references are consistent with a bus bar even if they use different terminology. The claimed term “bus bar” does not overcome the prior art as a whole and the AAPA makes it clear that the usage of the term “bus bar” cannot be the reasons for allowance of the claims.
Applicant argues:
‘With respect to amended Claim 22, Applicant notes that the collector electrode (9a) and the emitter electrode (2b) of Yoshioka nor the metallic plate 25 of Yokomae do not have the recited properties of the recited first and second busbars, including that "the first busbar is in first single plane and the second busbar is in a second single plane" and wherein the first and second single planes are coplanar..’
Fig 4 of Yoshioka shows that elements 9a and 2b are coplanar.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS R BURTNER whose telephone number is (571)272-0966. The examiner can normally be reached on M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen Parker can be reached on 303-297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS R BURTNER/ Examiner, Art Unit 2841 /ROCKSHANA D CHOWDHURY/Primary Examiner, Art Unit 2841
Prosecution Insights