DETAILED ACTION
Election/Restriction
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-4 and 6-17, drawn to a system for adjusting a power supply control signal, classified in 702/99.
II. Claims 18-20, drawn to an amplifier and a transistor and an adjustable resistor, classified in 374/179.
The inventions are independent or distinct, each from the other because:
Inventions I and II are directed to related products. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed have a materially different design. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
each invention has attained recognition in the art as a separate subject for inventive effort, and also a separate field of search;
each invention can be shown to have formed a separate subject for inventive effort when the examiner can show a recognition of separate inventive effort by inventors; and
it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries).
Newly submitted claims 18-20 are directed to an invention that is independent or distinct from the invention originally claimed for the reasons set forth above.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 18-20 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6-9, 15, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-9, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Male, US 2007/0075398 A1 (hereinafter Male).
Regarding claim 1, Male teaches a system, comprising:
a resistor (20, Fig. 2);
interface circuitry coupled to the calibration resistor (12, 14, “The resistive heater element is energized and the pulse amplitude is controlled,” ¶ 0014);
a heater (25, Fig. 1); and
a processor coupled to the heater and to the interface circuit (12, 14, “The resistive heater element is energized and the pulse amplitude is controlled,” ¶ 0014), wherein the processor is configurable to:
retrieve a calibration value (“comparing initial current values with post-energizing current values,” ¶ 0020);
provide a power supply control signal to initiate a power pulse to the heater (“The resistive heater element is energized and the pulse amplitude is controlled, to provide a uniform and symmetrical thermal gradient, e.g., a local temperature between about 30 degrees Centigrade and about 60 degrees Centigrade above the average temperature of the chip,” ¶ 0014);
determine a resistance of the resistor using the interface circuitry (“the overall TCR of the resistance network 20 and the TCRs of resistance material segments 22 and 24 can be measured quickly at various temperatures,” ¶ 0038);
adjust the power supply control signal to change a voltage level or a duration of the power pulse responsive to a comparison between the calibration value and a value proportional to the resistance of the resistor (“The resistive heater element is energized and the pulse amplitude is controlled, to provide a uniform and symmetrical thermal gradient, e.g., a local temperature between about 30 degrees Centigrade and about 60 degrees Centigrade above the average temperature of the chip,” ¶ 0014, (“the overall TCR of the resistance network 20 and the TCRs of resistance material segments 22 and 24 can be measured quickly at various temperatures,” ¶ 0038).
Regarding claim 2, Male teaches the invention of claim 1, as set forth in the rejection of claim 1 above. Male also teaches the interface circuitry includes switches configurable to, when activated, allow injection of a pre-determined current into the resistor to measure the resistance of the resistor; and the processor is configurable to provide a calibration signal to activate the switches (“Referring to FIG. 1, there is shown circuitry for a high-precision, on-chip, bias current source 10 in accordance with the present invention,” ¶ 0026).
Regarding claim 3, Male teaches the invention of claim 1, as set forth in the rejection of claim 1 above. Male also teaches further comprising an adjustable resistance network coupled to the interface circuitry, wherein the adjustable resistance network includes first resistance segments (22, Fig. 2), and the calibration resistor includes second resistance segments thermally coupled to the first resistance segments (24, Fig. 2).
Regarding claim 4, Male teaches the invention of claim 3, as set forth in the rejection of claim 3 above. Male also teaches wherein the first resistance segments are disposed in one or more layers of an integrated circuit, and the second resistance segments are disposed in one or more layers (22 and 24 in at least one layer, Fig. 2).
Regarding claim 6, Male teaches the invention of claim 3, as set forth in the rejection of claim 3 above. Male also teaches wherein the first resistance segments are members of an array of physical resistance segments fabricated from a resistive material, and the second resistance segments are members of the array of physical resistance segments (both 22 and 24 are fabricated from resistive materials, Fig. 2).
Regarding claim 7, Male teaches the invention of claim 3, as set forth in the rejection of claim 3 above. Male also teaches wherein the second resistance segments and the first resistance segments are interdigitated (22 and 24 are interdigitated, Fig. 2).
Regarding claim 8, Male teaches the invention of claim 3, as set forth in the rejection of claim 3 above. Male also teaches wherein the second resistance segments and the first resistance segments are part of a common-centroid layout (22 and 24 are interdigitated as part of a common-centroid layout, Fig. 2).
Regarding claim 9, Male teaches a method, comprising:
instructing a power supply to provide a power pulse to a heater (“The resistive heater element is energized and the pulse amplitude is controlled, to provide a uniform and symmetrical thermal gradient, e.g., a local temperature between about 30 degrees Centigrade and about 60 degrees Centigrade above the average temperature of the chip,” ¶ 0014);
measuring a resistance of a resistor (“the overall TCR of the resistance network 20 and the TCRs of resistance material segments 22 and 24 can be measured quickly at various temperatures,” ¶ 0038);
obtaining a calibration value for the resistor, wherein the calibration value is proportional to a calibration temperature rise; and adjusting the power pulse based on a comparison between the calibration value and a value based on to the resistance (“Adjusting the overall TCR of the resistance network includes determining post-energizing current and resistance properties of each resistance material of the first and second plurality of segments; comparing initial current values with post-energizing current values; and adjusting the number of first and second resistance material segments in the "resistance mixture", ¶ 0020).
Regarding claim 15, Male teaches the invention of claim 9, as set forth in the rejection of claim 9 above. Male also teaches determining a temperature rise of an adjustable resistance network in response to heat generated by the heater; and storing a value indicative of the calibration temperature rise as the calibration value (“the overall TCR of the resistance network 20 and the TCRs of resistance material segments 22 and 24 can be measured quickly at various temperatures,” ¶ 0038 – that the measurements are made at various temperatures means the temperature must be known, which means the temperature rise is also known).
Regarding claim 16, Male teaches the invention of claim 9, as set forth in the rejection of claim 9 above. Male also teaches providing a calibration signal that activates switches to enable injection of a pre-determined current into the resistor to measure the resistance (“Referring to FIG. 1, there is shown circuitry for a high-precision, on-chip, bias current source 10 in accordance with the present invention,” ¶ 0026).
Allowable Subject Matter
Claims 10-14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEO T HINZE whose telephone number is (571)272-2864. The examiner can normally be reached M-Th 9-2.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephen Meier can be reached on (571)272-2149. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEO T HINZE/
Patent Examiner
AU 2853
03 April 2026
/STEPHEN D MEIER/ Supervisory Patent Examiner, Art Unit 2853