DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al (hereafter Tan)(US Pub. 20240171374) in view of Ruehle (US Pat. 6748412).
Ruehle was cited in the IDS filed 0`/30/2023
5. As to claim 1, Tan discloses a system (abstract), comprising a processor to:
receive a circuit with a plurality of Boolean variables to be simulated over real numbers ([0024] Boolean circuit with logic gates); encode the circuit using a negation-based encoding ([0024] negation functions);
execute AND operations in the encoded circuit by summing negated variables ([0032] and [0036]); reduce positive integers in results of the summed negated variables to a value of one ([0104] integers); and
negate the results with reduced positive integers to generate decoded results of the AND operations ([0085] and [0086] decoding).
6. Tan does not disclose detecting a chain of AND operations in the circuit. However, Ruehle discloses disclose detecting a chain of AND operations in the circuit (fig. 4 chain of AND flip flops).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Tan by incorporating the chain of AND operations, as in Ruehle, for the benefit of more efficient operation (Ruehle, column 9, lines 21-65).
7. As to claims 2, 9, and 16, the combination of Tan and Ruehle discloses the circuit is encoded using a fuzzy AND gate (Ruehle, fig. 4).
8. As to claims 3, 10, and 17 the combination of Tan and Ruehle discloses wherein the positive integers in the results are reduced using a compare method (Tan, [0104]-[0107]).
9. As to claims 4, 12, and 18, the combination of Tan and Ruehle discloses wherein the positive integers in the results are reduced using an equality operator (Tan [0106]).
10. As to claims 5, 13, and 19, the combination of Tan and Ruehle discloses wherein the processor is to analyze the circuit and identify a structure of ANDing the plurality of Boolean variables (Tan, [0024]).
11. As to claims 6, 14, and 20, the combination of Tan and Ruehle discloses wherein summing the negative variables uses only addition operations (Tan ([0032] and [0036]).
12. As to claims 7 and 11, the combination of Tan and Ruehle discloses wherein the AND operations are executed under homomorphic encryption (abstract homomorphic encryption).
13. As to claims 8 and 15, the claims are rejected for similar reasons as claim 1 above.
Conclusion
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. 20200213079 – related to systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL D. YAARY/Primary Examiner, Art Unit 2151
Prosecution Insights