DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 30 January 2023, 8 December 2023, and 9 May 2024 have been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-11, and 13 rejected under 35 U.S.C. 103 as being unpatentable over Yoshihiko et al. JP-2010200478-A (hereinafter Yoshihiko) in view of Hirasawa et al. JP-2018196205-A (hereinafter Hirasawa-18).
Regarding claim 1, Yoshihiko discloses (fig. 1-11) a semiconductor device comprising:
an elongated cooler through which a refrigerant flows (cooler 2 with cooling pipes 22, ¶20-22, 27-30, 35);
a plurality of semiconductor modules (21 ¶20), each including one or more semiconductor elements (¶36); and
a passive element (3 ¶21),
wherein:
the cooler includes:
a first cooling surface (220b/22 and 210 on top of each element 21 in cooling tube 22 ¶28, 45); and
a second cooling surface (220a/22 and 210 on bottom of each element 21 in cooling tube 22 ¶22, 28) opposing the first cooling surface (fig. 1),
the plurality of semiconductor modules (21) is arrayed in a longitudinal direction of the cooler and is coupled to, or is in contact with, the first cooling surface (each cooling surface 22 above modules 21 as shown in fig. 1), and
the passive element (3) is coupled to, or is in contact with, the second cooling surface (220b) (fig. 1).
Yoshihiko does not explicitly disclose that the passive element (3) is configured to drive the plurality of semiconductor modules. Yoshihiko discloses element 3 generates heat from being energized and is part of the same power conversion circuit as semiconductor elements 21.
In the same field of endeavor, Hirasawa-18 discloses (¶7, 14) that “reactor 3 is electrically connected to the semiconductor module 2” (Hirasawa-18 ¶14, where module 2 corresponds to semiconductor elements 21 of Yoshihiko).
It would have been obvious to one of ordinary skill in the art at the time of filing for the power conversion circuit to use the integrally installed element 3 as the powering unit to drive the plurality of semiconductor modules, simplifying the device structure by providing a shared cooling to both electrical portions of the device when engaged, reducing total device size.
Regarding claim 2, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 1,
further comprising:
a housing containing (300 Yoshihiko ¶19-26) the passive element (3 Yoshihiko ¶21), the cooler (cooler 2 with cooling pipes 22, Yoshihiko ¶20-22, 27-30, 35), and the plurality of semiconductor modules (21 Yoshihiko ¶20, 36),
wherein:
the housing includes a mounting surface on which the passive element is mounted (Yoshihiko ¶26 where element 3 can integrally attached to element 300 as part of the overall body/housing 100), and
a stacking direction of stacking of the passive element, the cooler, and the semiconductor module is parallel to the mounting surface (fig. 1-2, where stacked cooler 2, passive element 3, and modules 21 are parallel).
Regarding claim 3, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 2,
wherein a space is provided not only between the plurality of semiconductor modules and the mounting surface, but also between the cooler and the mounting surface (fig. 1 Yoshihiko¶57, where space between elements 21 is shown as cooling pipes 22, and inlet 230 and outlet 240 with gasket 303 show the space between the cooler and the mounting).
While Hirasawa-18 discloses an electrical connection between element 3 and the semiconductor modules, Yoshihiko in view of Hirasawa-18 does not explicitly disclose a conductor is positioned in the space, the conductor electrically connecting the plurality of semiconductor modules and the passive element to each other.
It would have been obvious to one of ordinary skill in the art at the time of filing for the electrical connection to passive element/reactor 3 to be located within the space between the cooler and the mounting surface, improving device reliability by providing cooling for the conductive connections as well as isolating the connections from risk of contact with the cooling fluid that could short the electrical connection.
Regarding claim 4, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 2,
wherein:
the passive element (3 Yoshihiko ¶21) includes:
a first element surface coupled to, or in contact with, the second cooling surface (220a, fig. 1); and
a second element surface that is one end surface of the passive element in the longitudinal direction of the cooler (surface opposite hole 301 in outlet 240 as shown in Yoshihiko fig.1),
the cooler includes:
a body (100 Yoshihiko ¶24-26) including the first cooling surface (23) and the second cooling surface (24); and
a first head (230 Yoshihiko ¶30) being in contact with a first end portion of the body (101 Yoshihiko ¶31), the first head including a flow path communicating with a flow path inside the body (Yoshihiko fig. 1, where the first head connects to the inlet flow coming through the first end portion of the body 101),
the first head includes a third cooling surface that is a plane facing the second element surface (Yoshihiko fig. 1, 4 where the plane is the housing 300 near the inlet and faces the left surface of element 3), and
the third cooling surface is coupled to, or is in contact with, the second element surface (Yoshihiko fig. 1, 4, where the third cooling surface contacts the second surface of element 3 through the housing 300).
Regarding claim 6, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 1,
wherein:
the cooler includes:
a first wall including the first cooling surface (Yoshihiko fig. 1, where the first wall is the left side along 23 within body 100);
a second wall including the second cooling surface (Yoshihiko fig. 1, where the second wall is the right side along the 24 within body 100 and including the housing 300 separated from element 3 by the hole 301); and
a flow path (L) through which the refrigerant flows, the flow path being positioned between the first wall and the second wall (Yoshihiko fig. 1, where the flow is between the left first wall and the second right wall along cooling pipes 22), and
the first wall is thinner than the second wall (Yoshihiko fig. 1, 4, where the left wall 100 is thinner than the right wall thickness labeled "300 (100)").
Regarding claim 7, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 1,
wherein
the cooler (22, Yoshihiko ¶20-22, 27-30, 35) includes:
a first wall including the first cooling surface (Yoshihiko fig. 1, where the first wall is the left side along the first cooling surface 23 within body 100);
a second wall including the second cooling surface (Yoshihiko fig. 1, where the second wall is the right side along the second cooling surface 24 within body 100);
a flow path (L) through which the refrigerant flows, the flow path being positioned between the first wall and the second wall (Yoshihiko fig. 1, where the flow is between the left first wall and the second right wall); and
a protrusion protruding from an inner wall surface of the first wall, the inner wall surface of the first wall opposing the first cooling surface (Yoshihiko fig. 1, where protrusions extend from the first wall at intervals matching the rows of semiconductor elements 21).
Regarding claim 8, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 1,
wherein:
the cooler includes:
a first flow path extending in the longitudinal direction of the cooler (Yoshihiko fig. 1 ¶30, where the path is shown with vertical arrow within hole 101 and the portion of flow L extending along the longitudinal direction through 23); and
a second flow path (4) extending in the longitudinal of the cooler (Yoshihiko fig. 1 ¶30, where the second path 4 extends out along the longitudinal direction near passive element 3),
the first flow path is closer to the plurality of semiconductor modules than the second flow path (Yoshihiko fig. 1, ¶30 where the outlet flow is specifically disclosed as downstream from the flow L as path 4 starting in hole 301 and further from the semiconductor elements), and
the refrigerant passes through the first flow path (L) to pass through the second flow path (4) (Yoshihiko fig. 1).
Regarding claim 9, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 1,
wherein:
a first flow path (Yoshihiko fig. 1 ¶30, where the first flow is the vertical portion of flow L within 23) extending in the longitudinal direction of the cooler;
a second flow path (4) extending in the longitudinal direction of the cooler (Yoshihiko fig. 1 ¶30, where the second path 4 extends out along the longitudinal direction near passive element 3); and
a plurality of third flow paths (flow L after leaving 23, Yoshihiko fig. 1) causes the first flow path and the second flow path to communicate with each other,
the plurality of third flow paths is arrayed in the longitudinal direction, each of the plurality of third flow paths extending in a direction perpendicular to the longitudinal direction (Yoshihiko fig. 1, where flow paths L pass through channels between semiconductor elements then combine and flow along the outlet longitudinal direction to communicate with path 4), and
the plurality of third flow paths is closer to the plurality of semiconductor modules than the first flow path and the second flow path are (Yoshihiko fig. 1, where the third flow paths L are directly passing over the walls containing elements 21).
Regarding claim 10, Yoshihiko discloses a semiconductor device comprising:
a semiconductor module including one or more semiconductor elements (21 ¶20, 36);
a cooler (stacked cooler 2 with cooling pipes 22, ¶20-22, 27-30, 35) configured to cool the semiconductor module (21);
a passive element (3 ¶21); and
a housing (100 ¶19-26) containing the semiconductor module, the cooler, and the passive element (fig. 1),
wherein:
the cooler includes:
a first cooling surface (220b/22 and 210 on top of each element 21 in cooling tube 22 ¶28, 45) on which the semiconductor module is mounted (fig. 1-2);
a second cooling surface (220a/22 and 210 on bottom of each element 21 in cooling tube 22 ¶22, 28) on which the passive element is mounted (fig. 1, where element 3 mounted on 220a); and
a fixed surface (300 ¶19-26) facing an interior wall of the housing, the fixed surface being fixed on the interior wall of the housing (fig. 1, where the fixed surface 300 is fixed to the bottom wall of the housing 101).
Yoshihiko does not explicitly disclose that the passive element (3) is electrically connected to the semiconductor modules. Yoshihiko discloses element 3 generates heat from being energized and is part of the same power conversion circuit as semiconductor modules.
In the same field of endeavor, Hirasawa-18 discloses (¶7, 14) that “reactor 3 is electrically connected to the semiconductor module 2” (Hirasawa-18 ¶14, where module 2 corresponds to semiconductor elements 21 of Yoshihiko).
It would have been obvious to one of ordinary skill in the art at the time of filing for the power conversion circuit to use the integrally installed element 3 as the powering unit to drive the plurality of semiconductor modules, simplifying the device structure by providing a shared cooling to both electrical portions of the device when engaged, reducing total device size.
Regarding claim 11, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 10,
wherein the first cooling surface (220b/22 and 210 on top of each element 21 in cooling tube 22 Yoshihiko ¶28, 45) is a surface opposing the second cooling surface (220a/22 and 210 on bottom of each element 21 in cooling tube 22 Yoshihiko ¶22, 28) (Yoshihiko fig. 1, where first cooling surfaces are the on the top opposite the second surfaces on the bottom).
Regarding claim 13, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 10,
wherein:
the cooler includes a refrigerant pipe into which a refrigerant flows or from which the refrigerant is drained (inlet 230 and outlet 240, Yoshihiko fig. 1, ¶21-23), and
the passive element includes:
a surface cooled by the second cooling surface (Yoshihiko fig. 1, where 220a supplies cooling to a surface of element 3); and
a surface adjacent to the surface cooled by the second cooling surface, the surface adjacent to the surface cooled by the second cooling surface being coupled to, or being in contact with, the refrigerant pipe (Yoshihiko fig. 1, 4 where an adjacent side is cooled through 300 in contact with the inlet 230).
Claims 5 and 12 rejected under 35 U.S.C. 103 as being unpatentable over Yoshihiko and Hirasawa-18 in view of Hirasawa et al. JP-2016139749-A (hereinafter Hirasawa-16).
Regarding claim 5, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 4,
wherein:
the passive element (3 Yoshihiko ¶21) further includes a third element surface opposing the second element surface (Yoshihiko fig. 1, where the third surface would be facing the outlet 240 opposite the second surface),
Yoshihiko in view of Hirasawa-18 does not disclose the cooler further includes a second head being in contact with a second end portion of the body, the second end portion of the body opposing the first end portion of the body, the second head including a flow path communicating with the flow path inside the body,
the second head includes a fourth cooling surface that is a plane facing the third element surface, and the fourth cooling surface is coupled to, or is in contact with, the third element surface.
In the same field of endeavor, Hirasawa-16 discloses (fig. 1-6) a stacked cooler in which the passive element 3 is within housing member (4) with first cooling surface (421), second and third cooling surfaces facing cooling connection pipes 52 on opposite sides (Hirasawa-16 fig 1, ¶25).
Hirasawa-16 further discloses the cooler further includes a second head (422 Hirasawa-16 fig. 1 ¶25) being in contact with a second end portion of the body (111 Hirasawa-16 ¶31), the second end portion of the body opposing the first end portion of the body (Hirasawa-16 fig. 1, where the first end portion contains the inlet and outlet connection pipes), the second head including a flow path communicating with the flow path inside the body (Hirasawa-16 fig. 1, where a cooling pipe 51, ¶25, 28-29, 34, is on the side of housing 4 connected to the second end of the body)
the second head includes a fourth cooling surface that is a plane facing the third element surface, and the fourth cooling surface is coupled to, or is in contact with, the third element surface (Hirasawa-16 fig. 1, where the fourth cooling surface plane is along the cooling pipe 51 shown on the second end of the body to cool element 3 and connects to pipe 52 along the third cooling surface for element 3).
It would have been obvious to one of ordinary skill in the art at the time of filing for cooling to applied to an additional surface of the passive element 3, improving device performance by maximizing the surface area of heat exchange for the heat generating element.
Regarding claim 12, Yoshihiko in view of Hirasawa-18 discloses the semiconductor device according to claim 10.
Yoshihiko in view of Hirasawa-18 does not disclose wherein the fixed surface is a surface adjacent to the first cooling surface. In the same field of endeavor, Hirasawa-16 discloses (fig. 1-5) wherein the fixed surface is a surface adjacent to the first cooling surface (where the stacked cooler has the passive element 3 opposite the inlet and outlet pipes with fixed element 4 located adjacent to a second cooling surface of the cooling pipe 51 at the second end 422 Hirasawa-16 fig. 1 ¶25).
It would have been obvious to one of ordinary skill in the art at the time of filing for the fixed surface holding the passive element to be placed with the second cooling surface on the outside of it, improving device performance by maximizing the surface area of heat exchange for the heat generating element.
Conclusion
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/Seth D Lawson/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893